Intel Intrinsics Guide

The Intel Intrinsics Guide is an interactive reference tool for Intel intrinsic instructions, which are C style functions that provide access to many Intel instructions - including Intel® SSE, AVX, AVX-512, and more - without the need to write assembly code.

Documentation version 3.4.6, from 07/15/2019.

This CHM was generated automatically by the tool. The source XML dataset is freely accessible on intel.com.


All

A B C D E F G H I L M O P R S T U W X Z

A

  • _mm_abs_epi8 Compute the absolute value of packed 8-bit integers in "a", and store the unsigned results in "dst"
  • _mm256_abs_epi8 Compute the absolute value of packed 8-bit integers in "a", and store the unsigned results in "dst"
  • _mm_abs_epi16 Compute the absolute value of packed 16-bit integers in "a", and store the unsigned results in "dst"
  • _mm256_abs_epi16 Compute the absolute value of packed 16-bit integers in "a", and store the unsigned results in "dst"
  • _mm_abs_epi32 Compute the absolute value of packed 32-bit integers in "a", and store the unsigned results in "dst"
  • _mm256_abs_epi32 Compute the absolute value of packed 32-bit integers in "a", and store the unsigned results in "dst"
  • _mm_abs_pi8 Compute the absolute value of packed 8-bit integers in "a", and store the unsigned results in "dst"
  • _mm_abs_pi16 Compute the absolute value of packed 16-bit integers in "a", and store the unsigned results in "dst"
  • _mm_abs_pi32 Compute the absolute value of packed 32-bit integers in "a", and store the unsigned results in "dst"
  • _mm_acos_pd Compute the inverse cosine of packed double-precision floating-point elements in "a" expressed in radians
  • _mm256_acos_pd Compute the inverse cosine of packed double-precision floating-point elements in "a"
  • _mm_acos_ps Compute the inverse cosine of packed single-precision floating-point elements in "a" expressed in radians
  • _mm256_acos_ps Compute the inverse cosine of packed single-precision floating-point elements in "a" expressed in radians
  • _mm_acosh_pd Compute the inverse hyperbolic cosine of packed double-precision floating-point elements in "a" expressed in radians
  • _mm256_acosh_pd Compute the inverse hyperbolic cosine of packed double-precision floating-point elements in "a" expressed in radians
  • _mm_acosh_ps Compute the inverse hyperbolic cosine of packed single-precision floating-point elements in "a" expressed in radians
  • _mm256_acosh_ps Compute the inverse hyperbolic cosine of packed single-precision floating-point elements in "a" expressed in radians
  • _mm_add_epi8 Add packed 8-bit integers in "a" and "b", and store the results in "dst"
  • _mm256_add_epi8 Add packed 8-bit integers in "a" and "b", and store the results in "dst"
  • _mm_add_epi16 Add packed 16-bit integers in "a" and "b", and store the results in "dst"
  • _mm256_add_epi16 Add packed 16-bit integers in "a" and "b", and store the results in "dst"
  • _mm_add_epi32 Add packed 32-bit integers in "a" and "b", and store the results in "dst"
  • _mm256_add_epi32 Add packed 32-bit integers in "a" and "b", and store the results in "dst"
  • _mm_add_epi64 Add packed 64-bit integers in "a" and "b", and store the results in "dst"
  • _mm256_add_epi64 Add packed 64-bit integers in "a" and "b", and store the results in "dst"
  • _mm_add_pd Add packed double-precision floating-point elements in "a" and "b"
  • _mm256_add_pd Add packed double-precision floating-point elements in "a" and "b"
  • _mm_add_pi8 Add packed 8-bit integers in "a" and "b", and store the results in "dst"
  • _mm_add_pi16 Add packed 16-bit integers in "a" and "b", and store the results in "dst"
  • _mm_add_pi32 Add packed 32-bit integers in "a" and "b", and store the results in "dst"
  • _mm_add_ps Add packed single-precision floating-point elements in "a" and "b"
  • _mm256_add_ps Add packed single-precision floating-point elements in "a" and "b"
  • _mm_add_sd Add the lower double-precision floating-point element in "a" and "b"
  • _mm_add_si64 Add 64-bit integers "a" and "b", and store the result in "dst".
  • _mm_add_ss Add the lower single-precision floating-point element in "a" and "b"
  • _addcarry_u32 Add unsigned 32-bit integers "a" and "b" with unsigned 8-bit carry-in "c_in" (carry flag), and store the unsigned 32-bit result in "out", and the carry-out in "dst" (carry or overflow flag)
  • _addcarry_u64 Add unsigned 64-bit integers "a" and "b" with unsigned 8-bit carry-in "c_in" (carry flag), and store the unsigned 64-bit result in "out", and the carry-out in "dst" (carry or overflow flag)
  • _addcarryx_u32 Add unsigned 32-bit integers "a" and "b" with unsigned 8-bit carry-in "c_in" (carry or overflow flag), and store the unsigned 32-bit result in "out", and the carry-out in "dst" (carry or overflow flag)
  • _addcarryx_u64 Add unsigned 64-bit integers "a" and "b" with unsigned 8-bit carry-in "c_in" (carry or overflow flag), and store the unsigned 64-bit result in "out", and the carry-out in "dst" (carry or overflow flag)
  • _mm_adds_epi8 Add packed 8-bit integers in "a" and "b" using saturation, and store the results in "dst"
  • _mm256_adds_epi8 Add packed 8-bit integers in "a" and "b" using saturation, and store the results in "dst"
  • _mm_adds_epi16 Add packed 16-bit integers in "a" and "b" using saturation, and store the results in "dst"
  • _mm256_adds_epi16 Add packed 16-bit integers in "a" and "b" using saturation, and store the results in "dst"
  • _mm_adds_epu8 Add packed unsigned 8-bit integers in "a" and "b" using saturation
  • _mm256_adds_epu8 Add packed unsigned 8-bit integers in "a" and "b" using saturation
  • _mm_adds_epu16 Add packed unsigned 16-bit integers in "a" and "b" using saturation
  • _mm256_adds_epu16 Add packed unsigned 16-bit integers in "a" and "b" using saturation
  • _mm_adds_pi8 Add packed 8-bit integers in "a" and "b" using saturation, and store the results in "dst"
  • _mm_adds_pi16 Add packed 16-bit integers in "a" and "b" using saturation, and store the results in "dst"
  • _mm_adds_pu8 Add packed unsigned 8-bit integers in "a" and "b" using saturation
  • _mm_adds_pu16 Add packed unsigned 16-bit integers in "a" and "b" using saturation
  • _mm_addsub_pd Alternatively add and subtract packed double-precision floating-point elements in "a" to/from packed elements in "b"
  • _mm256_addsub_pd Alternatively add and subtract packed double-precision floating-point elements in "a" to/from packed elements in "b"
  • _mm_addsub_ps Alternatively add and subtract packed single-precision floating-point elements in "a" to/from packed elements in "b"
  • _mm256_addsub_ps Alternatively add and subtract packed single-precision floating-point elements in "a" to/from packed elements in "b"
  • _mm_aesdec_si128 Perform one round of an AES decryption flow on data (state) in "a" using the round key in "RoundKey"
  • _mm_aesdeclast_si128 Perform the last round of an AES decryption flow on data (state) in "a" using the round key in "RoundKey"
  • _mm_aesenc_si128 Perform one round of an AES encryption flow on data (state) in "a" using the round key in "RoundKey"
  • _mm_aesenclast_si128 Perform the last round of an AES encryption flow on data (state) in "a" using the round key in "RoundKey"
  • _mm_aesimc_si128 Perform the InvMixColumns transformation on "a" and store the result in "dst"
  • _mm_aeskeygenassist_si128 Assist in expanding the AES cipher key by computing steps towards generating a round key for encryption cipher using data from "a" and an 8-bit round constant specified in "imm8"
  • _mm_alignr_epi8 Concatenate 16-byte blocks in "a" and "b" into a 32-byte temporary result, shift the result right by "count" bytes, and store the low 16 bytes in "dst"
  • _mm256_alignr_epi8 Concatenate pairs of 16-byte blocks in "a" and "b" into a 32-byte temporary result, shift the result right by "count" bytes, and store the low 16 bytes in "dst"
  • _mm_alignr_pi8 Concatenate 8-byte blocks in "a" and "b" into a 16-byte temporary result, shift the result right by "count" bytes, and store the low 16 bytes in "dst"
  • _allow_cpu_features Treat the processor-specific feature(s) specified in "a" as available
  • _mm_and_pd Compute the bitwise AND of packed double-precision floating-point elements in "a" and "b"
  • _mm256_and_pd Compute the bitwise AND of packed double-precision floating-point elements in "a" and "b"
  • _mm_and_ps Compute the bitwise AND of packed single-precision floating-point elements in "a" and "b"
  • _mm256_and_ps Compute the bitwise AND of packed single-precision floating-point elements in "a" and "b"
  • _mm_and_si64 Compute the bitwise AND of 64 bits (representing integer data) in "a" and "b"
  • _mm_and_si128 Compute the bitwise AND of 128 bits (representing integer data) in "a" and "b"
  • _mm256_and_si256 Compute the bitwise AND of 256 bits (representing integer data) in "a" and "b"
  • _andn_u32 Compute the bitwise NOT of 32-bit integer "a" and then AND with b
  • _andn_u64 Compute the bitwise NOT of 64-bit integer "a" and then AND with b
  • _mm_andnot_pd Compute the bitwise NOT of packed double-precision floating-point elements in "a" and then AND with "b"
  • _mm256_andnot_pd Compute the bitwise NOT of packed double-precision floating-point elements in "a" and then AND with "b"
  • _mm_andnot_ps Compute the bitwise NOT of packed single-precision floating-point elements in "a" and then AND with "b"
  • _mm256_andnot_ps Compute the bitwise NOT of packed single-precision floating-point elements in "a" and then AND with "b"
  • _mm_andnot_si64 Compute the bitwise NOT of 64 bits (representing integer data) in "a" and then AND with "b"
  • _mm_andnot_si128 Compute the bitwise NOT of 128 bits (representing integer data) in "a" and then AND with "b"
  • _mm256_andnot_si256 Compute the bitwise NOT of 256 bits (representing integer data) in "a" and then AND with "b"
  • _mm_asin_pd Compute the inverse sine of packed double-precision floating-point elements in "a" expressed in radians
  • _mm256_asin_pd Compute the inverse sine of packed double-precision floating-point elements in "a" expressed in radians
  • _mm_asin_ps Compute the inverse sine of packed single-precision floating-point elements in "a" expressed in radians
  • _mm256_asin_ps Compute the inverse sine of packed single-precision floating-point elements in "a" expressed in radians
  • _mm_asinh_pd Compute the inverse hyperbolic sine of packed double-precision floating-point elements in "a" expressed in radians
  • _mm256_asinh_pd Compute the inverse hyperbolic sine of packed double-precision floating-point elements in "a" expressed in radians
  • _mm_asinh_ps Compute the inverse hyperbolic sine of packed single-precision floating-point elements in "a" expressed in radians
  • _mm256_asinh_ps Compute the inverse hyperbolic sine of packed single-precision floating-point elements in "a" expressed in radians
  • _mm_atan_pd Compute the inverse tangent of packed double-precision floating-point elements in "a" expressed in radians
  • _mm256_atan_pd Compute the inverse tangent of packed double-precision floating-point elements in "a" expressed in radians
  • _mm_atan_ps Compute the inverse tangent of packed single-precision floating-point elements in "a" expressed in radians
  • _mm256_atan_ps Compute the inverse tangent of packed single-precision floating-point elements in "a" expressed in radians
  • _mm_atan2_pd Compute the inverse tangent of packed double-precision floating-point elements in "a" divided by packed elements in "b"
  • _mm256_atan2_pd Compute the inverse tangent of packed double-precision floating-point elements in "a" divided by packed elements in "b"
  • _mm_atan2_ps Compute the inverse tangent of packed single-precision floating-point elements in "a" divided by packed elements in "b"
  • _mm256_atan2_ps Compute the inverse tangent of packed single-precision floating-point elements in "a" divided by packed elements in "b"
  • _mm_atanh_pd Compute the inverse hyperbolic tangent of packed double-precision floating-point elements in "a" expressed in radians
  • _mm256_atanh_pd Compute the inverse hyperbolic tangent of packed double-precision floating-point elements in "a" expressed in radians
  • _mm_atanh_ps Compute the inverse hyperbolic tangent of packed single-precision floating-point elements in "a" expressed in radians
  • _mm256_atanh_ps Compute the inverse hyperbolic tangent of packed single-precision floating-point elements in "a" expressed in radians
  • _mm_avg_epu8 Average packed unsigned 8-bit integers in "a" and "b", and store the results in "dst"
  • _mm256_avg_epu8 Average packed unsigned 8-bit integers in "a" and "b", and store the results in "dst"
  • _mm_avg_epu16 Average packed unsigned 16-bit integers in "a" and "b", and store the results in "dst"
  • _mm256_avg_epu16 Average packed unsigned 16-bit integers in "a" and "b", and store the results in "dst"
  • _mm_avg_pu8 Average packed unsigned 8-bit integers in "a" and "b", and store the results in "dst"
  • _mm_avg_pu16 Average packed unsigned 16-bit integers in "a" and "b", and store the results in "dst"

B

  • _bextr_u32 Extract contiguous bits from unsigned 32-bit integer "a", and store the result in "dst"
  • _bextr_u64 Extract contiguous bits from unsigned 64-bit integer "a", and store the result in "dst"
  • _bextr2_u32 Extract contiguous bits from unsigned 32-bit integer "a", and store the result in "dst"
  • _bextr2_u64 Extract contiguous bits from unsigned 64-bit integer "a", and store the result in "dst"
  • _bit_scan_forward Set "dst" to the index of the lowest set bit in 32-bit integer "a"
  • _bit_scan_reverse Set "dst" to the index of the highest set bit in 32-bit integer "a"
  • _BitScanForward Set "index" to the index of the lowest set bit in 32-bit integer "mask"
  • _BitScanForward64 Set "index" to the index of the lowest set bit in 64-bit integer "mask"
  • _BitScanReverse Set "index" to the index of the highest set bit in 32-bit integer "mask"
  • _BitScanReverse64 Set "index" to the index of the highest set bit in 64-bit integer "mask"
  • _bittest Return the bit at index "b" of 32-bit integer "a".
  • _bittest64 Return the bit at index "b" of 64-bit integer "a".
  • _bittestandcomplement Return the bit at index "b" of 32-bit integer "a", and set that bit to its complement
  • _bittestandcomplement64 Return the bit at index "b" of 64-bit integer "a", and set that bit to its complement
  • _bittestandreset Return the bit at index "b" of 32-bit integer "a", and set that bit to zero
  • _bittestandreset64 Return the bit at index "b" of 64-bit integer "a", and set that bit to zero
  • _bittestandset Return the bit at index "b" of 32-bit integer "a", and set that bit to one
  • _bittestandset64 Return the bit at index "b" of 64-bit integer "a", and set that bit to one
  • _mm_blend_epi16 Blend packed 16-bit integers from "a" and "b" using control mask "imm8"
  • _mm256_blend_epi16 Blend packed 16-bit integers from "a" and "b" within 128-bit lanes using control mask "imm8"
  • _mm_blend_epi32 Blend packed 32-bit integers from "a" and "b" using control mask "imm8"
  • _mm256_blend_epi32 Blend packed 32-bit integers from "a" and "b" using control mask "imm8"
  • _mm_blend_pd Blend packed double-precision floating-point elements from "a" and "b" using control mask "imm8"
  • _mm256_blend_pd Blend packed double-precision floating-point elements from "a" and "b" using control mask "imm8"
  • _mm_blend_ps Blend packed single-precision floating-point elements from "a" and "b" using control mask "imm8"
  • _mm256_blend_ps Blend packed single-precision floating-point elements from "a" and "b" using control mask "imm8"
  • _mm_blendv_epi8 Blend packed 8-bit integers from "a" and "b" using "mask", and store the results in "dst"
  • _mm256_blendv_epi8 Blend packed 8-bit integers from "a" and "b" using "mask", and store the results in "dst"
  • _mm_blendv_pd Blend packed double-precision floating-point elements from "a" and "b" using "mask"
  • _mm256_blendv_pd Blend packed double-precision floating-point elements from "a" and "b" using "mask"
  • _mm_blendv_ps Blend packed single-precision floating-point elements from "a" and "b" using "mask"
  • _mm256_blendv_ps Blend packed single-precision floating-point elements from "a" and "b" using "mask"
  • _blsi_u32 Extract the lowest set bit from unsigned 32-bit integer "a" and set the corresponding bit in "dst"
  • _blsi_u64 Extract the lowest set bit from unsigned 64-bit integer "a" and set the corresponding bit in "dst"
  • _blsmsk_u32 Set all the lower bits of "dst" up to and including the lowest set bit in unsigned 32-bit integer "a"
  • _blsmsk_u64 Set all the lower bits of "dst" up to and including the lowest set bit in unsigned 64-bit integer "a"
  • _blsr_u32 Copy all bits from unsigned 32-bit integer "a" to "dst", and reset (set to 0) the bit in "dst" that corresponds to the lowest set bit in "a"
  • _blsr_u64 Copy all bits from unsigned 64-bit integer "a" to "dst", and reset (set to 0) the bit in "dst" that corresponds to the lowest set bit in "a"
  • _bnd_chk_ptr_bounds Checks if ["q", "q" + "size" - 1] is within the lower and upper bounds of "q" and throws a #BR if not
  • _bnd_chk_ptr_lbounds Checks if "q" is within its lower bound, and throws a #BR if not.
  • _bnd_chk_ptr_ubounds Checks if "q" is within its upper bound, and throws a #BR if not.
  • _bnd_copy_ptr_bounds Make a pointer with the value of "q" and bounds set to the bounds of "r" (e
  • _bnd_get_ptr_lbound Return the lower bound of "q".
  • _bnd_get_ptr_ubound Return the upper bound of "q".
  • _bnd_init_ptr_bounds Make a pointer with the value of "q" and open bounds, which allow the pointer to access the entire virtual address space
  • _bnd_narrow_ptr_bounds Narrow the bounds for pointer "q" to the intersection of the bounds of "r" and the bounds ["q", "q" + "size" - 1]
  • _bnd_set_ptr_bounds Make a pointer with the value of "srcmem" and bounds set to ["srcmem", "srcmem" + "size" - 1]
  • _bnd_store_ptr_bounds Stores the bounds of "ptr_val" pointer in memory at address "ptr_addr"
  • _mm256_broadcast_pd Broadcast 128 bits from memory (composed of 2 packed double-precision floating-point elements) to all elements of "dst"
  • _mm256_broadcast_ps Broadcast 128 bits from memory (composed of 4 packed single-precision floating-point elements) to all elements of "dst"
  • _mm256_broadcast_sd Broadcast a double-precision floating-point element from memory to all elements of "dst"
  • _mm256_broadcast_ss Broadcast a single-precision floating-point element from memory to all elements of "dst"
  • _mm_broadcast_ss Broadcast a single-precision floating-point element from memory to all elements of "dst"
  • _mm_broadcastb_epi8 Broadcast the low packed 8-bit integer from "a" to all elements of "dst"
  • _mm256_broadcastb_epi8 Broadcast the low packed 8-bit integer from "a" to all elements of "dst"
  • _mm_broadcastd_epi32 Broadcast the low packed 32-bit integer from "a" to all elements of "dst"
  • _mm256_broadcastd_epi32 Broadcast the low packed 32-bit integer from "a" to all elements of "dst"
  • _mm_broadcastq_epi64 Broadcast the low packed 64-bit integer from "a" to all elements of "dst"
  • _mm256_broadcastq_epi64 Broadcast the low packed 64-bit integer from "a" to all elements of "dst"
  • _mm_broadcastsd_pd Broadcast the low double-precision floating-point element from "a" to all elements of "dst"
  • _mm256_broadcastsd_pd Broadcast the low double-precision floating-point element from "a" to all elements of "dst"
  • _mm_broadcastsi128_si256 Broadcast 128 bits of integer data from "a" to all 128-bit lanes in "dst"
  • _mm256_broadcastsi128_si256 Broadcast 128 bits of integer data from "a" to all 128-bit lanes in "dst"
  • _mm_broadcastss_ps Broadcast the low single-precision floating-point element from "a" to all elements of "dst"
  • _mm256_broadcastss_ps Broadcast the low single-precision floating-point element from "a" to all elements of "dst"
  • _mm_broadcastw_epi16 Broadcast the low packed 16-bit integer from "a" to all elements of "dst"
  • _mm256_broadcastw_epi16 Broadcast the low packed 16-bit integer from "a" to all elements of "dst"
  • _mm256_bslli_epi128 Shift 128-bit lanes in "a" left by "imm8" bytes while shifting in zeros
  • _mm_bslli_si128 Shift "a" left by "imm8" bytes while shifting in zeros, and store the results in "dst"
  • _mm256_bsrli_epi128 Shift 128-bit lanes in "a" right by "imm8" bytes while shifting in zeros
  • _mm_bsrli_si128 Shift "a" right by "imm8" bytes while shifting in zeros, and store the results in "dst"
  • _bswap Reverse the byte order of 32-bit integer "a", and store the result in "dst"
  • _bswap64 Reverse the byte order of 64-bit integer "a", and store the result in "dst"
  • _bzhi_u32 Copy all bits from unsigned 32-bit integer "a" to "dst", and reset (set to 0) the high bits in "dst" starting at "index"
  • _bzhi_u64 Copy all bits from unsigned 64-bit integer "a" to "dst", and reset (set to 0) the high bits in "dst" starting at "index"

C

  • _castf32_u32 Cast from type float to type unsigned __int32 without conversion. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.
  • _castf64_u64 Cast from type double to type unsigned __int64 without conversion
  • _mm_castpd_ps Cast vector of type __m128d to type __m128. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.
  • _mm256_castpd_ps Cast vector of type __m256d to type __m256. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.
  • _mm_castpd_si128 Cast vector of type __m128d to type __m128i. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.
  • _mm256_castpd_si256 Casts vector of type __m256d to type __m256i. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.
  • _mm256_castpd128_pd256 Casts vector of type __m128d to type __m256d; the upper 128 bits of the result are undefined
  • _mm256_castpd256_pd128 Casts vector of type __m256d to type __m128d. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.
  • _mm_castps_pd Cast vector of type __m128 to type __m128d. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.
  • _mm256_castps_pd Cast vector of type __m256 to type __m256d. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.
  • _mm_castps_si128 Cast vector of type __m128 to type __m128i. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.
  • _mm256_castps_si256 Casts vector of type __m256 to type __m256i. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.
  • _mm256_castps128_ps256 Casts vector of type __m128 to type __m256; the upper 128 bits of the result are undefined
  • _mm256_castps256_ps128 Casts vector of type __m256 to type __m128. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.
  • _mm_castsi128_pd Cast vector of type __m128i to type __m128d. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.
  • _mm_castsi128_ps Cast vector of type __m128i to type __m128. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.
  • _mm256_castsi128_si256 Casts vector of type __m128i to type __m256i; the upper 128 bits of the result are undefined
  • _mm256_castsi256_pd Casts vector of type __m256i to type __m256d. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.
  • _mm256_castsi256_ps Casts vector of type __m256i to type __m256. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.
  • _mm256_castsi256_si128 Casts vector of type __m256i to type __m128i. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.
  • _castu32_f32 Cast from type unsigned __int32 to type float without conversion. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.
  • _castu64_f64 Cast from type unsigned __int64 to type double without conversion
  • _mm_cbrt_pd Compute the cube root of packed double-precision floating-point elements in "a"
  • _mm256_cbrt_pd Compute the cube root of packed double-precision floating-point elements in "a"
  • _mm_cbrt_ps Compute the cube root of packed single-precision floating-point elements in "a"
  • _mm256_cbrt_ps Compute the cube root of packed single-precision floating-point elements in "a"
  • _mm_cdfnorm_pd Compute the cumulative distribution function of packed double-precision floating-point elements in "a" using the normal distribution
  • _mm256_cdfnorm_pd Compute the cumulative distribution function of packed double-precision floating-point elements in "a" using the normal distribution
  • _mm_cdfnorm_ps Compute the cumulative distribution function of packed single-precision floating-point elements in "a" using the normal distribution
  • _mm256_cdfnorm_ps Compute the cumulative distribution function of packed single-precision floating-point elements in "a" using the normal distribution
  • _mm_cdfnorminv_pd Compute the inverse cumulative distribution function of packed double-precision floating-point elements in "a" using the normal distribution
  • _mm256_cdfnorminv_pd Compute the inverse cumulative distribution function of packed double-precision floating-point elements in "a" using the normal distribution
  • _mm_cdfnorminv_ps Compute the inverse cumulative distribution function of packed single-precision floating-point elements in "a" using the normal distribution
  • _mm256_cdfnorminv_ps Compute the inverse cumulative distribution function of packed single-precision floating-point elements in "a" using the normal distribution
  • _mm_ceil_pd Round the packed double-precision floating-point elements in "a" up to an integer value
  • _mm256_ceil_pd Round the packed double-precision floating-point elements in "a" up to an integer value
  • _mm_ceil_ps Round the packed single-precision floating-point elements in "a" up to an integer value
  • _mm256_ceil_ps Round the packed single-precision floating-point elements in "a" up to an integer value
  • _mm_ceil_sd Round the lower double-precision floating-point element in "b" up to an integer value
  • _mm_ceil_ss Round the lower single-precision floating-point element in "b" up to an integer value
  • _mm_cexp_ps Compute the exponential value of "e" raised to the power of packed complex single-precision floating-point elements in "a"
  • _mm256_cexp_ps Compute the exponential value of "e" raised to the power of packed complex single-precision floating-point elements in "a"
  • _mm_cldemote Hint to hardware that the cache line that contains "p" should be demoted from the cache closest to the processor core to a level more distant from the processor core
  • _mm_clflush Invalidate and flush the cache line that contains "p" from all levels of the cache hierarchy
  • _mm_clflushopt Invalidate and flush the cache line that contains "p" from all levels of the cache hierarchy
  • _mm_clmulepi64_si128 Perform a carry-less multiplication of two 64-bit integers, selected from "a" and "b" according to "imm8"
  • _mm_clog_ps Compute the natural logarithm of packed complex single-precision floating-point elements in "a"
  • _mm256_clog_ps Compute the natural logarithm of packed complex single-precision floating-point elements in "a"
  • _clrssbsy Mark shadow stack pointed to by "p" as not busy.
  • _mm_clwb Write back to memory the cache line that contains "p" from any level of the cache hierarchy in the cache coherence domain
  • _mm_cmp_pd Compare packed double-precision floating-point elements in "a" and "b"
  • _mm256_cmp_pd Compare packed double-precision floating-point elements in "a" and "b"
  • _mm_cmp_ps Compare packed single-precision floating-point elements in "a" and "b"
  • _mm256_cmp_ps Compare packed single-precision floating-point elements in "a" and "b"
  • _mm_cmp_sd Compare the lower double-precision floating-point element in "a" and "b"
  • _mm_cmp_ss Compare the lower single-precision floating-point element in "a" and "b"
  • _mm_cmpeq_epi8 Compare packed 8-bit integers in "a" and "b" for equality, and store the results in "dst"
  • _mm256_cmpeq_epi8 Compare packed 8-bit integers in "a" and "b" for equality, and store the results in "dst"
  • _mm_cmpeq_epi16 Compare packed 16-bit integers in "a" and "b" for equality, and store the results in "dst"
  • _mm256_cmpeq_epi16 Compare packed 16-bit integers in "a" and "b" for equality, and store the results in "dst"
  • _mm_cmpeq_epi32 Compare packed 32-bit integers in "a" and "b" for equality, and store the results in "dst"
  • _mm256_cmpeq_epi32 Compare packed 32-bit integers in "a" and "b" for equality, and store the results in "dst"
  • _mm_cmpeq_epi64 Compare packed 64-bit integers in "a" and "b" for equality, and store the results in "dst"
  • _mm256_cmpeq_epi64 Compare packed 64-bit integers in "a" and "b" for equality, and store the results in "dst"
  • _mm_cmpeq_pd Compare packed double-precision floating-point elements in "a" and "b" for equality
  • _mm_cmpeq_pi8 Compare packed 8-bit integers in "a" and "b" for equality, and store the results in "dst"
  • _mm_cmpeq_pi16 Compare packed 16-bit integers in "a" and "b" for equality, and store the results in "dst"
  • _mm_cmpeq_pi32 Compare packed 32-bit integers in "a" and "b" for equality, and store the results in "dst"
  • _mm_cmpeq_ps Compare packed single-precision floating-point elements in "a" and "b" for equality
  • _mm_cmpeq_sd Compare the lower double-precision floating-point elements in "a" and "b" for equality
  • _mm_cmpeq_ss Compare the lower single-precision floating-point elements in "a" and "b" for equality
  • _mm_cmpestra Compare packed strings in "a" and "b" with lengths "la" and "lb" using the control in "imm8"
  • _mm_cmpestrc Compare packed strings in "a" and "b" with lengths "la" and "lb" using the control in "imm8"
  • _mm_cmpestri Compare packed strings in "a" and "b" with lengths "la" and "lb" using the control in "imm8", and store the generated index in "dst"
  • _mm_cmpestrm Compare packed strings in "a" and "b" with lengths "la" and "lb" using the control in "imm8", and store the generated mask in "dst"
  • _mm_cmpestro Compare packed strings in "a" and "b" with lengths "la" and "lb" using the control in "imm8"
  • _mm_cmpestrs Compare packed strings in "a" and "b" with lengths "la" and "lb" using the control in "imm8"
  • _mm_cmpestrz Compare packed strings in "a" and "b" with lengths "la" and "lb" using the control in "imm8"
  • _mm_cmpge_pd Compare packed double-precision floating-point elements in "a" and "b" for greater-than-or-equal
  • _mm_cmpge_ps Compare packed single-precision floating-point elements in "a" and "b" for greater-than-or-equal
  • _mm_cmpge_sd Compare the lower double-precision floating-point elements in "a" and "b" for greater-than-or-equal
  • _mm_cmpge_ss Compare the lower single-precision floating-point elements in "a" and "b" for greater-than-or-equal
  • _mm_cmpgt_epi8 Compare packed 8-bit integers in "a" and "b" for greater-than, and store the results in "dst"
  • _mm256_cmpgt_epi8 Compare packed 8-bit integers in "a" and "b" for greater-than, and store the results in "dst"
  • _mm_cmpgt_epi16 Compare packed 16-bit integers in "a" and "b" for greater-than, and store the results in "dst"
  • _mm256_cmpgt_epi16 Compare packed 16-bit integers in "a" and "b" for greater-than, and store the results in "dst"
  • _mm_cmpgt_epi32 Compare packed 32-bit integers in "a" and "b" for greater-than, and store the results in "dst"
  • _mm256_cmpgt_epi32 Compare packed 32-bit integers in "a" and "b" for greater-than, and store the results in "dst"
  • _mm_cmpgt_epi64 Compare packed 64-bit integers in "a" and "b" for greater-than, and store the results in "dst"
  • _mm256_cmpgt_epi64 Compare packed 64-bit integers in "a" and "b" for greater-than, and store the results in "dst"
  • _mm_cmpgt_pd Compare packed double-precision floating-point elements in "a" and "b" for greater-than
  • _mm_cmpgt_pi8 Compare packed 8-bit integers in "a" and "b" for greater-than, and store the results in "dst"
  • _mm_cmpgt_pi16 Compare packed 16-bit integers in "a" and "b" for greater-than, and store the results in "dst"
  • _mm_cmpgt_pi32 Compare packed 32-bit integers in "a" and "b" for greater-than, and store the results in "dst"
  • _mm_cmpgt_ps Compare packed single-precision floating-point elements in "a" and "b" for greater-than
  • _mm_cmpgt_sd Compare the lower double-precision floating-point elements in "a" and "b" for greater-than
  • _mm_cmpgt_ss Compare the lower single-precision floating-point elements in "a" and "b" for greater-than
  • _mm_cmpistra Compare packed strings with implicit lengths in "a" and "b" using the control in "imm8"
  • _mm_cmpistrc Compare packed strings with implicit lengths in "a" and "b" using the control in "imm8"
  • _mm_cmpistri Compare packed strings with implicit lengths in "a" and "b" using the control in "imm8", and store the generated index in "dst"
  • _mm_cmpistrm Compare packed strings with implicit lengths in "a" and "b" using the control in "imm8", and store the generated mask in "dst"
  • _mm_cmpistro Compare packed strings with implicit lengths in "a" and "b" using the control in "imm8"
  • _mm_cmpistrs Compare packed strings with implicit lengths in "a" and "b" using the control in "imm8"
  • _mm_cmpistrz Compare packed strings with implicit lengths in "a" and "b" using the control in "imm8"
  • _mm_cmple_pd Compare packed double-precision floating-point elements in "a" and "b" for less-than-or-equal
  • _mm_cmple_ps Compare packed single-precision floating-point elements in "a" and "b" for less-than-or-equal
  • _mm_cmple_sd Compare the lower double-precision floating-point elements in "a" and "b" for less-than-or-equal
  • _mm_cmple_ss Compare the lower single-precision floating-point elements in "a" and "b" for less-than-or-equal
  • _mm_cmplt_epi8 Compare packed 8-bit integers in "a" and "b" for less-than, and store the results in "dst"
  • _mm_cmplt_epi16 Compare packed 16-bit integers in "a" and "b" for less-than, and store the results in "dst"
  • _mm_cmplt_epi32 Compare packed 32-bit integers in "a" and "b" for less-than, and store the results in "dst"
  • _mm_cmplt_pd Compare packed double-precision floating-point elements in "a" and "b" for less-than
  • _mm_cmplt_ps Compare packed single-precision floating-point elements in "a" and "b" for less-than
  • _mm_cmplt_sd Compare the lower double-precision floating-point elements in "a" and "b" for less-than
  • _mm_cmplt_ss Compare the lower single-precision floating-point elements in "a" and "b" for less-than
  • _mm_cmpneq_pd Compare packed double-precision floating-point elements in "a" and "b" for not-equal
  • _mm_cmpneq_ps Compare packed single-precision floating-point elements in "a" and "b" for not-equal
  • _mm_cmpneq_sd Compare the lower double-precision floating-point elements in "a" and "b" for not-equal
  • _mm_cmpneq_ss Compare the lower single-precision floating-point elements in "a" and "b" for not-equal
  • _mm_cmpnge_pd Compare packed double-precision floating-point elements in "a" and "b" for not-greater-than-or-equal
  • _mm_cmpnge_ps Compare packed single-precision floating-point elements in "a" and "b" for not-greater-than-or-equal
  • _mm_cmpnge_sd Compare the lower double-precision floating-point elements in "a" and "b" for not-greater-than-or-equal
  • _mm_cmpnge_ss Compare the lower single-precision floating-point elements in "a" and "b" for not-greater-than-or-equal
  • _mm_cmpngt_pd Compare packed double-precision floating-point elements in "a" and "b" for not-greater-than
  • _mm_cmpngt_ps Compare packed single-precision floating-point elements in "a" and "b" for not-greater-than
  • _mm_cmpngt_sd Compare the lower double-precision floating-point elements in "a" and "b" for not-greater-than
  • _mm_cmpngt_ss Compare the lower single-precision floating-point elements in "a" and "b" for not-greater-than
  • _mm_cmpnle_pd Compare packed double-precision floating-point elements in "a" and "b" for not-less-than-or-equal
  • _mm_cmpnle_ps Compare packed single-precision floating-point elements in "a" and "b" for not-less-than-or-equal
  • _mm_cmpnle_sd Compare the lower double-precision floating-point elements in "a" and "b" for not-less-than-or-equal
  • _mm_cmpnle_ss Compare the lower single-precision floating-point elements in "a" and "b" for not-less-than-or-equal
  • _mm_cmpnlt_pd Compare packed double-precision floating-point elements in "a" and "b" for not-less-than
  • _mm_cmpnlt_ps Compare packed single-precision floating-point elements in "a" and "b" for not-less-than
  • _mm_cmpnlt_sd Compare the lower double-precision floating-point elements in "a" and "b" for not-less-than
  • _mm_cmpnlt_ss Compare the lower single-precision floating-point elements in "a" and "b" for not-less-than
  • _mm_cmpord_pd Compare packed double-precision floating-point elements in "a" and "b" to see if neither is NaN
  • _mm_cmpord_ps Compare packed single-precision floating-point elements in "a" and "b" to see if neither is NaN
  • _mm_cmpord_sd Compare the lower double-precision floating-point elements in "a" and "b" to see if neither is NaN
  • _mm_cmpord_ss Compare the lower single-precision floating-point elements in "a" and "b" to see if neither is NaN
  • _mm_cmpunord_pd Compare packed double-precision floating-point elements in "a" and "b" to see if either is NaN
  • _mm_cmpunord_ps Compare packed single-precision floating-point elements in "a" and "b" to see if either is NaN
  • _mm_cmpunord_sd Compare the lower double-precision floating-point elements in "a" and "b" to see if either is NaN
  • _mm_cmpunord_ss Compare the lower single-precision floating-point elements in "a" and "b" to see if either is NaN
  • _mm_comieq_sd Compare the lower double-precision floating-point element in "a" and "b" for equality
  • _mm_comieq_ss Compare the lower single-precision floating-point element in "a" and "b" for equality
  • _mm_comige_sd Compare the lower double-precision floating-point element in "a" and "b" for greater-than-or-equal
  • _mm_comige_ss Compare the lower single-precision floating-point element in "a" and "b" for greater-than-or-equal
  • _mm_comigt_sd Compare the lower double-precision floating-point element in "a" and "b" for greater-than
  • _mm_comigt_ss Compare the lower single-precision floating-point element in "a" and "b" for greater-than
  • _mm_comile_sd Compare the lower double-precision floating-point element in "a" and "b" for less-than-or-equal
  • _mm_comile_ss Compare the lower single-precision floating-point element in "a" and "b" for less-than-or-equal
  • _mm_comilt_sd Compare the lower double-precision floating-point element in "a" and "b" for less-than
  • _mm_comilt_ss Compare the lower single-precision floating-point element in "a" and "b" for less-than
  • _mm_comineq_sd Compare the lower double-precision floating-point element in "a" and "b" for not-equal
  • _mm_comineq_ss Compare the lower single-precision floating-point element in "a" and "b" for not-equal
  • _mm_cos_pd Compute the cosine of packed double-precision floating-point elements in "a" expressed in radians
  • _mm256_cos_pd Compute the cosine of packed double-precision floating-point elements in "a" expressed in radians
  • _mm_cos_ps Compute the cosine of packed single-precision floating-point elements in "a" expressed in radians
  • _mm256_cos_ps Compute the cosine of packed single-precision floating-point elements in "a" expressed in radians
  • _mm_cosd_pd Compute the cosine of packed double-precision floating-point elements in "a" expressed in degrees
  • _mm256_cosd_pd Compute the cosine of packed double-precision floating-point elements in "a" expressed in degrees
  • _mm_cosd_ps Compute the cosine of packed single-precision floating-point elements in "a" expressed in degrees
  • _mm256_cosd_ps Compute the cosine of packed single-precision floating-point elements in "a" expressed in degrees
  • _mm_cosh_pd Compute the hyperbolic cosine of packed double-precision floating-point elements in "a" expressed in radians
  • _mm256_cosh_pd Compute the hyperbolic cosine of packed double-precision floating-point elements in "a" expressed in radians
  • _mm_cosh_ps Compute the hyperbolic cosine of packed single-precision floating-point elements in "a" expressed in radians
  • _mm256_cosh_ps Compute the hyperbolic cosine of packed single-precision floating-point elements in "a" expressed in radians
  • _mm_crc32_u8 Starting with the initial value in "crc", accumulates a CRC32 value for unsigned 8-bit integer "v", and stores the result in "dst"
  • _mm_crc32_u16 Starting with the initial value in "crc", accumulates a CRC32 value for unsigned 16-bit integer "v", and stores the result in "dst"
  • _mm_crc32_u32 Starting with the initial value in "crc", accumulates a CRC32 value for unsigned 32-bit integer "v", and stores the result in "dst"
  • _mm_crc32_u64 Starting with the initial value in "crc", accumulates a CRC32 value for unsigned 64-bit integer "v", and stores the result in "dst"
  • _mm_csqrt_ps Compute the square root of packed complex single-precision floating-point elements in "a"
  • _mm256_csqrt_ps Compute the square root of packed complex single-precision floating-point elements in "a"
  • _mm_cvt_pi2ps Convert packed 32-bit integers in "b" to packed single-precision floating-point elements
  • _mm_cvt_ps2pi Convert packed single-precision floating-point elements in "a" to packed 32-bit integers
  • _mm_cvt_si2ss Convert the 32-bit integer "b" to a single-precision floating-point element
  • _mm_cvt_ss2si Convert the lower single-precision floating-point element in "a" to a 32-bit integer
  • _mm_cvtepi16_epi32 Sign extend packed 16-bit integers in "a" to packed 32-bit integers
  • _mm256_cvtepi16_epi32 Sign extend packed 16-bit integers in "a" to packed 32-bit integers
  • _mm_cvtepi16_epi64 Sign extend packed 16-bit integers in "a" to packed 64-bit integers
  • _mm256_cvtepi16_epi64 Sign extend packed 16-bit integers in "a" to packed 64-bit integers
  • _mm_cvtepi32_epi64 Sign extend packed 32-bit integers in "a" to packed 64-bit integers
  • _mm256_cvtepi32_epi64 Sign extend packed 32-bit integers in "a" to packed 64-bit integers
  • _mm_cvtepi32_pd Convert packed 32-bit integers in "a" to packed double-precision floating-point elements
  • _mm256_cvtepi32_pd Convert packed 32-bit integers in "a" to packed double-precision floating-point elements
  • _mm_cvtepi32_ps Convert packed 32-bit integers in "a" to packed single-precision floating-point elements
  • _mm256_cvtepi32_ps Convert packed 32-bit integers in "a" to packed single-precision floating-point elements
  • _mm_cvtepi8_epi16 Sign extend packed 8-bit integers in "a" to packed 16-bit integers
  • _mm256_cvtepi8_epi16 Sign extend packed 8-bit integers in "a" to packed 16-bit integers
  • _mm_cvtepi8_epi32 Sign extend packed 8-bit integers in "a" to packed 32-bit integers
  • _mm256_cvtepi8_epi32 Sign extend packed 8-bit integers in "a" to packed 32-bit integers
  • _mm_cvtepi8_epi64 Sign extend packed 8-bit integers in the low 8 bytes of "a" to packed 64-bit integers
  • _mm256_cvtepi8_epi64 Sign extend packed 8-bit integers in the low 8 bytes of "a" to packed 64-bit integers
  • _mm_cvtepu16_epi32 Zero extend packed unsigned 16-bit integers in "a" to packed 32-bit integers
  • _mm256_cvtepu16_epi32 Zero extend packed unsigned 16-bit integers in "a" to packed 32-bit integers
  • _mm_cvtepu16_epi64 Zero extend packed unsigned 16-bit integers in "a" to packed 64-bit integers
  • _mm256_cvtepu16_epi64 Zero extend packed unsigned 16-bit integers in "a" to packed 64-bit integers
  • _mm_cvtepu32_epi64 Zero extend packed unsigned 32-bit integers in "a" to packed 64-bit integers
  • _mm256_cvtepu32_epi64 Zero extend packed unsigned 32-bit integers in "a" to packed 64-bit integers
  • _mm_cvtepu8_epi16 Zero extend packed unsigned 8-bit integers in "a" to packed 16-bit integers
  • _mm256_cvtepu8_epi16 Zero extend packed unsigned 8-bit integers in "a" to packed 16-bit integers
  • _mm_cvtepu8_epi32 Zero extend packed unsigned 8-bit integers in "a" to packed 32-bit integers
  • _mm256_cvtepu8_epi32 Zero extend packed unsigned 8-bit integers in "a" to packed 32-bit integers
  • _mm_cvtepu8_epi64 Zero extend packed unsigned 8-bit integers in the low 8 byte sof "a" to packed 64-bit integers
  • _mm256_cvtepu8_epi64 Zero extend packed unsigned 8-bit integers in the low 8 byte sof "a" to packed 64-bit integers
  • _mm_cvtm64_si64 Copy 64-bit integer "a" to "dst".
  • _mm_cvtpd_epi32 Convert packed double-precision floating-point elements in "a" to packed 32-bit integers
  • _mm256_cvtpd_epi32 Convert packed double-precision floating-point elements in "a" to packed 32-bit integers
  • _mm_cvtpd_pi32 Convert packed double-precision floating-point elements in "a" to packed 32-bit integers
  • _mm_cvtpd_ps Convert packed double-precision floating-point elements in "a" to packed single-precision floating-point elements
  • _mm256_cvtpd_ps Convert packed double-precision floating-point elements in "a" to packed single-precision floating-point elements
  • _mm_cvtph_ps Convert packed half-precision (16-bit) floating-point elements in "a" to packed single-precision floating-point elements
  • _mm256_cvtph_ps Convert packed half-precision (16-bit) floating-point elements in "a" to packed single-precision floating-point elements
  • _mm_cvtpi16_ps Convert packed 16-bit integers in "a" to packed single-precision floating-point elements
  • _mm_cvtpi32_pd Convert packed 32-bit integers in "a" to packed double-precision floating-point elements
  • _mm_cvtpi32_ps Convert packed 32-bit integers in "b" to packed single-precision floating-point elements
  • _mm_cvtpi32x2_ps Convert packed 32-bit integers in "a" to packed single-precision floating-point elements
  • _mm_cvtpi8_ps Convert the lower packed 8-bit integers in "a" to packed single-precision floating-point elements
  • _mm_cvtps_epi32 Convert packed single-precision floating-point elements in "a" to packed 32-bit integers
  • _mm256_cvtps_epi32 Convert packed single-precision floating-point elements in "a" to packed 32-bit integers
  • _mm_cvtps_pd Convert packed single-precision floating-point elements in "a" to packed double-precision floating-point elements
  • _mm256_cvtps_pd Convert packed single-precision floating-point elements in "a" to packed double-precision floating-point elements
  • _mm_cvtps_ph Convert packed single-precision floating-point elements in "a" to packed half-precision (16-bit) floating-point elements
  • _mm256_cvtps_ph Convert packed single-precision floating-point elements in "a" to packed half-precision (16-bit) floating-point elements
  • _mm_cvtps_pi8 Convert packed single-precision floating-point elements in "a" to packed 8-bit integers
  • _mm_cvtps_pi16 Convert packed single-precision floating-point elements in "a" to packed 16-bit integers
  • _mm_cvtps_pi32 Convert packed single-precision floating-point elements in "a" to packed 32-bit integers
  • _mm_cvtpu16_ps Convert packed unsigned 16-bit integers in "a" to packed single-precision floating-point elements
  • _mm_cvtpu8_ps Convert the lower packed unsigned 8-bit integers in "a" to packed single-precision floating-point elements
  • _mm_cvtsd_f64 Copy the lower double-precision floating-point element of "a" to "dst"
  • _mm256_cvtsd_f64 Copy the lower double-precision floating-point element of "a" to "dst"
  • _mm_cvtsd_si32 Convert the lower double-precision floating-point element in "a" to a 32-bit integer
  • _mm_cvtsd_si64 Convert the lower double-precision floating-point element in "a" to a 64-bit integer
  • _mm_cvtsd_si64x Convert the lower double-precision floating-point element in "a" to a 64-bit integer
  • _mm_cvtsd_ss Convert the lower double-precision floating-point element in "b" to a single-precision floating-point element
  • _cvtsh_ss Convert the half-precision (16-bit) floating-point value "a" to a single-precision floating-point value
  • _mm_cvtsi128_si32 Copy the lower 32-bit integer in "a" to "dst".
  • _mm_cvtsi128_si64 Copy the lower 64-bit integer in "a" to "dst".
  • _mm_cvtsi128_si64x Copy the lower 64-bit integer in "a" to "dst".
  • _mm256_cvtsi256_si32 Copy the lower 32-bit integer in "a" to "dst".
  • _mm_cvtsi32_sd Convert the 32-bit integer "b" to a double-precision floating-point element
  • _mm_cvtsi32_si64 Copy 32-bit integer "a" to the lower elements of "dst", and zero the upper element of "dst"
  • _mm_cvtsi32_si128 Copy 32-bit integer "a" to the lower elements of "dst", and zero the upper elements of "dst"
  • _mm_cvtsi32_ss Convert the 32-bit integer "b" to a single-precision floating-point element
  • _mm_cvtsi64_m64 Copy 64-bit integer "a" to "dst".
  • _mm_cvtsi64_sd Convert the 64-bit integer "b" to a double-precision floating-point element
  • _mm_cvtsi64_si32 Copy the lower 32-bit integer in "a" to "dst".
  • _mm_cvtsi64_si128 Copy 64-bit integer "a" to the lower element of "dst", and zero the upper element
  • _mm_cvtsi64_ss Convert the 64-bit integer "b" to a single-precision floating-point element
  • _mm_cvtsi64x_sd Convert the 64-bit integer "b" to a double-precision floating-point element
  • _mm_cvtsi64x_si128 Copy 64-bit integer "a" to the lower element of "dst", and zero the upper element
  • _mm_cvtss_f32 Copy the lower single-precision floating-point element of "a" to "dst"
  • _mm256_cvtss_f32 Copy the lower single-precision floating-point element of "a" to "dst"
  • _mm_cvtss_sd Convert the lower single-precision floating-point element in "b" to a double-precision floating-point element
  • _cvtss_sh Convert the single-precision floating-point value "a" to a half-precision (16-bit) floating-point value
  • _mm_cvtss_si32 Convert the lower single-precision floating-point element in "a" to a 32-bit integer
  • _mm_cvtss_si64 Convert the lower single-precision floating-point element in "a" to a 64-bit integer
  • _mm_cvtt_ps2pi Convert packed single-precision floating-point elements in "a" to packed 32-bit integers with truncation
  • _mm_cvtt_ss2si Convert the lower single-precision floating-point element in "a" to a 32-bit integer with truncation
  • _mm_cvttpd_epi32 Convert packed double-precision floating-point elements in "a" to packed 32-bit integers with truncation
  • _mm256_cvttpd_epi32 Convert packed double-precision floating-point elements in "a" to packed 32-bit integers with truncation
  • _mm_cvttpd_pi32 Convert packed double-precision floating-point elements in "a" to packed 32-bit integers with truncation
  • _mm_cvttps_epi32 Convert packed single-precision floating-point elements in "a" to packed 32-bit integers with truncation
  • _mm256_cvttps_epi32 Convert packed single-precision floating-point elements in "a" to packed 32-bit integers with truncation
  • _mm_cvttps_pi32 Convert packed single-precision floating-point elements in "a" to packed 32-bit integers with truncation
  • _mm_cvttsd_si32 Convert the lower double-precision floating-point element in "a" to a 32-bit integer with truncation
  • _mm_cvttsd_si64 Convert the lower double-precision floating-point element in "a" to a 64-bit integer with truncation
  • _mm_cvttsd_si64x Convert the lower double-precision floating-point element in "a" to a 64-bit integer with truncation
  • _mm_cvttss_si32 Convert the lower single-precision floating-point element in "a" to a 32-bit integer with truncation
  • _mm_cvttss_si64 Convert the lower single-precision floating-point element in "a" to a 64-bit integer with truncation

D

  • _directstoreu_u32 Store 32-bit integer from "val" into memory using direct store.
  • _directstoreu_u64 Store 64-bit integer from "val" into memory using direct store.
  • _mm_div_epi8 Divide packed 8-bit integers in "a" by packed elements in "b", and store the truncated results in "dst"
  • _mm256_div_epi8 Divide packed 8-bit integers in "a" by packed elements in "b", and store the truncated results in "dst"
  • _mm_div_epi16 Divide packed 16-bit integers in "a" by packed elements in "b", and store the truncated results in "dst"
  • _mm256_div_epi16 Divide packed 16-bit integers in "a" by packed elements in "b", and store the truncated results in "dst"
  • _mm_div_epi32 Divide packed 32-bit integers in "a" by packed elements in "b", and store the truncated results in "dst"
  • _mm256_div_epi32 Divide packed 32-bit integers in "a" by packed elements in "b", and store the truncated results in "dst"
  • _mm_div_epi64 Divide packed 64-bit integers in "a" by packed elements in "b", and store the truncated results in "dst"
  • _mm256_div_epi64 Divide packed 64-bit integers in "a" by packed elements in "b", and store the truncated results in "dst"
  • _mm_div_epu8 Divide packed unsigned 8-bit integers in "a" by packed elements in "b", and store the truncated results in "dst"
  • _mm256_div_epu8 Divide packed unsigned 8-bit integers in "a" by packed elements in "b", and store the truncated results in "dst"
  • _mm_div_epu16 Divide packed unsigned 16-bit integers in "a" by packed elements in "b", and store the truncated results in "dst"
  • _mm256_div_epu16 Divide packed unsigned 16-bit integers in "a" by packed elements in "b", and store the truncated results in "dst"
  • _mm_div_epu32 Divide packed unsigned 32-bit integers in "a" by packed elements in "b", and store the truncated results in "dst"
  • _mm256_div_epu32 Divide packed unsigned 32-bit integers in "a" by packed elements in "b", and store the truncated results in "dst"
  • _mm_div_epu64 Divide packed unsigned 64-bit integers in "a" by packed elements in "b", and store the truncated results in "dst"
  • _mm256_div_epu64 Divide packed unsigned 64-bit integers in "a" by packed elements in "b", and store the truncated results in "dst"
  • _mm_div_pd Divide packed double-precision floating-point elements in "a" by packed elements in "b"
  • _mm256_div_pd Divide packed double-precision floating-point elements in "a" by packed elements in "b"
  • _mm_div_ps Divide packed single-precision floating-point elements in "a" by packed elements in "b"
  • _mm256_div_ps Divide packed single-precision floating-point elements in "a" by packed elements in "b"
  • _mm_div_sd Divide the lower double-precision floating-point element in "a" by the lower double-precision floating-point element in "b"
  • _mm_div_ss Divide the lower single-precision floating-point element in "a" by the lower single-precision floating-point element in "b"
  • _mm_dp_pd Conditionally multiply the packed double-precision floating-point elements in "a" and "b" using the high 4 bits in "imm8", sum the four products, and conditionally store the sum in "dst" using the low 4 bits of "imm8"
  • _mm_dp_ps Conditionally multiply the packed single-precision floating-point elements in "a" and "b" using the high 4 bits in "imm8", sum the four products, and conditionally store the sum in "dst" using the low 4 bits of "imm8"
  • _mm256_dp_ps Conditionally multiply the packed single-precision floating-point elements in "a" and "b" using the high 4 bits in "imm8", sum the four products, and conditionally store the sum in "dst" using the low 4 bits of "imm8"

E

  • _m_empty Empty the MMX state, which marks the x87 FPU registers as available for use by x87 instructions
  • _mm_empty Empty the MMX state, which marks the x87 FPU registers as available for use by x87 instructions
  • _encls_u32 Invoke the Intel SGX enclave system (privileged) leaf function specified by "a"
  • _enclu_u32 Invoke the Intel SGX enclave user (non-privilege) leaf function specified by "a"
  • _enclv_u32 Invoke the Intel SGX enclave virtualized (VMM) leaf function specified by "a"
  • _mm_erf_pd Compute the error function of packed double-precision floating-point elements in "a"
  • _mm256_erf_pd Compute the error function of packed double-precision floating-point elements in "a"
  • _mm_erf_ps Compute the error function of packed single-precision floating-point elements in "a"
  • _mm256_erf_ps Compute the error function of packed single-precision floating-point elements in "a"
  • _mm_erfc_pd Compute the complementary error function of packed double-precision floating-point elements in "a"
  • _mm256_erfc_pd Compute the complementary error function of packed double-precision floating-point elements in "a"
  • _mm_erfc_ps Compute the complementary error function of packed single-precision floating-point elements in "a"
  • _mm256_erfc_ps Compute the complementary error function of packed single-precision floating-point elements in "a"
  • _mm_erfcinv_pd Compute the inverse complementary error function of packed double-precision floating-point elements in "a"
  • _mm256_erfcinv_pd Compute the inverse complementary error function of packed double-precision floating-point elements in "a"
  • _mm_erfcinv_ps Compute the inverse complementary error function of packed single-precision floating-point elements in "a"
  • _mm256_erfcinv_ps Compute the inverse complementary error function of packed single-precision floating-point elements in "a"
  • _mm_erfinv_pd Compute the inverse error function of packed double-precision floating-point elements in "a"
  • _mm256_erfinv_pd Compute the inverse error function of packed double-precision floating-point elements in "a"
  • _mm_erfinv_ps Compute the inverse error function of packed single-precision floating-point elements in "a"
  • _mm256_erfinv_ps Compute the inverse error function of packed single-precision floating-point elements in "a"
  • _mm_exp_pd Compute the exponential value of "e" raised to the power of packed double-precision floating-point elements in "a"
  • _mm256_exp_pd Compute the exponential value of "e" raised to the power of packed double-precision floating-point elements in "a"
  • _mm_exp_ps Compute the exponential value of "e" raised to the power of packed single-precision floating-point elements in "a"
  • _mm256_exp_ps Compute the exponential value of "e" raised to the power of packed single-precision floating-point elements in "a"
  • _mm_exp10_pd Compute the exponential value of 10 raised to the power of packed double-precision floating-point elements in "a"
  • _mm256_exp10_pd Compute the exponential value of 10 raised to the power of packed double-precision floating-point elements in "a"
  • _mm_exp10_ps Compute the exponential value of 10 raised to the power of packed single-precision floating-point elements in "a"
  • _mm256_exp10_ps Compute the exponential value of 10 raised to the power of packed single-precision floating-point elements in "a"
  • _mm_exp2_pd Compute the exponential value of 2 raised to the power of packed double-precision floating-point elements in "a"
  • _mm256_exp2_pd Compute the exponential value of 2 raised to the power of packed double-precision floating-point elements in "a"
  • _mm_exp2_ps Compute the exponential value of 2 raised to the power of packed single-precision floating-point elements in "a"
  • _mm256_exp2_ps Compute the exponential value of 2 raised to the power of packed single-precision floating-point elements in "a"
  • _mm_expm1_pd Compute the exponential value of "e" raised to the power of packed double-precision floating-point elements in "a", subtract one from each element
  • _mm256_expm1_pd Compute the exponential value of "e" raised to the power of packed double-precision floating-point elements in "a", subtract one from each element
  • _mm_expm1_ps Compute the exponential value of "e" raised to the power of packed single-precision floating-point elements in "a", subtract one from each element
  • _mm256_expm1_ps Compute the exponential value of "e" raised to the power of packed single-precision floating-point elements in "a", subtract one from each element
  • _mm_extract_epi8 Extract an 8-bit integer from "a", selected with "imm8", and store the result in the lower element of "dst"
  • _mm256_extract_epi8 Extract an 8-bit integer from "a", selected with "index", and store the result in "dst"
  • _mm_extract_epi16 Extract a 16-bit integer from "a", selected with "imm8", and store the result in the lower element of "dst"
  • _mm256_extract_epi16 Extract a 16-bit integer from "a", selected with "index", and store the result in "dst"
  • _mm_extract_epi32 Extract a 32-bit integer from "a", selected with "imm8", and store the result in "dst"
  • _mm256_extract_epi32 Extract a 32-bit integer from "a", selected with "index", and store the result in "dst"
  • _mm_extract_epi64 Extract a 64-bit integer from "a", selected with "imm8", and store the result in "dst"
  • _mm256_extract_epi64 Extract a 64-bit integer from "a", selected with "index", and store the result in "dst"
  • _mm_extract_pi16 Extract a 16-bit integer from "a", selected with "imm8", and store the result in the lower element of "dst"
  • _mm_extract_ps Extract a single-precision floating-point element from "a", selected with "imm8"
  • _mm256_extractf128_pd Extract 128 bits (composed of 2 packed double-precision floating-point elements) from "a", selected with "imm8"
  • _mm256_extractf128_ps Extract 128 bits (composed of 4 packed single-precision floating-point elements) from "a", selected with "imm8"
  • _mm256_extractf128_si256 Extract 128 bits (composed of integer data) from "a", selected with "imm8"
  • _mm256_extracti128_si256 Extract 128 bits (composed of integer data) from "a", selected with "imm8"

F

  • _mm_floor_pd Round the packed double-precision floating-point elements in "a" down to an integer value
  • _mm256_floor_pd Round the packed double-precision floating-point elements in "a" down to an integer value
  • _mm_floor_ps Round the packed single-precision floating-point elements in "a" down to an integer value
  • _mm256_floor_ps Round the packed single-precision floating-point elements in "a" down to an integer value
  • _mm_floor_sd Round the lower double-precision floating-point element in "b" down to an integer value
  • _mm_floor_ss Round the lower single-precision floating-point element in "b" down to an integer value
  • _mm_fmadd_pd Multiply packed double-precision floating-point elements in "a" and "b", add the intermediate result to packed elements in "c"
  • _mm256_fmadd_pd Multiply packed double-precision floating-point elements in "a" and "b", add the intermediate result to packed elements in "c"
  • _mm_fmadd_ps Multiply packed single-precision floating-point elements in "a" and "b", add the intermediate result to packed elements in "c"
  • _mm256_fmadd_ps Multiply packed single-precision floating-point elements in "a" and "b", add the intermediate result to packed elements in "c"
  • _mm_fmadd_sd Multiply the lower double-precision floating-point elements in "a" and "b", and add the intermediate result to the lower element in "c"
  • _mm_fmadd_ss Multiply the lower single-precision floating-point elements in "a" and "b", and add the intermediate result to the lower element in "c"
  • _mm_fmaddsub_pd Multiply packed double-precision floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result
  • _mm256_fmaddsub_pd Multiply packed double-precision floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result
  • _mm_fmaddsub_ps Multiply packed single-precision floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result
  • _mm256_fmaddsub_ps Multiply packed single-precision floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result
  • _mm_fmsub_pd Multiply packed double-precision floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result
  • _mm256_fmsub_pd Multiply packed double-precision floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result
  • _mm_fmsub_ps Multiply packed single-precision floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result
  • _mm256_fmsub_ps Multiply packed single-precision floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result
  • _mm_fmsub_sd Multiply the lower double-precision floating-point elements in "a" and "b", and subtract the lower element in "c" from the intermediate result
  • _mm_fmsub_ss Multiply the lower single-precision floating-point elements in "a" and "b", and subtract the lower element in "c" from the intermediate result
  • _mm_fmsubadd_pd Multiply packed double-precision floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result
  • _mm256_fmsubadd_pd Multiply packed double-precision floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result
  • _mm_fmsubadd_ps Multiply packed single-precision floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result
  • _mm256_fmsubadd_ps Multiply packed single-precision floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result
  • _mm_fnmadd_pd Multiply packed double-precision floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c"
  • _mm256_fnmadd_pd Multiply packed double-precision floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c"
  • _mm_fnmadd_ps Multiply packed single-precision floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c"
  • _mm256_fnmadd_ps Multiply packed single-precision floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c"
  • _mm_fnmadd_sd Multiply the lower double-precision floating-point elements in "a" and "b", and add the negated intermediate result to the lower element in "c"
  • _mm_fnmadd_ss Multiply the lower single-precision floating-point elements in "a" and "b", and add the negated intermediate result to the lower element in "c"
  • _mm_fnmsub_pd Multiply packed double-precision floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result
  • _mm256_fnmsub_pd Multiply packed double-precision floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result
  • _mm_fnmsub_ps Multiply packed single-precision floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result
  • _mm256_fnmsub_ps Multiply packed single-precision floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result
  • _mm_fnmsub_sd Multiply the lower double-precision floating-point elements in "a" and "b", and subtract the lower element in "c" from the negated intermediate result
  • _mm_fnmsub_ss Multiply the lower single-precision floating-point elements in "a" and "b", and subtract the lower element in "c" from the negated intermediate result
  • _mm_free Free aligned memory that was allocated with "_mm_malloc".
  • _m_from_int Copy 32-bit integer "a" to the lower elements of "dst", and zero the upper element of "dst"
  • _m_from_int64 Copy 64-bit integer "a" to "dst".
  • _fxrstor Reload the x87 FPU, MMX technology, XMM, and MXCSR registers from the 512-byte memory image at "mem_addr"
  • _fxrstor64 Reload the x87 FPU, MMX technology, XMM, and MXCSR registers from the 512-byte memory image at "mem_addr"
  • _fxsave Save the current state of the x87 FPU, MMX technology, XMM, and MXCSR registers to a 512-byte memory location at "mem_addr"
  • _fxsave64 Save the current state of the x87 FPU, MMX technology, XMM, and MXCSR registers to a 512-byte memory location at "mem_addr"

G

  • _MM_GET_EXCEPTION_MASK Macro: Get the exception mask bits from the MXCSR control and status register
  • _MM_GET_EXCEPTION_STATE Macro: Get the exception state bits from the MXCSR control and status register
  • _MM_GET_FLUSH_ZERO_MODE Macro: Get the flush zero bits from the MXCSR control and status register
  • _MM_GET_ROUNDING_MODE Macro: Get the rounding mode bits from the MXCSR control and status register
  • _get_ssp If CET is enabled, read the low 32-bits of the current shadow stack pointer
  • _mm_getcsr Get the unsigned 32-bit value of the MXCSR control and status register

H

  • _mm_hadd_epi16 Horizontally add adjacent pairs of 16-bit integers in "a" and "b", and pack the signed 16-bit results in "dst"
  • _mm256_hadd_epi16 Horizontally add adjacent pairs of 16-bit integers in "a" and "b", and pack the signed 16-bit results in "dst"
  • _mm_hadd_epi32 Horizontally add adjacent pairs of 32-bit integers in "a" and "b", and pack the signed 32-bit results in "dst"
  • _mm256_hadd_epi32 Horizontally add adjacent pairs of 32-bit integers in "a" and "b", and pack the signed 32-bit results in "dst"
  • _mm_hadd_pd Horizontally add adjacent pairs of double-precision floating-point elements in "a" and "b", and pack the results in "dst"
  • _mm256_hadd_pd Horizontally add adjacent pairs of double-precision floating-point elements in "a" and "b", and pack the results in "dst"
  • _mm_hadd_pi16 Horizontally add adjacent pairs of 16-bit integers in "a" and "b", and pack the signed 16-bit results in "dst"
  • _mm_hadd_pi32 Horizontally add adjacent pairs of 32-bit integers in "a" and "b", and pack the signed 32-bit results in "dst"
  • _mm_hadd_ps Horizontally add adjacent pairs of single-precision floating-point elements in "a" and "b", and pack the results in "dst"
  • _mm256_hadd_ps Horizontally add adjacent pairs of single-precision floating-point elements in "a" and "b", and pack the results in "dst"
  • _mm_hadds_epi16 Horizontally add adjacent pairs of 16-bit integers in "a" and "b" using saturation, and pack the signed 16-bit results in "dst"
  • _mm256_hadds_epi16 Horizontally add adjacent pairs of 16-bit integers in "a" and "b" using saturation, and pack the signed 16-bit results in "dst"
  • _mm_hadds_pi16 Horizontally add adjacent pairs of 16-bit integers in "a" and "b" using saturation, and pack the signed 16-bit results in "dst"
  • _mm_hsub_epi16 Horizontally subtract adjacent pairs of 16-bit integers in "a" and "b", and pack the signed 16-bit results in "dst"
  • _mm256_hsub_epi16 Horizontally subtract adjacent pairs of 16-bit integers in "a" and "b", and pack the signed 16-bit results in "dst"
  • _mm_hsub_epi32 Horizontally subtract adjacent pairs of 32-bit integers in "a" and "b", and pack the signed 32-bit results in "dst"
  • _mm256_hsub_epi32 Horizontally subtract adjacent pairs of 32-bit integers in "a" and "b", and pack the signed 32-bit results in "dst"
  • _mm_hsub_pd Horizontally subtract adjacent pairs of double-precision floating-point elements in "a" and "b", and pack the results in "dst"
  • _mm256_hsub_pd Horizontally subtract adjacent pairs of double-precision floating-point elements in "a" and "b", and pack the results in "dst"
  • _mm_hsub_pi16 Horizontally subtract adjacent pairs of 16-bit integers in "a" and "b", and pack the signed 16-bit results in "dst"
  • _mm_hsub_pi32 Horizontally subtract adjacent pairs of 32-bit integers in "a" and "b", and pack the signed 32-bit results in "dst"
  • _mm_hsub_ps Horizontally add adjacent pairs of single-precision floating-point elements in "a" and "b", and pack the results in "dst"
  • _mm256_hsub_ps Horizontally add adjacent pairs of single-precision floating-point elements in "a" and "b", and pack the results in "dst"
  • _mm_hsubs_epi16 Horizontally subtract adjacent pairs of 16-bit integers in "a" and "b" using saturation, and pack the signed 16-bit results in "dst"
  • _mm256_hsubs_epi16 Horizontally subtract adjacent pairs of 16-bit integers in "a" and "b" using saturation, and pack the signed 16-bit results in "dst"
  • _mm_hsubs_pi16 Horizontally subtract adjacent pairs of 16-bit integers in "a" and "b" using saturation, and pack the signed 16-bit results in "dst"
  • _mm_hypot_pd Compute the length of the hypotenous of a right triangle, with the lengths of the other two sides of the triangle stored as packed double-precision floating-point elements in "a" and "b"
  • _mm256_hypot_pd Compute the length of the hypotenous of a right triangle, with the lengths of the other two sides of the triangle stored as packed double-precision floating-point elements in "a" and "b"
  • _mm_hypot_ps Compute the length of the hypotenous of a right triangle, with the lengths of the other two sides of the triangle stored as packed single-precision floating-point elements in "a" and "b"
  • _mm256_hypot_ps Compute the length of the hypotenous of a right triangle, with the lengths of the other two sides of the triangle stored as packed single-precision floating-point elements in "a" and "b"

I

  • _mm_i32gather_epi32 Gather 32-bit integers from memory using 32-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.
  • _mm256_i32gather_epi32 Gather 32-bit integers from memory using 32-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.
  • _mm_i32gather_epi64 Gather 64-bit integers from memory using 32-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.
  • _mm256_i32gather_epi64 Gather 64-bit integers from memory using 32-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.
  • _mm_i32gather_pd Gather double-precision floating-point elements from memory using 32-bit indices
  • _mm256_i32gather_pd Gather double-precision floating-point elements from memory using 32-bit indices
  • _mm_i32gather_ps Gather single-precision floating-point elements from memory using 32-bit indices
  • _mm256_i32gather_ps Gather single-precision floating-point elements from memory using 32-bit indices
  • _mm_i64gather_epi32 Gather 32-bit integers from memory using 64-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.
  • _mm256_i64gather_epi32 Gather 32-bit integers from memory using 64-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.
  • _mm_i64gather_epi64 Gather 64-bit integers from memory using 64-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.
  • _mm256_i64gather_epi64 Gather 64-bit integers from memory using 64-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.
  • _mm_i64gather_pd Gather double-precision floating-point elements from memory using 64-bit indices
  • _mm256_i64gather_pd Gather double-precision floating-point elements from memory using 64-bit indices
  • _mm_i64gather_ps Gather single-precision floating-point elements from memory using 64-bit indices
  • _mm256_i64gather_ps Gather single-precision floating-point elements from memory using 64-bit indices
  • _mm_idiv_epi32 Divide packed 32-bit integers in "a" by packed elements in "b", and store the truncated results in "dst"
  • _mm256_idiv_epi32 Divide packed 32-bit integers in "a" by packed elements in "b", and store the truncated results in "dst"
  • _mm_idivrem_epi32 Divide packed 32-bit integers in "a" by packed elements in "b", store the truncated results in "dst", and store the remainders as packed 32-bit integers into memory at "mem_addr"
  • _mm256_idivrem_epi32 Divide packed 32-bit integers in "a" by packed elements in "b", store the truncated results in "dst", and store the remainders as packed 32-bit integers into memory at "mem_addr"
  • _inc_ssp Increment the shadow stack pointer by 4 times the value specified in bits [7:0] of "a"
  • _incsspd Increment the shadow stack pointer by 4 times the value specified in bits [7:0] of "a"
  • _incsspq Increment the shadow stack pointer by 8 times the value specified in bits [7:0] of "a"
  • _mm_insert_epi8 Copy "a" to "dst", and insert the lower 8-bit integer from "i" into "dst" at the location specified by "imm8"
  • _mm256_insert_epi8 Copy "a" to "dst", and insert the 8-bit integer "i" into "dst" at the location specified by "index"
  • _mm_insert_epi16 Copy "a" to "dst", and insert the 16-bit integer "i" into "dst" at the location specified by "imm8"
  • _mm256_insert_epi16 Copy "a" to "dst", and insert the 16-bit integer "i" into "dst" at the location specified by "index"
  • _mm_insert_epi32 Copy "a" to "dst", and insert the 32-bit integer "i" into "dst" at the location specified by "imm8"
  • _mm256_insert_epi32 Copy "a" to "dst", and insert the 32-bit integer "i" into "dst" at the location specified by "index"
  • _mm_insert_epi64 Copy "a" to "dst", and insert the 64-bit integer "i" into "dst" at the location specified by "imm8"
  • _mm256_insert_epi64 Copy "a" to "dst", and insert the 64-bit integer "i" into "dst" at the location specified by "index"
  • _mm_insert_pi16 Copy "a" to "dst", and insert the 16-bit integer "i" into "dst" at the location specified by "imm8"
  • _mm_insert_ps Copy "a" to "tmp", then insert a single-precision floating-point element from "b" into "tmp" using the control in "imm8"
  • _mm256_insertf128_pd Copy "a" to "dst", then insert 128 bits (composed of 2 packed double-precision floating-point elements) from "b" into "dst" at the location specified by "imm8"
  • _mm256_insertf128_ps Copy "a" to "dst", then insert 128 bits (composed of 4 packed single-precision floating-point elements) from "b" into "dst" at the location specified by "imm8"
  • _mm256_insertf128_si256 Copy "a" to "dst", then insert 128 bits from "b" into "dst" at the location specified by "imm8"
  • _mm256_inserti128_si256 Copy "a" to "dst", then insert 128 bits (composed of integer data) from "b" into "dst" at the location specified by "imm8"
  • _mm_invcbrt_pd Compute the inverse cube root of packed double-precision floating-point elements in "a"
  • _mm256_invcbrt_pd Compute the inverse cube root of packed double-precision floating-point elements in "a"
  • _mm_invcbrt_ps Compute the inverse cube root of packed single-precision floating-point elements in "a"
  • _mm256_invcbrt_ps Compute the inverse cube root of packed single-precision floating-point elements in "a"
  • _invpcid Invalidate mappings in the Translation Lookaside Buffers (TLBs) and paging-structure caches for the processor context identifier (PCID) specified by "descriptor" based on the invalidation type specified in "type"
  • _mm_invsqrt_pd Compute the inverse square root of packed double-precision floating-point elements in "a"
  • _mm256_invsqrt_pd Compute the inverse square root of packed double-precision floating-point elements in "a"
  • _mm_invsqrt_ps Compute the inverse square root of packed single-precision floating-point elements in "a"
  • _mm256_invsqrt_ps Compute the inverse square root of packed single-precision floating-point elements in "a"
  • _mm_irem_epi32 Divide packed 32-bit integers in "a" by packed elements in "b", and store the remainders as packed 32-bit integers in "dst"
  • _mm256_irem_epi32 Divide packed 32-bit integers in "a" by packed elements in "b", and store the remainders as packed 32-bit integers in "dst"

L

  • _mm_lddqu_si128 Load 128-bits of integer data from unaligned memory into "dst". This intrinsic may perform better than "_mm_loadu_si128" when the data crosses a cache line boundary.
  • _mm256_lddqu_si256 Load 256-bits of integer data from unaligned memory into "dst". This intrinsic may perform better than "_mm256_loadu_si256" when the data crosses a cache line boundary.
  • _mm_lfence Perform a serializing operation on all load-from-memory instructions that were issued prior to this instruction
  • _mm_load_pd Load 128-bits (composed of 2 packed double-precision floating-point elements) from memory into "dst"
  • _mm256_load_pd Load 256-bits (composed of 4 packed double-precision floating-point elements) from memory into "dst"
  • _mm_load_pd1 Load a double-precision floating-point element from memory into both elements of "dst"
  • _mm_load_ps Load 128-bits (composed of 4 packed single-precision floating-point elements) from memory into "dst"
  • _mm256_load_ps Load 256-bits (composed of 8 packed single-precision floating-point elements) from memory into "dst"
  • _mm_load_ps1 Load a single-precision floating-point element from memory into all elements of "dst"
  • _mm_load_sd Load a double-precision floating-point element from memory into the lower of "dst", and zero the upper element
  • _mm_load_si128 Load 128-bits of integer data from memory into "dst". "mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.
  • _mm256_load_si256 Load 256-bits of integer data from memory into "dst". "mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.
  • _mm_load_ss Load a single-precision floating-point element from memory into the lower of "dst", and zero the upper 3 elements
  • _mm_load1_pd Load a double-precision floating-point element from memory into both elements of "dst"
  • _mm_load1_ps Load a single-precision floating-point element from memory into all elements of "dst"
  • _loadbe_i16 Load 16 bits from memory, perform a byte swap operation, and store the result in "dst"
  • _loadbe_i32 Load 32 bits from memory, perform a byte swap operation, and store the result in "dst"
  • _loadbe_i64 Load 64 bits from memory, perform a byte swap operation, and store the result in "dst"
  • _mm_loaddup_pd Load a double-precision floating-point element from memory into both elements of "dst"
  • _mm_loadh_pd Load a double-precision floating-point element from memory into the upper element of "dst", and copy the lower element from "a" to "dst"
  • _mm_loadh_pi Load 2 single-precision floating-point elements from memory into the upper 2 elements of "dst", and copy the lower 2 elements from "a" to "dst"
  • _mm_loadl_epi64 Load 64-bit integer from memory into the first element of "dst".
  • _mm_loadl_pd Load a double-precision floating-point element from memory into the lower element of "dst", and copy the upper element from "a" to "dst"
  • _mm_loadl_pi Load 2 single-precision floating-point elements from memory into the lower 2 elements of "dst", and copy the upper 2 elements from "a" to "dst"
  • _mm_loadr_pd Load 2 double-precision floating-point elements from memory into "dst" in reverse order
  • _mm_loadr_ps Load 4 single-precision floating-point elements from memory into "dst" in reverse order
  • _mm_loadu_pd Load 128-bits (composed of 2 packed double-precision floating-point elements) from memory into "dst"
  • _mm256_loadu_pd Load 256-bits (composed of 4 packed double-precision floating-point elements) from memory into "dst"
  • _mm_loadu_ps Load 128-bits (composed of 4 packed single-precision floating-point elements) from memory into "dst"
  • _mm256_loadu_ps Load 256-bits (composed of 8 packed single-precision floating-point elements) from memory into "dst"
  • _mm_loadu_si16 Load unaligned 16-bit integer from memory into the first element of "dst"
  • _mm_loadu_si32 Load unaligned 32-bit integer from memory into the first element of "dst"
  • _mm_loadu_si64 Load unaligned 64-bit integer from memory into the first element of "dst"
  • _mm_loadu_si128 Load 128-bits of integer data from memory into "dst". "mem_addr" does not need to be aligned on any particular boundary.
  • _mm256_loadu_si256 Load 256-bits of integer data from memory into "dst". "mem_addr" does not need to be aligned on any particular boundary.
  • _mm256_loadu2_m128 Load two 128-bit values (composed of 4 packed single-precision floating-point elements) from memory, and combine them into a 256-bit value in "dst"
  • _mm256_loadu2_m128d Load two 128-bit values (composed of 2 packed double-precision floating-point elements) from memory, and combine them into a 256-bit value in "dst"
  • _mm256_loadu2_m128i Load two 128-bit values (composed of integer data) from memory, and combine them into a 256-bit value in "dst"
  • _mm_log_pd Compute the natural logarithm of packed double-precision floating-point elements in "a"
  • _mm256_log_pd Compute the natural logarithm of packed double-precision floating-point elements in "a"
  • _mm_log_ps Compute the natural logarithm of packed single-precision floating-point elements in "a"
  • _mm256_log_ps Compute the natural logarithm of packed single-precision floating-point elements in "a"
  • _mm_log10_pd Compute the base-10 logarithm of packed double-precision floating-point elements in "a"
  • _mm256_log10_pd Compute the base-10 logarithm of packed double-precision floating-point elements in "a"
  • _mm_log10_ps Compute the base-10 logarithm of packed single-precision floating-point elements in "a"
  • _mm256_log10_ps Compute the base-10 logarithm of packed single-precision floating-point elements in "a"
  • _mm_log1p_pd Compute the natural logarithm of one plus packed double-precision floating-point elements in "a"
  • _mm256_log1p_pd Compute the natural logarithm of one plus packed double-precision floating-point elements in "a"
  • _mm_log1p_ps Compute the natural logarithm of one plus packed single-precision floating-point elements in "a"
  • _mm256_log1p_ps Compute the natural logarithm of one plus packed single-precision floating-point elements in "a"
  • _mm_log2_pd Compute the base-2 logarithm of packed double-precision floating-point elements in "a"
  • _mm256_log2_pd Compute the base-2 logarithm of packed double-precision floating-point elements in "a"
  • _mm_log2_ps Compute the base-2 logarithm of packed single-precision floating-point elements in "a"
  • _mm256_log2_ps Compute the base-2 logarithm of packed single-precision floating-point elements in "a"
  • _mm_logb_pd Convert the exponent of each packed double-precision floating-point element in "a" to a double-precision floating-point number representing the integer exponent
  • _mm256_logb_pd Convert the exponent of each packed double-precision floating-point element in "a" to a double-precision floating-point number representing the integer exponent
  • _mm_logb_ps Convert the exponent of each packed single-precision floating-point element in "a" to a single-precision floating-point number representing the integer exponent
  • _mm256_logb_ps Convert the exponent of each packed single-precision floating-point element in "a" to a single-precision floating-point number representing the integer exponent
  • _lrotl Shift the bits of unsigned long integer "a" left by the number of bits specified in "shift"
  • _lrotr Shift the bits of unsigned long integer "a" right by the number of bits specified in "shift"
  • _lzcnt_u32 Count the number of leading zero bits in unsigned 32-bit integer "a"
  • _lzcnt_u64 Count the number of leading zero bits in unsigned 64-bit integer "a"

M

  • _mm_madd_epi16 Multiply packed signed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers
  • _mm256_madd_epi16 Multiply packed signed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers
  • _mm_madd_pi16 Multiply packed 16-bit integers in "a" and "b", producing intermediate 32-bit integers
  • _mm_maddubs_epi16 Vertically multiply each unsigned 8-bit integer from "a" with the corresponding signed 8-bit integer from "b", producing intermediate signed 16-bit integers
  • _mm256_maddubs_epi16 Vertically multiply each unsigned 8-bit integer from "a" with the corresponding signed 8-bit integer from "b", producing intermediate signed 16-bit integers
  • _mm_maddubs_pi16 Vertically multiply each unsigned 8-bit integer from "a" with the corresponding signed 8-bit integer from "b", producing intermediate signed 16-bit integers
  • _mm_malloc Allocate "size" bytes of memory, aligned to the alignment specified in "align"
  • _mm_mask_i32gather_epi32 Gather 32-bit integers from memory using 32-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8.
  • _mm256_mask_i32gather_epi32 Gather 32-bit integers from memory using 32-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8.
  • _mm_mask_i32gather_epi64 Gather 64-bit integers from memory using 32-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8.
  • _mm256_mask_i32gather_epi64 Gather 64-bit integers from memory using 32-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8.
  • _mm_mask_i32gather_pd Gather double-precision floating-point elements from memory using 32-bit indices
  • _mm256_mask_i32gather_pd Gather double-precision floating-point elements from memory using 32-bit indices
  • _mm_mask_i32gather_ps Gather single-precision floating-point elements from memory using 32-bit indices
  • _mm256_mask_i32gather_ps Gather single-precision floating-point elements from memory using 32-bit indices
  • _mm_mask_i64gather_epi32 Gather 32-bit integers from memory using 64-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8.
  • _mm256_mask_i64gather_epi32 Gather 32-bit integers from memory using 64-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8.
  • _mm_mask_i64gather_epi64 Gather 64-bit integers from memory using 64-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8.
  • _mm256_mask_i64gather_epi64 Gather 64-bit integers from memory using 64-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8.
  • _mm_mask_i64gather_pd Gather double-precision floating-point elements from memory using 64-bit indices
  • _mm256_mask_i64gather_pd Gather double-precision floating-point elements from memory using 64-bit indices
  • _mm_mask_i64gather_ps Gather single-precision floating-point elements from memory using 64-bit indices
  • _mm256_mask_i64gather_ps Gather single-precision floating-point elements from memory using 64-bit indices
  • _mm_maskload_epi32 Load packed 32-bit integers from memory into "dst" using "mask" (elements are zeroed out when the highest bit is not set in the corresponding element)
  • _mm256_maskload_epi32 Load packed 32-bit integers from memory into "dst" using "mask" (elements are zeroed out when the highest bit is not set in the corresponding element)
  • _mm_maskload_epi64 Load packed 64-bit integers from memory into "dst" using "mask" (elements are zeroed out when the highest bit is not set in the corresponding element)
  • _mm256_maskload_epi64 Load packed 64-bit integers from memory into "dst" using "mask" (elements are zeroed out when the highest bit is not set in the corresponding element)
  • _mm256_maskload_pd Load packed double-precision floating-point elements from memory into "dst" using "mask" (elements are zeroed out when the high bit of the corresponding element is not set)
  • _mm_maskload_pd Load packed double-precision floating-point elements from memory into "dst" using "mask" (elements are zeroed out when the high bit of the corresponding element is not set)
  • _mm256_maskload_ps Load packed single-precision floating-point elements from memory into "dst" using "mask" (elements are zeroed out when the high bit of the corresponding element is not set)
  • _mm_maskload_ps Load packed single-precision floating-point elements from memory into "dst" using "mask" (elements are zeroed out when the high bit of the corresponding element is not set)
  • _mm_maskmove_si64 Conditionally store 8-bit integer elements from "a" into memory using "mask" (elements are not stored when the highest bit is not set in the corresponding element) and a non-temporal memory hint
  • _mm_maskmoveu_si128 Conditionally store 8-bit integer elements from "a" into memory using "mask" (elements are not stored when the highest bit is not set in the corresponding element) and a non-temporal memory hint
  • _m_maskmovq Conditionally store 8-bit integer elements from "a" into memory using "mask" (elements are not stored when the highest bit is not set in the corresponding element)
  • _mm_maskstore_epi32 Store packed 32-bit integers from "a" into memory using "mask" (elements are not stored when the highest bit is not set in the corresponding element)
  • _mm256_maskstore_epi32 Store packed 32-bit integers from "a" into memory using "mask" (elements are not stored when the highest bit is not set in the corresponding element)
  • _mm_maskstore_epi64 Store packed 64-bit integers from "a" into memory using "mask" (elements are not stored when the highest bit is not set in the corresponding element)
  • _mm256_maskstore_epi64 Store packed 64-bit integers from "a" into memory using "mask" (elements are not stored when the highest bit is not set in the corresponding element)
  • _mm256_maskstore_pd Store packed double-precision floating-point elements from "a" into memory using "mask"
  • _mm_maskstore_pd Store packed double-precision floating-point elements from "a" into memory using "mask"
  • _mm256_maskstore_ps Store packed single-precision floating-point elements from "a" into memory using "mask"
  • _mm_maskstore_ps Store packed single-precision floating-point elements from "a" into memory using "mask"
  • _mm_max_epi8 Compare packed 8-bit integers in "a" and "b", and store packed maximum values in "dst"
  • _mm256_max_epi8 Compare packed 8-bit integers in "a" and "b", and store packed maximum values in "dst"
  • _mm_max_epi16 Compare packed 16-bit integers in "a" and "b", and store packed maximum values in "dst"
  • _mm256_max_epi16 Compare packed 16-bit integers in "a" and "b", and store packed maximum values in "dst"
  • _mm_max_epi32 Compare packed 32-bit integers in "a" and "b", and store packed maximum values in "dst"
  • _mm256_max_epi32 Compare packed 32-bit integers in "a" and "b", and store packed maximum values in "dst"
  • _mm_max_epu8 Compare packed unsigned 8-bit integers in "a" and "b", and store packed maximum values in "dst"
  • _mm256_max_epu8 Compare packed unsigned 8-bit integers in "a" and "b", and store packed maximum values in "dst"
  • _mm_max_epu16 Compare packed unsigned 16-bit integers in "a" and "b", and store packed maximum values in "dst"
  • _mm256_max_epu16 Compare packed unsigned 16-bit integers in "a" and "b", and store packed maximum values in "dst"
  • _mm_max_epu32 Compare packed unsigned 32-bit integers in "a" and "b", and store packed maximum values in "dst"
  • _mm256_max_epu32 Compare packed unsigned 32-bit integers in "a" and "b", and store packed maximum values in "dst"
  • _mm_max_pd Compare packed double-precision floating-point elements in "a" and "b", and store packed maximum values in "dst"
  • _mm256_max_pd Compare packed double-precision floating-point elements in "a" and "b", and store packed maximum values in "dst"
  • _mm_max_pi16 Compare packed 16-bit integers in "a" and "b", and store packed maximum values in "dst"
  • _mm_max_ps Compare packed single-precision floating-point elements in "a" and "b", and store packed maximum values in "dst"
  • _mm256_max_ps Compare packed single-precision floating-point elements in "a" and "b", and store packed maximum values in "dst"
  • _mm_max_pu8 Compare packed unsigned 8-bit integers in "a" and "b", and store packed maximum values in "dst"
  • _mm_max_sd Compare the lower double-precision floating-point elements in "a" and "b", store the maximum value in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst"
  • _mm_max_ss Compare the lower single-precision floating-point elements in "a" and "b", store the maximum value in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst"
  • _may_i_use_cpu_feature Dynamically query the processor to determine if the processor-specific feature(s) specified in "a" are available
  • _mm_mfence Perform a serializing operation on all load-from-memory and store-to-memory instructions that were issued prior to this instruction
  • _mm_min_epi8 Compare packed 8-bit integers in "a" and "b", and store packed minimum values in "dst"
  • _mm256_min_epi8 Compare packed 8-bit integers in "a" and "b", and store packed minimum values in "dst"
  • _mm_min_epi16 Compare packed 16-bit integers in "a" and "b", and store packed minimum values in "dst"
  • _mm256_min_epi16 Compare packed 16-bit integers in "a" and "b", and store packed minimum values in "dst"
  • _mm_min_epi32 Compare packed 32-bit integers in "a" and "b", and store packed minimum values in "dst"
  • _mm256_min_epi32 Compare packed 32-bit integers in "a" and "b", and store packed minimum values in "dst"
  • _mm_min_epu8 Compare packed unsigned 8-bit integers in "a" and "b", and store packed minimum values in "dst"
  • _mm256_min_epu8 Compare packed unsigned 8-bit integers in "a" and "b", and store packed minimum values in "dst"
  • _mm_min_epu16 Compare packed unsigned 16-bit integers in "a" and "b", and store packed minimum values in "dst"
  • _mm256_min_epu16 Compare packed unsigned 16-bit integers in "a" and "b", and store packed minimum values in "dst"
  • _mm_min_epu32 Compare packed unsigned 32-bit integers in "a" and "b", and store packed minimum values in "dst"
  • _mm256_min_epu32 Compare packed unsigned 32-bit integers in "a" and "b", and store packed minimum values in "dst"
  • _mm_min_pd Compare packed double-precision floating-point elements in "a" and "b", and store packed minimum values in "dst"
  • _mm256_min_pd Compare packed double-precision floating-point elements in "a" and "b", and store packed minimum values in "dst"
  • _mm_min_pi16 Compare packed 16-bit integers in "a" and "b", and store packed minimum values in "dst"
  • _mm_min_ps Compare packed single-precision floating-point elements in "a" and "b", and store packed minimum values in "dst"
  • _mm256_min_ps Compare packed single-precision floating-point elements in "a" and "b", and store packed minimum values in "dst"
  • _mm_min_pu8 Compare packed unsigned 8-bit integers in "a" and "b", and store packed minimum values in "dst"
  • _mm_min_sd Compare the lower double-precision floating-point elements in "a" and "b", store the minimum value in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst"
  • _mm_min_ss Compare the lower single-precision floating-point elements in "a" and "b", store the minimum value in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst"
  • _mm_minpos_epu16 Horizontally compute the minimum amongst the packed unsigned 16-bit integers in "a", store the minimum and index in "dst", and zero the remaining bits in "dst"
  • _mm_monitor Arm address monitoring hardware using the address specified in "p"
  • _movdir64b Move 64-byte (512-bit) value using direct store from source memory address "src" to destination memory address "dst"
  • _mm_move_epi64 Copy the lower 64-bit integer in "a" to the lower element of "dst", and zero the upper element
  • _mm_move_sd Move the lower double-precision floating-point element from "b" to the lower element of "dst", and copy the upper element from "a" to the upper element of "dst"
  • _mm_move_ss Move the lower single-precision floating-point element from "b" to the lower element of "dst", and copy the upper 3 elements from "a" to the upper elements of "dst"
  • _mm_movedup_pd Duplicate the low double-precision floating-point element from "a"
  • _mm256_movedup_pd Duplicate even-indexed double-precision floating-point elements from "a"
  • _mm_movehdup_ps Duplicate odd-indexed single-precision floating-point elements from "a"
  • _mm256_movehdup_ps Duplicate odd-indexed single-precision floating-point elements from "a"
  • _mm_movehl_ps Move the upper 2 single-precision floating-point elements from "b" to the lower 2 elements of "dst", and copy the upper 2 elements from "a" to the upper 2 elements of "dst"
  • _mm_moveldup_ps Duplicate even-indexed single-precision floating-point elements from "a"
  • _mm256_moveldup_ps Duplicate even-indexed single-precision floating-point elements from "a"
  • _mm_movelh_ps Move the lower 2 single-precision floating-point elements from "b" to the upper 2 elements of "dst", and copy the lower 2 elements from "a" to the lower 2 elements of "dst"
  • _mm_movemask_epi8 Create mask from the most significant bit of each 8-bit element in "a"
  • _mm256_movemask_epi8 Create mask from the most significant bit of each 8-bit element in "a"
  • _mm_movemask_pd Set each bit of mask "dst" based on the most significant bit of the corresponding packed double-precision floating-point element in "a"
  • _mm256_movemask_pd Set each bit of mask "dst" based on the most significant bit of the corresponding packed double-precision floating-point element in "a"
  • _mm_movemask_pi8 Create mask from the most significant bit of each 8-bit element in "a"
  • _mm_movemask_ps Set each bit of mask "dst" based on the most significant bit of the corresponding packed single-precision floating-point element in "a"
  • _mm256_movemask_ps Set each bit of mask "dst" based on the most significant bit of the corresponding packed single-precision floating-point element in "a"
  • _mm_movepi64_pi64 Copy the lower 64-bit integer in "a" to "dst".
  • _mm_movpi64_epi64 Copy the 64-bit integer "a" to the lower element of "dst", and zero the upper element
  • _mm_mpsadbw_epu8 Compute the sum of absolute differences (SADs) of quadruplets of unsigned 8-bit integers in "a" compared to those in "b", and store the 16-bit results in "dst"
  • _mm256_mpsadbw_epu8 Compute the sum of absolute differences (SADs) of quadruplets of unsigned 8-bit integers in "a" compared to those in "b", and store the 16-bit results in "dst"
  • _mm_mul_epi32 Multiply the low 32-bit integers from each packed 64-bit element in "a" and "b", and store the signed 64-bit results in "dst"
  • _mm256_mul_epi32 Multiply the low 32-bit integers from each packed 64-bit element in "a" and "b", and store the signed 64-bit results in "dst"
  • _mm_mul_epu32 Multiply the low unsigned 32-bit integers from each packed 64-bit element in "a" and "b", and store the unsigned 64-bit results in "dst"
  • _mm256_mul_epu32 Multiply the low unsigned 32-bit integers from each packed 64-bit element in "a" and "b", and store the unsigned 64-bit results in "dst"
  • _mm_mul_pd Multiply packed double-precision floating-point elements in "a" and "b"
  • _mm256_mul_pd Multiply packed double-precision floating-point elements in "a" and "b"
  • _mm_mul_ps Multiply packed single-precision floating-point elements in "a" and "b"
  • _mm256_mul_ps Multiply packed single-precision floating-point elements in "a" and "b"
  • _mm_mul_sd Multiply the lower double-precision floating-point element in "a" and "b"
  • _mm_mul_ss Multiply the lower single-precision floating-point element in "a" and "b"
  • _mm_mul_su32 Multiply the low unsigned 32-bit integers from "a" and "b", and store the unsigned 64-bit result in "dst"
  • _mm_mulhi_epi16 Multiply the packed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst"
  • _mm256_mulhi_epi16 Multiply the packed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst"
  • _mm_mulhi_epu16 Multiply the packed unsigned 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst"
  • _mm256_mulhi_epu16 Multiply the packed unsigned 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst"
  • _mm_mulhi_pi16 Multiply the packed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst"
  • _mm_mulhi_pu16 Multiply the packed unsigned 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst"
  • _mm_mulhrs_epi16 Multiply packed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers
  • _mm256_mulhrs_epi16 Multiply packed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers
  • _mm_mulhrs_pi16 Multiply packed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers
  • _mm_mullo_epi16 Multiply the packed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the low 16 bits of the intermediate integers in "dst"
  • _mm256_mullo_epi16 Multiply the packed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the low 16 bits of the intermediate integers in "dst"
  • _mm_mullo_epi32 Multiply the packed 32-bit integers in "a" and "b", producing intermediate 64-bit integers, and store the low 32 bits of the intermediate integers in "dst"
  • _mm256_mullo_epi32 Multiply the packed 32-bit integers in "a" and "b", producing intermediate 64-bit integers, and store the low 32 bits of the intermediate integers in "dst"
  • _mm_mullo_pi16 Multiply the packed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the low 16 bits of the intermediate integers in "dst"
  • _mulx_u32 Multiply unsigned 32-bit integers "a" and "b", store the low 32-bits of the result in "dst", and store the high 32-bits in "hi"
  • _mulx_u64 Multiply unsigned 64-bit integers "a" and "b", store the low 64-bits of the result in "dst", and store the high 64-bits in "hi"
  • _mm_mwait Hint to the processor that it can enter an implementation-dependent-optimized state while waiting for an event or store operation to the address range specified by MONITOR

O

  • _mm_or_pd Compute the bitwise OR of packed double-precision floating-point elements in "a" and "b"
  • _mm256_or_pd Compute the bitwise OR of packed double-precision floating-point elements in "a" and "b"
  • _mm_or_ps Compute the bitwise OR of packed single-precision floating-point elements in "a" and "b"
  • _mm256_or_ps Compute the bitwise OR of packed single-precision floating-point elements in "a" and "b"
  • _mm_or_si64 Compute the bitwise OR of 64 bits (representing integer data) in "a" and "b"
  • _mm_or_si128 Compute the bitwise OR of 128 bits (representing integer data) in "a" and "b"
  • _mm256_or_si256 Compute the bitwise OR of 256 bits (representing integer data) in "a" and "b"

P

  • _mm_packs_epi16 Convert packed 16-bit integers from "a" and "b" to packed 8-bit integers using signed saturation
  • _mm256_packs_epi16 Convert packed 16-bit integers from "a" and "b" to packed 8-bit integers using signed saturation
  • _mm_packs_epi32 Convert packed 32-bit integers from "a" and "b" to packed 16-bit integers using signed saturation
  • _mm256_packs_epi32 Convert packed 32-bit integers from "a" and "b" to packed 16-bit integers using signed saturation
  • _mm_packs_pi16 Convert packed 16-bit integers from "a" and "b" to packed 8-bit integers using signed saturation
  • _mm_packs_pi32 Convert packed 32-bit integers from "a" and "b" to packed 16-bit integers using signed saturation
  • _mm_packs_pu16 Convert packed 16-bit integers from "a" and "b" to packed 8-bit integers using unsigned saturation
  • _m_packssdw Convert packed 32-bit integers from "a" and "b" to packed 16-bit integers using signed saturation
  • _m_packsswb Convert packed 16-bit integers from "a" and "b" to packed 8-bit integers using signed saturation
  • _mm_packus_epi16 Convert packed 16-bit integers from "a" and "b" to packed 8-bit integers using unsigned saturation
  • _mm256_packus_epi16 Convert packed 16-bit integers from "a" and "b" to packed 8-bit integers using unsigned saturation
  • _mm_packus_epi32 Convert packed 32-bit integers from "a" and "b" to packed 16-bit integers using unsigned saturation
  • _mm256_packus_epi32 Convert packed 32-bit integers from "a" and "b" to packed 16-bit integers using unsigned saturation
  • _m_packuswb Convert packed 16-bit integers from "a" and "b" to packed 8-bit integers using unsigned saturation
  • _m_paddb Add packed 8-bit integers in "a" and "b", and store the results in "dst"
  • _m_paddd Add packed 32-bit integers in "a" and "b", and store the results in "dst"
  • _m_paddsb Add packed 8-bit integers in "a" and "b" using saturation, and store the results in "dst"
  • _m_paddsw Add packed 16-bit integers in "a" and "b" using saturation, and store the results in "dst"
  • _m_paddusb Add packed unsigned 8-bit integers in "a" and "b" using saturation
  • _m_paddusw Add packed unsigned 16-bit integers in "a" and "b" using saturation
  • _m_paddw Add packed 16-bit integers in "a" and "b", and store the results in "dst"
  • _m_pand Compute the bitwise AND of 64 bits (representing integer data) in "a" and "b"
  • _m_pandn Compute the bitwise NOT of 64 bits (representing integer data) in "a" and then AND with "b"
  • _mm_pause Provide a hint to the processor that the code sequence is a spin-wait loop
  • _m_pavgb Average packed unsigned 8-bit integers in "a" and "b", and store the results in "dst"
  • _m_pavgw Average packed unsigned 16-bit integers in "a" and "b", and store the results in "dst"
  • _m_pcmpeqb Compare packed 8-bit integers in "a" and "b" for equality, and store the results in "dst"
  • _m_pcmpeqd Compare packed 32-bit integers in "a" and "b" for equality, and store the results in "dst"
  • _m_pcmpeqw Compare packed 16-bit integers in "a" and "b" for equality, and store the results in "dst"
  • _m_pcmpgtb Compare packed 8-bit integers in "a" and "b" for greater-than, and store the results in "dst"
  • _m_pcmpgtd Compare packed 32-bit integers in "a" and "b" for greater-than, and store the results in "dst"
  • _m_pcmpgtw Compare packed 16-bit integers in "a" and "b" for greater-than, and store the results in "dst"
  • _pconfig_u32 Invoke the PCONFIG leaf function specified by "a". The "__data" array contains 3 32-bit elements that may act as input, output, or be unused, depending on the semantics of the specified leaf function
  • _pdep_u32 Deposit contiguous low bits from unsigned 32-bit integer "a" to "dst" at the corresponding bit locations specified by "mask"
  • _pdep_u64 Deposit contiguous low bits from unsigned 64-bit integer "a" to "dst" at the corresponding bit locations specified by "mask"
  • _mm256_permute_pd Shuffle double-precision floating-point elements in "a" within 128-bit lanes using the control in "imm8"
  • _mm_permute_pd Shuffle double-precision floating-point elements in "a" using the control in "imm8"
  • _mm256_permute_ps Shuffle single-precision floating-point elements in "a" within 128-bit lanes using the control in "imm8"
  • _mm_permute_ps Shuffle single-precision floating-point elements in "a" using the control in "imm8"
  • _mm256_permute2f128_pd Shuffle 128-bits (composed of 2 packed double-precision floating-point elements) selected by "imm8" from "a" and "b"
  • _mm256_permute2f128_ps Shuffle 128-bits (composed of 4 packed single-precision floating-point elements) selected by "imm8" from "a" and "b"
  • _mm256_permute2f128_si256 Shuffle 128-bits (composed of integer data) selected by "imm8" from "a" and "b"
  • _mm256_permute2x128_si256 Shuffle 128-bits (composed of integer data) selected by "imm8" from "a" and "b"
  • _mm256_permute4x64_epi64 Shuffle 64-bit integers in "a" across lanes using the control in "imm8"
  • _mm256_permute4x64_pd Shuffle double-precision floating-point elements in "a" across lanes using the control in "imm8"
  • _mm256_permutevar_pd Shuffle double-precision floating-point elements in "a" within 128-bit lanes using the control in "b"
  • _mm_permutevar_pd Shuffle double-precision floating-point elements in "a" using the control in "b"
  • _mm256_permutevar_ps Shuffle single-precision floating-point elements in "a" within 128-bit lanes using the control in "b"
  • _mm_permutevar_ps Shuffle single-precision floating-point elements in "a" using the control in "b"
  • _mm256_permutevar8x32_epi32 Shuffle 32-bit integers in "a" across lanes using the corresponding index in "idx"
  • _mm256_permutevar8x32_ps Shuffle single-precision floating-point elements in "a" across lanes using the corresponding index in "idx"
  • _pext_u32 Extract bits from unsigned 32-bit integer "a" at the corresponding bit locations specified by "mask" to contiguous low bits in "dst"
  • _pext_u64 Extract bits from unsigned 64-bit integer "a" at the corresponding bit locations specified by "mask" to contiguous low bits in "dst"
  • _m_pextrw Extract a 16-bit integer from "a", selected with "imm8", and store the result in the lower element of "dst"
  • _m_pinsrw Copy "a" to "dst", and insert the 16-bit integer "i" into "dst" at the location specified by "imm8"
  • _m_pmaddwd Multiply packed 16-bit integers in "a" and "b", producing intermediate 32-bit integers
  • _m_pmaxsw Compare packed 16-bit integers in "a" and "b", and store packed maximum values in "dst"
  • _m_pmaxub Compare packed unsigned 8-bit integers in "a" and "b", and store packed maximum values in "dst"
  • _m_pminsw Compare packed 16-bit integers in "a" and "b", and store packed minimum values in "dst"
  • _m_pminub Compare packed unsigned 8-bit integers in "a" and "b", and store packed minimum values in "dst"
  • _m_pmovmskb Create mask from the most significant bit of each 8-bit element in "a"
  • _m_pmulhuw Multiply the packed unsigned 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst"
  • _m_pmulhw Multiply the packed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst"
  • _m_pmullw Multiply the packed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the low 16 bits of the intermediate integers in "dst"
  • _mm_popcnt_u32 Count the number of bits set to 1 in unsigned 32-bit integer "a"
  • _mm_popcnt_u64 Count the number of bits set to 1 in unsigned 64-bit integer "a"
  • _popcnt32 Count the number of bits set to 1 in 32-bit integer "a", and return that count in "dst"
  • _popcnt64 Count the number of bits set to 1 in 64-bit integer "a", and return that count in "dst"
  • _m_por Compute the bitwise OR of 64 bits (representing integer data) in "a" and "b"
  • _mm_pow_pd Compute the exponential value of packed double-precision floating-point elements in "a" raised by packed elements in "b"
  • _mm256_pow_pd Compute the exponential value of packed double-precision floating-point elements in "a" raised by packed elements in "b"
  • _mm_pow_ps Compute the exponential value of packed single-precision floating-point elements in "a" raised by packed elements in "b"
  • _mm256_pow_ps Compute the exponential value of packed single-precision floating-point elements in "a" raised by packed elements in "b"
  • _mm_prefetch SSE Fetch the line of data from memory that contains address "p" to a location in the cache heirarchy specified by the locality hint "i"
  • _mm_prefetch Other Fetch the line of data from memory that contains address "p" to a location in the cache heirarchy specified by the locality hint "i"
  • _m_psadbw Compute the absolute differences of packed unsigned 8-bit integers in "a" and "b", then horizontally sum each consecutive 8 differences to produce four unsigned 16-bit integers, and pack these unsigned 16-bit integers in the low 16 bits of "dst"
  • _m_pshufw Shuffle 16-bit integers in "a" using the control in "imm8", and store the results in "dst"
  • _m_pslld Shift packed 32-bit integers in "a" left by "count" while shifting in zeros
  • _m_pslldi Shift packed 32-bit integers in "a" left by "imm8" while shifting in zeros
  • _m_psllq Shift 64-bit integer "a" left by "count" while shifting in zeros, and store the result in "dst"
  • _m_psllqi Shift 64-bit integer "a" left by "imm8" while shifting in zeros, and store the result in "dst"
  • _m_psllw Shift packed 16-bit integers in "a" left by "count" while shifting in zeros
  • _m_psllwi Shift packed 16-bit integers in "a" left by "imm8" while shifting in zeros
  • _m_psrad Shift packed 32-bit integers in "a" right by "count" while shifting in sign bits
  • _m_psradi Shift packed 32-bit integers in "a" right by "imm8" while shifting in sign bits
  • _m_psraw Shift packed 16-bit integers in "a" right by "count" while shifting in sign bits
  • _m_psrawi Shift packed 16-bit integers in "a" right by "imm8" while shifting in sign bits
  • _m_psrld Shift packed 32-bit integers in "a" right by "count" while shifting in zeros
  • _m_psrldi Shift packed 32-bit integers in "a" right by "imm8" while shifting in zeros
  • _m_psrlq Shift 64-bit integer "a" right by "count" while shifting in zeros
  • _m_psrlqi Shift 64-bit integer "a" right by "imm8" while shifting in zeros, and store the result in "dst"
  • _m_psrlw Shift packed 16-bit integers in "a" right by "count" while shifting in zeros
  • _m_psrlwi Shift packed 16-bit integers in "a" right by "imm8" while shifting in zeros
  • _m_psubb Subtract packed 8-bit integers in "b" from packed 8-bit integers in "a"
  • _m_psubd Subtract packed 32-bit integers in "b" from packed 32-bit integers in "a"
  • _m_psubsb Subtract packed 8-bit integers in "b" from packed 8-bit integers in "a" using saturation
  • _m_psubsw Subtract packed 16-bit integers in "b" from packed 16-bit integers in "a" using saturation
  • _m_psubusb Subtract packed unsigned 8-bit integers in "b" from packed unsigned 8-bit integers in "a" using saturation
  • _m_psubusw Subtract packed unsigned 16-bit integers in "b" from packed unsigned 16-bit integers in "a" using saturation
  • _m_psubw Subtract packed 16-bit integers in "b" from packed 16-bit integers in "a"
  • _ptwrite32 Insert the 32-bit data from "a" into a Processor Trace stream via a PTW packet
  • _ptwrite64 Insert the 64-bit data from "a" into a Processor Trace stream via a PTW packet
  • _m_punpckhbw Unpack and interleave 8-bit integers from the high half of "a" and "b"
  • _m_punpckhdq Unpack and interleave 32-bit integers from the high half of "a" and "b"
  • _m_punpckhwd Unpack and interleave 16-bit integers from the high half of "a" and "b"
  • _m_punpcklbw Unpack and interleave 8-bit integers from the low half of "a" and "b"
  • _m_punpckldq Unpack and interleave 32-bit integers from the low half of "a" and "b"
  • _m_punpcklwd Unpack and interleave 16-bit integers from the low half of "a" and "b"
  • _m_pxor Compute the bitwise OR of 64 bits (representing integer data) in "a" and "b"

R

  • _mm_rcp_ps Compute the approximate reciprocal of packed single-precision floating-point elements in "a"
  • _mm256_rcp_ps Compute the approximate reciprocal of packed single-precision floating-point elements in "a"
  • _mm_rcp_ss Compute the approximate reciprocal of the lower single-precision floating-point element in "a"
  • _rdpid_u32 Copy the IA32_TSC_AUX MSR (signature value) into "dst".
  • _rdpmc Read the Performance Monitor Counter (PMC) specified by "a", and store up to 64-bits in "dst"
  • _rdrand16_step Read a hardware generated 16-bit random value and store the result in "val"
  • _rdrand32_step Read a hardware generated 32-bit random value and store the result in "val"
  • _rdrand64_step Read a hardware generated 64-bit random value and store the result in "val"
  • _rdseed16_step Read a 16-bit NIST SP800-90B and SP800-90C compliant random value and store in "val"
  • _rdseed32_step Read a 32-bit NIST SP800-90B and SP800-90C compliant random value and store in "val"
  • _rdseed64_step Read a 64-bit NIST SP800-90B and SP800-90C compliant random value and store in "val"
  • _rdsspd_i32 Read the low 32-bits of the current shadow stack pointer, and store the result in "dst"
  • _rdsspq_i64 Read the current shadow stack pointer, and store the result in "dst"
  • _rdtsc Copy the current 64-bit value of the processor's time-stamp counter into "dst"
  • __rdtscp Copy the current 64-bit value of the processor's time-stamp counter into "dst", and store the IA32_TSC_AUX MSR (signature value) into memory at "mem_addr"
  • _readfsbase_u32 Read the FS segment base register and store the 32-bit result in "dst"
  • _readfsbase_u64 Read the FS segment base register and store the 64-bit result in "dst"
  • _readgsbase_u32 Read the GS segment base register and store the 32-bit result in "dst"
  • _readgsbase_u64 Read the GS segment base register and store the 64-bit result in "dst"
  • _mm_rem_epi8 Divide packed 8-bit integers in "a" by packed elements in "b", and store the remainders as packed 32-bit integers in "dst"
  • _mm256_rem_epi8 Divide packed 8-bit integers in "a" by packed elements in "b", and store the remainders as packed 32-bit integers in "dst"
  • _mm_rem_epi16 Divide packed 16-bit integers in "a" by packed elements in "b", and store the remainders as packed 32-bit integers in "dst"
  • _mm256_rem_epi16 Divide packed 16-bit integers in "a" by packed elements in "b", and store the remainders as packed 32-bit integers in "dst"
  • _mm_rem_epi32 Divide packed 32-bit integers in "a" by packed elements in "b", and store the remainders as packed 32-bit integers in "dst"
  • _mm256_rem_epi32 Divide packed 32-bit integers in "a" by packed elements in "b", and store the remainders as packed 32-bit integers in "dst"
  • _mm_rem_epi64 Divide packed 64-bit integers in "a" by packed elements in "b", and store the remainders as packed 32-bit integers in "dst"
  • _mm256_rem_epi64 Divide packed 64-bit integers in "a" by packed elements in "b", and store the remainders as packed 32-bit integers in "dst"
  • _mm_rem_epu8 Divide packed unsigned 8-bit integers in "a" by packed elements in "b", and store the remainders as packed unsigned 32-bit integers in "dst"
  • _mm256_rem_epu8 Divide packed unsigned 8-bit integers in "a" by packed elements in "b", and store the remainders as packed unsigned 32-bit integers in "dst"
  • _mm_rem_epu16 Divide packed unsigned 16-bit integers in "a" by packed elements in "b", and store the remainders as packed unsigned 32-bit integers in "dst"
  • _mm256_rem_epu16 Divide packed unsigned 16-bit integers in "a" by packed elements in "b", and store the remainders as packed unsigned 32-bit integers in "dst"
  • _mm_rem_epu32 Divide packed unsigned 32-bit integers in "a" by packed elements in "b", and store the remainders as packed unsigned 32-bit integers in "dst"
  • _mm256_rem_epu32 Divide packed unsigned 32-bit integers in "a" by packed elements in "b", and store the remainders as packed unsigned 32-bit integers in "dst"
  • _mm_rem_epu64 Divide packed unsigned 64-bit integers in "a" by packed elements in "b", and store the remainders as packed unsigned 32-bit integers in "dst"
  • _mm256_rem_epu64 Divide packed unsigned 64-bit integers in "a" by packed elements in "b", and store the remainders as packed unsigned 32-bit integers in "dst"
  • _rotl Shift the bits of unsigned 32-bit integer "a" left by the number of bits specified in "shift"
  • _rotl64 Shift the bits of unsigned 64-bit integer "a" left by the number of bits specified in "shift"
  • _rotr Shift the bits of unsigned 32-bit integer "a" right by the number of bits specified in "shift"
  • _rotr64 Shift the bits of unsigned 64-bit integer "a" right by the number of bits specified in "shift"
  • _rotwl Shift the bits of unsigned 16-bit integer "a" left by the number of bits specified in "shift"
  • _rotwr Shift the bits of unsigned 16-bit integer "a" right by the number of bits specified in "shift"
  • _mm_round_pd Round the packed double-precision floating-point elements in "a" using the "rounding" parameter
  • _mm256_round_pd Round the packed double-precision floating-point elements in "a" using the "rounding" parameter
  • _mm_round_ps Round the packed single-precision floating-point elements in "a" using the "rounding" parameter
  • _mm256_round_ps Round the packed single-precision floating-point elements in "a" using the "rounding" parameter
  • _mm_round_sd Round the lower double-precision floating-point element in "b" using the "rounding" parameter
  • _mm_round_ss Round the lower single-precision floating-point element in "b" using the "rounding" parameter
  • _mm_rsqrt_ps Compute the approximate reciprocal square root of packed single-precision floating-point elements in "a"
  • _mm256_rsqrt_ps Compute the approximate reciprocal square root of packed single-precision floating-point elements in "a"
  • _mm_rsqrt_ss Compute the approximate reciprocal square root of the lower single-precision floating-point element in "a"
  • _rstorssp Restore the saved shadow stack pointer from the shadow stack restore token previously created on shadow stack by saveprevssp

S

  • _mm_sad_epu8 Compute the absolute differences of packed unsigned 8-bit integers in "a" and "b", then horizontally sum each consecutive 8 differences to produce two unsigned 16-bit integers, and pack these unsigned 16-bit integers in the low 16 bits of 64-bit elements in "dst"
  • _mm256_sad_epu8 Compute the absolute differences of packed unsigned 8-bit integers in "a" and "b", then horizontally sum each consecutive 8 differences to produce four unsigned 16-bit integers, and pack these unsigned 16-bit integers in the low 16 bits of 64-bit elements in "dst"
  • _mm_sad_pu8 Compute the absolute differences of packed unsigned 8-bit integers in "a" and "b", then horizontally sum each consecutive 8 differences to produce four unsigned 16-bit integers, and pack these unsigned 16-bit integers in the low 16 bits of "dst"
  • _saveprevssp Save the previous shadow stack pointer context.
  • _mm_set_epi8 Set packed 8-bit integers in "dst" with the supplied values in reverse order
  • _mm256_set_epi8 Set packed 8-bit integers in "dst" with the supplied values in reverse order
  • _mm_set_epi16 Set packed 16-bit integers in "dst" with the supplied values.
  • _mm256_set_epi16 Set packed 16-bit integers in "dst" with the supplied values.
  • _mm_set_epi32 Set packed 32-bit integers in "dst" with the supplied values.
  • _mm256_set_epi32 Set packed 32-bit integers in "dst" with the supplied values.
  • _mm_set_epi64 Set packed 64-bit integers in "dst" with the supplied values.
  • _mm_set_epi64x Set packed 64-bit integers in "dst" with the supplied values.
  • _mm256_set_epi64x Set packed 64-bit integers in "dst" with the supplied values.
  • _MM_SET_EXCEPTION_MASK Macro: Set the exception mask bits of the MXCSR control and status register to the value in unsigned 32-bit integer "a"
  • _MM_SET_EXCEPTION_STATE Macro: Set the exception state bits of the MXCSR control and status register to the value in unsigned 32-bit integer "a"
  • _MM_SET_FLUSH_ZERO_MODE Macro: Set the flush zero bits of the MXCSR control and status register to the value in unsigned 32-bit integer "a"
  • _mm256_set_m128 Set packed __m256 vector "dst" with the supplied values.
  • _mm256_set_m128d Set packed __m256d vector "dst" with the supplied values.
  • _mm256_set_m128i Set packed __m256i vector "dst" with the supplied values.
  • _mm_set_pd Set packed double-precision floating-point elements in "dst" with the supplied values
  • _mm256_set_pd Set packed double-precision floating-point elements in "dst" with the supplied values
  • _mm_set_pd1 Broadcast double-precision floating-point value "a" to all elements of "dst"
  • _mm_set_pi8 Set packed 8-bit integers in "dst" with the supplied values in reverse order
  • _mm_set_pi16 Set packed 16-bit integers in "dst" with the supplied values.
  • _mm_set_pi32 Set packed 32-bit integers in "dst" with the supplied values.
  • _mm_set_ps Set packed single-precision floating-point elements in "dst" with the supplied values
  • _mm256_set_ps Set packed single-precision floating-point elements in "dst" with the supplied values
  • _mm_set_ps1 Broadcast single-precision floating-point value "a" to all elements of "dst"
  • _MM_SET_ROUNDING_MODE Macro: Set the rounding mode bits of the MXCSR control and status register to the value in unsigned 32-bit integer "a"
  • _mm_set_sd Copy double-precision floating-point element "a" to the lower element of "dst", and zero the upper element
  • _mm_set_ss Copy single-precision floating-point element "a" to the lower element of "dst", and zero the upper 3 elements
  • _mm_set1_epi8 Broadcast 8-bit integer "a" to all elements of "dst". This intrinsic may generate "vpbroadcastb".
  • _mm256_set1_epi8 Broadcast 8-bit integer "a" to all elements of "dst". This intrinsic may generate the "vpbroadcastb".
  • _mm_set1_epi16 Broadcast 16-bit integer "a" to all all elements of "dst". This intrinsic may generate "vpbroadcastw".
  • _mm256_set1_epi16 Broadcast 16-bit integer "a" to all all elements of "dst". This intrinsic may generate the "vpbroadcastw".
  • _mm_set1_epi32 Broadcast 32-bit integer "a" to all elements of "dst". This intrinsic may generate "vpbroadcastd".
  • _mm256_set1_epi32 Broadcast 32-bit integer "a" to all elements of "dst". This intrinsic may generate the "vpbroadcastd".
  • _mm_set1_epi64 Broadcast 64-bit integer "a" to all elements of "dst".
  • _mm_set1_epi64x Broadcast 64-bit integer "a" to all elements of "dst". This intrinsic may generate the "vpbroadcastq".
  • _mm256_set1_epi64x Broadcast 64-bit integer "a" to all elements of "dst". This intrinsic may generate the "vpbroadcastq".
  • _mm_set1_pd Broadcast double-precision floating-point value "a" to all elements of "dst"
  • _mm256_set1_pd Broadcast double-precision floating-point value "a" to all elements of "dst"
  • _mm_set1_pi8 Broadcast 8-bit integer "a" to all elements of "dst".
  • _mm_set1_pi16 Broadcast 16-bit integer "a" to all all elements of "dst".
  • _mm_set1_pi32 Broadcast 32-bit integer "a" to all elements of "dst".
  • _mm_set1_ps Broadcast single-precision floating-point value "a" to all elements of "dst"
  • _mm256_set1_ps Broadcast single-precision floating-point value "a" to all elements of "dst"
  • _mm_setcsr Set the MXCSR control and status register with the value in unsigned 32-bit integer "a"
  • _mm_setr_epi8 Set packed 8-bit integers in "dst" with the supplied values in reverse order
  • _mm256_setr_epi8 Set packed 8-bit integers in "dst" with the supplied values in reverse order
  • _mm_setr_epi16 Set packed 16-bit integers in "dst" with the supplied values in reverse order
  • _mm256_setr_epi16 Set packed 16-bit integers in "dst" with the supplied values in reverse order
  • _mm_setr_epi32 Set packed 32-bit integers in "dst" with the supplied values in reverse order
  • _mm256_setr_epi32 Set packed 32-bit integers in "dst" with the supplied values in reverse order
  • _mm_setr_epi64 Set packed 64-bit integers in "dst" with the supplied values in reverse order
  • _mm256_setr_epi64x Set packed 64-bit integers in "dst" with the supplied values in reverse order
  • _mm256_setr_m128 Set packed __m256 vector "dst" with the supplied values.
  • _mm256_setr_m128d Set packed __m256d vector "dst" with the supplied values.
  • _mm256_setr_m128i Set packed __m256i vector "dst" with the supplied values.
  • _mm_setr_pd Set packed double-precision floating-point elements in "dst" with the supplied values in reverse order
  • _mm256_setr_pd Set packed double-precision floating-point elements in "dst" with the supplied values in reverse order
  • _mm_setr_pi8 Set packed 8-bit integers in "dst" with the supplied values in reverse order
  • _mm_setr_pi16 Set packed 16-bit integers in "dst" with the supplied values in reverse order
  • _mm_setr_pi32 Set packed 32-bit integers in "dst" with the supplied values in reverse order
  • _mm_setr_ps Set packed single-precision floating-point elements in "dst" with the supplied values in reverse order
  • _mm256_setr_ps Set packed single-precision floating-point elements in "dst" with the supplied values in reverse order
  • _setssbsy Mark shadow stack pointed to by IA32_PL0_SSP as busy.
  • _mm_setzero_pd Return vector of type __m128d with all elements set to zero.
  • _mm256_setzero_pd Return vector of type __m256d with all elements set to zero.
  • _mm_setzero_ps Return vector of type __m128 with all elements set to zero.
  • _mm256_setzero_ps Return vector of type __m256 with all elements set to zero.
  • _mm_setzero_si64 Return vector of type __m64 with all elements set to zero.
  • _mm_setzero_si128 Return vector of type __m128i with all elements set to zero.
  • _mm256_setzero_si256 Return vector of type __m256i with all elements set to zero.
  • _mm_sfence Perform a serializing operation on all store-to-memory instructions that were issued prior to this instruction
  • _mm_sha1msg1_epu32 Perform an intermediate calculation for the next four SHA1 message values (unsigned 32-bit integers) using previous message values from "a" and "b"
  • _mm_sha1msg2_epu32 Perform the final calculation for the next four SHA1 message values (unsigned 32-bit integers) using the intermediate result in "a" and the previous message values in "b"
  • _mm_sha1nexte_epu32 Calculate SHA1 state variable E after four rounds of operation from the current SHA1 state variable "a", add that value to the scheduled values (unsigned 32-bit integers) in "b"
  • _mm_sha1rnds4_epu32 Perform four rounds of SHA1 operation using an initial SHA1 state (A,B,C,D) from "a" and some pre-computed sum of the next 4 round message values (unsigned 32-bit integers), and state variable E from "b", and store the updated SHA1 state (A,B,C,D) in "dst"
  • _mm_sha256msg1_epu32 Perform an intermediate calculation for the next four SHA256 message values (unsigned 32-bit integers) using previous message values from "a" and "b"
  • _mm_sha256msg2_epu32 Perform the final calculation for the next four SHA256 message values (unsigned 32-bit integers) using previous message values from "a" and "b"
  • _mm_sha256rnds2_epu32 Perform 2 rounds of SHA256 operation using an initial SHA256 state (C,D,G,H) from "a", an initial SHA256 state (A,B,E,F) from "b", and a pre-computed sum of the next 2 round message values (unsigned 32-bit integers) and the corresponding round constants from "k", and store the updated SHA256 state (A,B,E,F) in "dst"
  • _mm_shuffle_epi8 Shuffle packed 8-bit integers in "a" according to shuffle control mask in the corresponding 8-bit element of "b"
  • _mm256_shuffle_epi8 Shuffle 8-bit integers in "a" within 128-bit lanes according to shuffle control mask in the corresponding 8-bit element of "b"
  • _mm_shuffle_epi32 Shuffle 32-bit integers in "a" using the control in "imm8", and store the results in "dst"
  • _mm256_shuffle_epi32 Shuffle 32-bit integers in "a" within 128-bit lanes using the control in "imm8"
  • _mm_shuffle_pd Shuffle double-precision floating-point elements using the control in "imm8"
  • _mm256_shuffle_pd Shuffle double-precision floating-point elements within 128-bit lanes using the control in "imm8"
  • _mm_shuffle_pi8 Shuffle packed 8-bit integers in "a" according to shuffle control mask in the corresponding 8-bit element of "b"
  • _mm_shuffle_pi16 Shuffle 16-bit integers in "a" using the control in "imm8", and store the results in "dst"
  • _mm_shuffle_ps Shuffle single-precision floating-point elements in "a" using the control in "imm8"
  • _mm256_shuffle_ps Shuffle single-precision floating-point elements in "a" within 128-bit lanes using the control in "imm8"
  • _mm_shufflehi_epi16 Shuffle 16-bit integers in the high 64 bits of "a" using the control in "imm8"
  • _mm256_shufflehi_epi16 Shuffle 16-bit integers in the high 64 bits of 128-bit lanes of "a" using the control in "imm8"
  • _mm_shufflelo_epi16 Shuffle 16-bit integers in the low 64 bits of "a" using the control in "imm8"
  • _mm256_shufflelo_epi16 Shuffle 16-bit integers in the low 64 bits of 128-bit lanes of "a" using the control in "imm8"
  • _mm_sign_epi8 Negate packed 8-bit integers in "a" when the corresponding signed 8-bit integer in "b" is negative
  • _mm256_sign_epi8 Negate packed 8-bit integers in "a" when the corresponding signed 8-bit integer in "b" is negative
  • _mm_sign_epi16 Negate packed 16-bit integers in "a" when the corresponding signed 16-bit integer in "b" is negative
  • _mm256_sign_epi16 Negate packed 16-bit integers in "a" when the corresponding signed 16-bit integer in "b" is negative
  • _mm_sign_epi32 Negate packed 32-bit integers in "a" when the corresponding signed 32-bit integer in "b" is negative
  • _mm256_sign_epi32 Negate packed 32-bit integers in "a" when the corresponding signed 32-bit integer in "b" is negative
  • _mm_sign_pi8 Negate packed 8-bit integers in "a" when the corresponding signed 8-bit integer in "b" is negative
  • _mm_sign_pi16 Negate packed 16-bit integers in "a" when the corresponding signed 16-bit integer in "b" is negative
  • _mm_sign_pi32 Negate packed 32-bit integers in "a" when the corresponding signed 32-bit integer in "b" is negative
  • _mm_sin_pd Compute the sine of packed double-precision floating-point elements in "a" expressed in radians
  • _mm256_sin_pd Compute the sine of packed double-precision floating-point elements in "a" expressed in radians
  • _mm_sin_ps Compute the sine of packed single-precision floating-point elements in "a" expressed in radians
  • _mm256_sin_ps Compute the sine of packed single-precision floating-point elements in "a" expressed in radians
  • _mm_sincos_pd Compute the sine and cosine of packed double-precision floating-point elements in "a" expressed in radians, store the sine in "dst", and store the cosine into memory at "mem_addr"
  • _mm256_sincos_pd Compute the sine and cosine of packed double-precision floating-point elements in "a" expressed in radians, store the sine in "dst", and store the cosine into memory at "mem_addr"
  • _mm_sincos_ps Compute the sine and cosine of packed single-precision floating-point elements in "a" expressed in radians, store the sine in "dst", and store the cosine into memory at "mem_addr"
  • _mm256_sincos_ps Compute the sine and cosine of packed single-precision floating-point elements in "a" expressed in radians, store the sine in "dst", and store the cosine into memory at "mem_addr"
  • _mm_sind_pd Compute the sine of packed double-precision floating-point elements in "a" expressed in degrees
  • _mm256_sind_pd Compute the sine of packed double-precision floating-point elements in "a" expressed in degrees
  • _mm_sind_ps Compute the sine of packed single-precision floating-point elements in "a" expressed in degrees
  • _mm256_sind_ps Compute the sine of packed single-precision floating-point elements in "a" expressed in degrees
  • _mm_sinh_pd Compute the hyperbolic sine of packed double-precision floating-point elements in "a" expressed in radians
  • _mm256_sinh_pd Compute the hyperbolic sine of packed double-precision floating-point elements in "a" expressed in radians
  • _mm_sinh_ps Compute the hyperbolic sine of packed single-precision floating-point elements in "a" expressed in radians
  • _mm256_sinh_ps Compute the hyperbolic sine of packed single-precision floating-point elements in "a" expressed in radians
  • _mm_sll_epi16 Shift packed 16-bit integers in "a" left by "count" while shifting in zeros
  • _mm256_sll_epi16 Shift packed 16-bit integers in "a" left by "count" while shifting in zeros
  • _mm_sll_epi32 Shift packed 32-bit integers in "a" left by "count" while shifting in zeros
  • _mm256_sll_epi32 Shift packed 32-bit integers in "a" left by "count" while shifting in zeros
  • _mm_sll_epi64 Shift packed 64-bit integers in "a" left by "count" while shifting in zeros
  • _mm256_sll_epi64 Shift packed 64-bit integers in "a" left by "count" while shifting in zeros
  • _mm_sll_pi16 Shift packed 16-bit integers in "a" left by "count" while shifting in zeros
  • _mm_sll_pi32 Shift packed 32-bit integers in "a" left by "count" while shifting in zeros
  • _mm_sll_si64 Shift 64-bit integer "a" left by "count" while shifting in zeros, and store the result in "dst"
  • _mm_slli_epi16 Shift packed 16-bit integers in "a" left by "imm8" while shifting in zeros
  • _mm256_slli_epi16 Shift packed 16-bit integers in "a" left by "imm8" while shifting in zeros
  • _mm_slli_epi32 Shift packed 32-bit integers in "a" left by "imm8" while shifting in zeros
  • _mm256_slli_epi32 Shift packed 32-bit integers in "a" left by "imm8" while shifting in zeros
  • _mm_slli_epi64 Shift packed 64-bit integers in "a" left by "imm8" while shifting in zeros
  • _mm256_slli_epi64 Shift packed 64-bit integers in "a" left by "imm8" while shifting in zeros
  • _mm_slli_pi16 Shift packed 16-bit integers in "a" left by "imm8" while shifting in zeros
  • _mm_slli_pi32 Shift packed 32-bit integers in "a" left by "imm8" while shifting in zeros
  • _mm_slli_si64 Shift 64-bit integer "a" left by "imm8" while shifting in zeros, and store the result in "dst"
  • _mm_slli_si128 Shift "a" left by "imm8" bytes while shifting in zeros, and store the results in "dst"
  • _mm256_slli_si256 Shift 128-bit lanes in "a" left by "imm8" bytes while shifting in zeros
  • _mm_sllv_epi32 Shift packed 32-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros
  • _mm256_sllv_epi32 Shift packed 32-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros
  • _mm_sllv_epi64 Shift packed 64-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros
  • _mm256_sllv_epi64 Shift packed 64-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros
  • _mm_sqrt_pd Compute the square root of packed double-precision floating-point elements in "a"
  • _mm256_sqrt_pd Compute the square root of packed double-precision floating-point elements in "a"
  • _mm_sqrt_ps Compute the square root of packed single-precision floating-point elements in "a"
  • _mm256_sqrt_ps Compute the square root of packed single-precision floating-point elements in "a"
  • _mm_sqrt_sd Compute the square root of the lower double-precision floating-point element in "b"
  • _mm_sqrt_ss Compute the square root of the lower single-precision floating-point element in "a"
  • _mm_sra_epi16 Shift packed 16-bit integers in "a" right by "count" while shifting in sign bits
  • _mm256_sra_epi16 Shift packed 16-bit integers in "a" right by "count" while shifting in sign bits
  • _mm_sra_epi32 Shift packed 32-bit integers in "a" right by "count" while shifting in sign bits
  • _mm256_sra_epi32 Shift packed 32-bit integers in "a" right by "count" while shifting in sign bits
  • _mm_sra_pi16 Shift packed 16-bit integers in "a" right by "count" while shifting in sign bits
  • _mm_sra_pi32 Shift packed 32-bit integers in "a" right by "count" while shifting in sign bits
  • _mm_srai_epi16 Shift packed 16-bit integers in "a" right by "imm8" while shifting in sign bits
  • _mm256_srai_epi16 Shift packed 16-bit integers in "a" right by "imm8" while shifting in sign bits
  • _mm_srai_epi32 Shift packed 32-bit integers in "a" right by "imm8" while shifting in sign bits
  • _mm256_srai_epi32 Shift packed 32-bit integers in "a" right by "imm8" while shifting in sign bits
  • _mm_srai_pi16 Shift packed 16-bit integers in "a" right by "imm8" while shifting in sign bits
  • _mm_srai_pi32 Shift packed 32-bit integers in "a" right by "imm8" while shifting in sign bits
  • _mm_srav_epi32 Shift packed 32-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits
  • _mm256_srav_epi32 Shift packed 32-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits
  • _mm_srl_epi16 Shift packed 16-bit integers in "a" right by "count" while shifting in zeros
  • _mm256_srl_epi16 Shift packed 16-bit integers in "a" right by "count" while shifting in zeros
  • _mm_srl_epi32 Shift packed 32-bit integers in "a" right by "count" while shifting in zeros
  • _mm256_srl_epi32 Shift packed 32-bit integers in "a" right by "count" while shifting in zeros
  • _mm_srl_epi64 Shift packed 64-bit integers in "a" right by "count" while shifting in zeros
  • _mm256_srl_epi64 Shift packed 64-bit integers in "a" right by "count" while shifting in zeros
  • _mm_srl_pi16 Shift packed 16-bit integers in "a" right by "count" while shifting in zeros
  • _mm_srl_pi32 Shift packed 32-bit integers in "a" right by "count" while shifting in zeros
  • _mm_srl_si64 Shift 64-bit integer "a" right by "count" while shifting in zeros
  • _mm_srli_epi16 Shift packed 16-bit integers in "a" right by "imm8" while shifting in zeros
  • _mm256_srli_epi16 Shift packed 16-bit integers in "a" right by "imm8" while shifting in zeros
  • _mm_srli_epi32 Shift packed 32-bit integers in "a" right by "imm8" while shifting in zeros
  • _mm256_srli_epi32 Shift packed 32-bit integers in "a" right by "imm8" while shifting in zeros
  • _mm_srli_epi64 Shift packed 64-bit integers in "a" right by "imm8" while shifting in zeros
  • _mm256_srli_epi64 Shift packed 64-bit integers in "a" right by "imm8" while shifting in zeros
  • _mm_srli_pi16 Shift packed 16-bit integers in "a" right by "imm8" while shifting in zeros
  • _mm_srli_pi32 Shift packed 32-bit integers in "a" right by "imm8" while shifting in zeros
  • _mm_srli_si64 Shift 64-bit integer "a" right by "imm8" while shifting in zeros, and store the result in "dst"
  • _mm_srli_si128 Shift "a" right by "imm8" bytes while shifting in zeros, and store the results in "dst"
  • _mm256_srli_si256 Shift 128-bit lanes in "a" right by "imm8" bytes while shifting in zeros
  • _mm_srlv_epi32 Shift packed 32-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros
  • _mm256_srlv_epi32 Shift packed 32-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros
  • _mm_srlv_epi64 Shift packed 64-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros
  • _mm256_srlv_epi64 Shift packed 64-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros
  • _mm_store_pd Store 128-bits (composed of 2 packed double-precision floating-point elements) from "a" into memory
  • _mm256_store_pd Store 256-bits (composed of 4 packed double-precision floating-point elements) from "a" into memory
  • _mm_store_pd1 Store the lower double-precision floating-point element from "a" into 2 contiguous elements in memory
  • _mm_store_ps Store 128-bits (composed of 4 packed single-precision floating-point elements) from "a" into memory
  • _mm256_store_ps Store 256-bits (composed of 8 packed single-precision floating-point elements) from "a" into memory
  • _mm_store_ps1 Store the lower single-precision floating-point element from "a" into 4 contiguous elements in memory
  • _mm_store_sd Store the lower double-precision floating-point element from "a" into memory
  • _mm_store_si128 Store 128-bits of integer data from "a" into memory. "mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.
  • _mm256_store_si256 Store 256-bits of integer data from "a" into memory. "mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.
  • _mm_store_ss Store the lower single-precision floating-point element from "a" into memory
  • _mm_store1_pd Store the lower double-precision floating-point element from "a" into 2 contiguous elements in memory
  • _mm_store1_ps Store the lower single-precision floating-point element from "a" into 4 contiguous elements in memory
  • _storebe_i16 Perform a bit swap operation of the 16 bits in "data", and store the results to memory
  • _storebe_i32 Perform a bit swap operation of the 32 bits in "data", and store the results to memory
  • _storebe_i64 Perform a bit swap operation of the 64 bits in "data", and store the results to memory
  • _mm_storeh_pd Store the upper double-precision floating-point element from "a" into memory
  • _mm_storeh_pi Store the upper 2 single-precision floating-point elements from "a" into memory
  • _mm_storel_epi64 Store 64-bit integer from the first element of "a" into memory.
  • _mm_storel_pd Store the lower double-precision floating-point element from "a" into memory
  • _mm_storel_pi Store the lower 2 single-precision floating-point elements from "a" into memory
  • _mm_storer_pd Store 2 double-precision floating-point elements from "a" into memory in reverse order
  • _mm_storer_ps Store 4 single-precision floating-point elements from "a" into memory in reverse order
  • _mm_storeu_pd Store 128-bits (composed of 2 packed double-precision floating-point elements) from "a" into memory
  • _mm256_storeu_pd Store 256-bits (composed of 4 packed double-precision floating-point elements) from "a" into memory
  • _mm_storeu_ps Store 128-bits (composed of 4 packed single-precision floating-point elements) from "a" into memory
  • _mm256_storeu_ps Store 256-bits (composed of 8 packed single-precision floating-point elements) from "a" into memory
  • _mm_storeu_si16 Store 16-bit integer from the first element of "a" into memory. "mem_addr" does not need to be aligned on any particular boundary.
  • _mm_storeu_si32 Store 32-bit integer from the first element of "a" into memory. "mem_addr" does not need to be aligned on any particular boundary.
  • _mm_storeu_si64 Store 64-bit integer from the first element of "a" into memory. "mem_addr" does not need to be aligned on any particular boundary.
  • _mm_storeu_si128 Store 128-bits of integer data from "a" into memory. "mem_addr" does not need to be aligned on any particular boundary.
  • _mm256_storeu_si256 Store 256-bits of integer data from "a" into memory. "mem_addr" does not need to be aligned on any particular boundary.
  • _mm256_storeu2_m128 Store the high and low 128-bit halves (each composed of 4 packed single-precision floating-point elements) from "a" into memory two different 128-bit locations
  • _mm256_storeu2_m128d Store the high and low 128-bit halves (each composed of 2 packed double-precision floating-point elements) from "a" into memory two different 128-bit locations
  • _mm256_storeu2_m128i Store the high and low 128-bit halves (each composed of integer data) from "a" into memory two different 128-bit locations
  • _mm_stream_load_si128 Load 128-bits of integer data from memory into "dst" using a non-temporal memory hint
  • _mm256_stream_load_si256 Load 256-bits of integer data from memory into "dst" using a non-temporal memory hint
  • _mm_stream_pd Store 128-bits (composed of 2 packed double-precision floating-point elements) from "a" into memory using a non-temporal memory hint
  • _mm256_stream_pd Store 256-bits (composed of 4 packed double-precision floating-point elements) from "a" into memory using a non-temporal memory hint
  • _mm_stream_pi Store 64-bits of integer data from "a" into memory using a non-temporal memory hint
  • _mm_stream_ps Store 128-bits (composed of 4 packed single-precision floating-point elements) from "a" into memory using a non-temporal memory hint
  • _mm256_stream_ps Store 256-bits (composed of 8 packed single-precision floating-point elements) from "a" into memory using a non-temporal memory hint
  • _mm_stream_si32 Store 32-bit integer "a" into memory using a non-temporal hint to minimize cache pollution
  • _mm_stream_si64 Store 64-bit integer "a" into memory using a non-temporal hint to minimize cache pollution
  • _mm_stream_si128 Store 128-bits of integer data from "a" into memory using a non-temporal memory hint
  • _mm256_stream_si256 Store 256-bits of integer data from "a" into memory using a non-temporal memory hint
  • _mm_sub_epi8 Subtract packed 8-bit integers in "b" from packed 8-bit integers in "a"
  • _mm256_sub_epi8 Subtract packed 8-bit integers in "b" from packed 8-bit integers in "a"
  • _mm_sub_epi16 Subtract packed 16-bit integers in "b" from packed 16-bit integers in "a"
  • _mm256_sub_epi16 Subtract packed 16-bit integers in "b" from packed 16-bit integers in "a"
  • _mm_sub_epi32 Subtract packed 32-bit integers in "b" from packed 32-bit integers in "a"
  • _mm256_sub_epi32 Subtract packed 32-bit integers in "b" from packed 32-bit integers in "a"
  • _mm_sub_epi64 Subtract packed 64-bit integers in "b" from packed 64-bit integers in "a"
  • _mm256_sub_epi64 Subtract packed 64-bit integers in "b" from packed 64-bit integers in "a"
  • _mm_sub_pd Subtract packed double-precision floating-point elements in "b" from packed double-precision floating-point elements in "a"
  • _mm256_sub_pd Subtract packed double-precision floating-point elements in "b" from packed double-precision floating-point elements in "a"
  • _mm_sub_pi8 Subtract packed 8-bit integers in "b" from packed 8-bit integers in "a"
  • _mm_sub_pi16 Subtract packed 16-bit integers in "b" from packed 16-bit integers in "a"
  • _mm_sub_pi32 Subtract packed 32-bit integers in "b" from packed 32-bit integers in "a"
  • _mm_sub_ps Subtract packed single-precision floating-point elements in "b" from packed single-precision floating-point elements in "a"
  • _mm256_sub_ps Subtract packed single-precision floating-point elements in "b" from packed single-precision floating-point elements in "a"
  • _mm_sub_sd Subtract the lower double-precision floating-point element in "b" from the lower double-precision floating-point element in "a"
  • _mm_sub_si64 Subtract 64-bit integer "b" from 64-bit integer "a", and store the result in "dst"
  • _mm_sub_ss Subtract the lower single-precision floating-point element in "b" from the lower single-precision floating-point element in "a"
  • _subborrow_u32 Add unsigned 8-bit borrow "b_in" (carry flag) to unsigned 32-bit integer "b", and subtract the result from unsigned 32-bit integer "a"
  • _subborrow_u64 Add unsigned 8-bit borrow "b_in" (carry flag) to unsigned 64-bit integer "b", and subtract the result from unsigned 64-bit integer "a"
  • _mm_subs_epi8 Subtract packed 8-bit integers in "b" from packed 8-bit integers in "a" using saturation
  • _mm256_subs_epi8 Subtract packed 8-bit integers in "b" from packed 8-bit integers in "a" using saturation
  • _mm_subs_epi16 Subtract packed 16-bit integers in "b" from packed 16-bit integers in "a" using saturation
  • _mm256_subs_epi16 Subtract packed 16-bit integers in "b" from packed 16-bit integers in "a" using saturation
  • _mm_subs_epu8 Subtract packed unsigned 8-bit integers in "b" from packed unsigned 8-bit integers in "a" using saturation
  • _mm256_subs_epu8 Subtract packed unsigned 8-bit integers in "b" from packed unsigned 8-bit integers in "a" using saturation
  • _mm_subs_epu16 Subtract packed unsigned 16-bit integers in "b" from packed unsigned 16-bit integers in "a" using saturation
  • _mm256_subs_epu16 Subtract packed unsigned 16-bit integers in "b" from packed unsigned 16-bit integers in "a" using saturation
  • _mm_subs_pi8 Subtract packed 8-bit integers in "b" from packed 8-bit integers in "a" using saturation
  • _mm_subs_pi16 Subtract packed 16-bit integers in "b" from packed 16-bit integers in "a" using saturation
  • _mm_subs_pu8 Subtract packed unsigned 8-bit integers in "b" from packed unsigned 8-bit integers in "a" using saturation
  • _mm_subs_pu16 Subtract packed unsigned 16-bit integers in "b" from packed unsigned 16-bit integers in "a" using saturation
  • _mm_svml_ceil_pd Round the packed double-precision floating-point elements in "a" up to an integer value
  • _mm256_svml_ceil_pd Round the packed double-precision floating-point elements in "a" up to an integer value
  • _mm_svml_ceil_ps Round the packed single-precision floating-point elements in "a" up to an integer value
  • _mm256_svml_ceil_ps Round the packed single-precision floating-point elements in "a" up to an integer value
  • _mm_svml_floor_pd Round the packed double-precision floating-point elements in "a" down to an integer value
  • _mm256_svml_floor_pd Round the packed double-precision floating-point elements in "a" down to an integer value
  • _mm_svml_floor_ps Round the packed single-precision floating-point elements in "a" down to an integer value
  • _mm256_svml_floor_ps Round the packed single-precision floating-point elements in "a" down to an integer value
  • _mm_svml_round_pd Round the packed double-precision floating-point elements in "a" to the nearest integer value
  • _mm256_svml_round_pd Round the packed double-precision floating-point elements in "a" to the nearest integer value
  • _mm_svml_round_ps Round the packed single-precision floating-point elements in "a" to the nearest integer value
  • _mm256_svml_round_ps Round the packed single-precision floating-point elements in "a" to the nearest integer value
  • _mm_svml_sqrt_pd Compute the square root of packed double-precision floating-point elements in "a"
  • _mm256_svml_sqrt_pd Compute the square root of packed double-precision floating-point elements in "a"
  • _mm_svml_sqrt_ps Compute the square root of packed single-precision floating-point elements in "a"
  • _mm256_svml_sqrt_ps Compute the square root of packed single-precision floating-point elements in "a"

T

  • _mm_tan_pd Compute the tangent of packed double-precision floating-point elements in "a" expressed in radians
  • _mm256_tan_pd Compute the tangent of packed double-precision floating-point elements in "a" expressed in radians
  • _mm_tan_ps Compute the tangent of packed single-precision floating-point elements in "a" expressed in radians
  • _mm256_tan_ps Compute the tangent of packed single-precision floating-point elements in "a" expressed in radians
  • _mm_tand_pd Compute the tangent of packed double-precision floating-point elements in "a" expressed in degrees
  • _mm256_tand_pd Compute the tangent of packed double-precision floating-point elements in "a" expressed in degrees
  • _mm_tand_ps Compute the tangent of packed single-precision floating-point elements in "a" expressed in degrees
  • _mm256_tand_ps Compute the tangent of packed single-precision floating-point elements in "a" expressed in degrees
  • _mm_tanh_pd Compute the hyperbolic tangent of packed double-precision floating-point elements in "a" expressed in radians
  • _mm256_tanh_pd Compute the hyperbolic tangent of packed double-precision floating-point elements in "a" expressed in radians
  • _mm_tanh_ps Compute the hyperbolic tangent of packed single-precision floating-point elements in "a" expressed in radians
  • _mm256_tanh_ps Compute the hyperbolic tangent of packed single-precision floating-point elements in "a" expressed in radians
  • _mm_test_all_ones Compute the bitwise NOT of "a" and then AND with a 128-bit vector containing all 1's
  • _mm_test_all_zeros Compute the bitwise AND of 128 bits (representing integer data) in "a" and "mask"
  • _mm_test_mix_ones_zeros Compute the bitwise AND of 128 bits (representing integer data) in "a" and "mask", and set "ZF" to 1 if the result is zero, otherwise set "ZF" to 0
  • _mm256_testc_pd Compute the bitwise AND of 256 bits (representing double-precision floating-point elements) in "a" and "b", producing an intermediate 256-bit value, and set "ZF" to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set "ZF" to 0
  • _mm_testc_pd Compute the bitwise AND of 128 bits (representing double-precision floating-point elements) in "a" and "b", producing an intermediate 128-bit value, and set "ZF" to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set "ZF" to 0
  • _mm256_testc_ps Compute the bitwise AND of 256 bits (representing single-precision floating-point elements) in "a" and "b", producing an intermediate 256-bit value, and set "ZF" to 1 if the sign bit of each 32-bit element in the intermediate value is zero, otherwise set "ZF" to 0
  • _mm_testc_ps Compute the bitwise AND of 128 bits (representing single-precision floating-point elements) in "a" and "b", producing an intermediate 128-bit value, and set "ZF" to 1 if the sign bit of each 32-bit element in the intermediate value is zero, otherwise set "ZF" to 0
  • _mm_testc_si128 Compute the bitwise AND of 128 bits (representing integer data) in "a" and "b", and set "ZF" to 1 if the result is zero, otherwise set "ZF" to 0
  • _mm256_testc_si256 Compute the bitwise AND of 256 bits (representing integer data) in "a" and "b", and set "ZF" to 1 if the result is zero, otherwise set "ZF" to 0
  • _mm256_testnzc_pd Compute the bitwise AND of 256 bits (representing double-precision floating-point elements) in "a" and "b", producing an intermediate 256-bit value, and set "ZF" to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set "ZF" to 0
  • _mm_testnzc_pd Compute the bitwise AND of 128 bits (representing double-precision floating-point elements) in "a" and "b", producing an intermediate 128-bit value, and set "ZF" to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set "ZF" to 0
  • _mm256_testnzc_ps Compute the bitwise AND of 256 bits (representing single-precision floating-point elements) in "a" and "b", producing an intermediate 256-bit value, and set "ZF" to 1 if the sign bit of each 32-bit element in the intermediate value is zero, otherwise set "ZF" to 0
  • _mm_testnzc_ps Compute the bitwise AND of 128 bits (representing single-precision floating-point elements) in "a" and "b", producing an intermediate 128-bit value, and set "ZF" to 1 if the sign bit of each 32-bit element in the intermediate value is zero, otherwise set "ZF" to 0
  • _mm_testnzc_si128 Compute the bitwise AND of 128 bits (representing integer data) in "a" and "b", and set "ZF" to 1 if the result is zero, otherwise set "ZF" to 0
  • _mm256_testnzc_si256 Compute the bitwise AND of 256 bits (representing integer data) in "a" and "b", and set "ZF" to 1 if the result is zero, otherwise set "ZF" to 0
  • _mm256_testz_pd Compute the bitwise AND of 256 bits (representing double-precision floating-point elements) in "a" and "b", producing an intermediate 256-bit value, and set "ZF" to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set "ZF" to 0
  • _mm_testz_pd Compute the bitwise AND of 128 bits (representing double-precision floating-point elements) in "a" and "b", producing an intermediate 128-bit value, and set "ZF" to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set "ZF" to 0
  • _mm256_testz_ps Compute the bitwise AND of 256 bits (representing single-precision floating-point elements) in "a" and "b", producing an intermediate 256-bit value, and set "ZF" to 1 if the sign bit of each 32-bit element in the intermediate value is zero, otherwise set "ZF" to 0
  • _mm_testz_ps Compute the bitwise AND of 128 bits (representing single-precision floating-point elements) in "a" and "b", producing an intermediate 128-bit value, and set "ZF" to 1 if the sign bit of each 32-bit element in the intermediate value is zero, otherwise set "ZF" to 0
  • _mm_testz_si128 Compute the bitwise AND of 128 bits (representing integer data) in "a" and "b", and set "ZF" to 1 if the result is zero, otherwise set "ZF" to 0
  • _mm256_testz_si256 Compute the bitwise AND of 256 bits (representing integer data) in "a" and "b", and set "ZF" to 1 if the result is zero, otherwise set "ZF" to 0
  • _m_to_int Copy the lower 32-bit integer in "a" to "dst".
  • _m_to_int64 Copy 64-bit integer "a" to "dst".
  • _tpause Directs the processor to enter an implementation-dependent optimized state until the TSC reaches or exceeds the value specified in "counter"
  • _MM_TRANSPOSE4_PS Macro: Transpose the 4x4 matrix formed by the 4 rows of single-precision floating-point elements in "row0", "row1", "row2", and "row3", and store the transposed matrix in these vectors ("row0" now contains column 0, etc
  • _mm_trunc_pd Truncate the packed double-precision floating-point elements in "a"
  • _mm256_trunc_pd Truncate the packed double-precision floating-point elements in "a"
  • _mm_trunc_ps Truncate the packed single-precision floating-point elements in "a"
  • _mm256_trunc_ps Truncate the packed single-precision floating-point elements in "a"
  • _mm_tzcnt_32 Count the number of trailing zero bits in unsigned 32-bit integer "a"
  • _mm_tzcnt_64 Count the number of trailing zero bits in unsigned 64-bit integer "a"
  • _tzcnt_u32 Count the number of trailing zero bits in unsigned 32-bit integer "a"
  • _tzcnt_u64 Count the number of trailing zero bits in unsigned 64-bit integer "a"

U

  • _mm_ucomieq_sd Compare the lower double-precision floating-point element in "a" and "b" for equality
  • _mm_ucomieq_ss Compare the lower single-precision floating-point element in "a" and "b" for equality
  • _mm_ucomige_sd Compare the lower double-precision floating-point element in "a" and "b" for greater-than-or-equal
  • _mm_ucomige_ss Compare the lower single-precision floating-point element in "a" and "b" for greater-than-or-equal
  • _mm_ucomigt_sd Compare the lower double-precision floating-point element in "a" and "b" for greater-than
  • _mm_ucomigt_ss Compare the lower single-precision floating-point element in "a" and "b" for greater-than
  • _mm_ucomile_sd Compare the lower double-precision floating-point element in "a" and "b" for less-than-or-equal
  • _mm_ucomile_ss Compare the lower single-precision floating-point element in "a" and "b" for less-than-or-equal
  • _mm_ucomilt_sd Compare the lower double-precision floating-point element in "a" and "b" for less-than
  • _mm_ucomilt_ss Compare the lower single-precision floating-point element in "a" and "b" for less-than
  • _mm_ucomineq_sd Compare the lower double-precision floating-point element in "a" and "b" for not-equal
  • _mm_ucomineq_ss Compare the lower single-precision floating-point element in "a" and "b" for not-equal
  • _mm_udiv_epi32 Divide packed unsigned 32-bit integers in "a" by packed elements in "b", and store the truncated results in "dst"
  • _mm256_udiv_epi32 Divide packed unsigned 32-bit integers in "a" by packed elements in "b", and store the truncated results in "dst"
  • _mm_udivrem_epi32 Divide packed unsigned 32-bit integers in "a" by packed elements in "b", store the truncated results in "dst", and store the remainders as packed unsigned 32-bit integers into memory at "mem_addr"
  • _mm256_udivrem_epi32 Divide packed unsigned 32-bit integers in "a" by packed elements in "b", store the truncated results in "dst", and store the remainders as packed unsigned 32-bit integers into memory at "mem_addr"
  • _umonitor Sets up a linear address range to be monitored by hardware and activates the monitor
  • _umwait Directs the processor to enter an implementation-dependent optimized state while monitoring a range of addresses
  • _mm_undefined_pd Return vector of type __m128d with undefined elements.
  • _mm256_undefined_pd Return vector of type __m256d with undefined elements.
  • _mm_undefined_ps Return vector of type __m128 with undefined elements.
  • _mm256_undefined_ps Return vector of type __m256 with undefined elements.
  • _mm_undefined_si128 Return vector of type __m128i with undefined elements.
  • _mm256_undefined_si256 Return vector of type __m256i with undefined elements.
  • _mm_unpackhi_epi8 Unpack and interleave 8-bit integers from the high half of "a" and "b"
  • _mm256_unpackhi_epi8 Unpack and interleave 8-bit integers from the high half of each 128-bit lane in "a" and "b"
  • _mm_unpackhi_epi16 Unpack and interleave 16-bit integers from the high half of "a" and "b"
  • _mm256_unpackhi_epi16 Unpack and interleave 16-bit integers from the high half of each 128-bit lane in "a" and "b"
  • _mm_unpackhi_epi32 Unpack and interleave 32-bit integers from the high half of "a" and "b"
  • _mm256_unpackhi_epi32 Unpack and interleave 32-bit integers from the high half of each 128-bit lane in "a" and "b"
  • _mm_unpackhi_epi64 Unpack and interleave 64-bit integers from the high half of "a" and "b"
  • _mm256_unpackhi_epi64 Unpack and interleave 64-bit integers from the high half of each 128-bit lane in "a" and "b"
  • _mm_unpackhi_pd Unpack and interleave double-precision floating-point elements from the high half of "a" and "b"
  • _mm256_unpackhi_pd Unpack and interleave double-precision floating-point elements from the high half of each 128-bit lane in "a" and "b"
  • _mm_unpackhi_pi8 Unpack and interleave 8-bit integers from the high half of "a" and "b"
  • _mm_unpackhi_pi16 Unpack and interleave 16-bit integers from the high half of "a" and "b"
  • _mm_unpackhi_pi32 Unpack and interleave 32-bit integers from the high half of "a" and "b"
  • _mm_unpackhi_ps Unpack and interleave single-precision floating-point elements from the high half "a" and "b"
  • _mm256_unpackhi_ps Unpack and interleave single-precision floating-point elements from the high half of each 128-bit lane in "a" and "b"
  • _mm_unpacklo_epi8 Unpack and interleave 8-bit integers from the low half of "a" and "b"
  • _mm256_unpacklo_epi8 Unpack and interleave 8-bit integers from the low half of each 128-bit lane in "a" and "b"
  • _mm_unpacklo_epi16 Unpack and interleave 16-bit integers from the low half of "a" and "b"
  • _mm256_unpacklo_epi16 Unpack and interleave 16-bit integers from the low half of each 128-bit lane in "a" and "b"
  • _mm_unpacklo_epi32 Unpack and interleave 32-bit integers from the low half of "a" and "b"
  • _mm256_unpacklo_epi32 Unpack and interleave 32-bit integers from the low half of each 128-bit lane in "a" and "b"
  • _mm_unpacklo_epi64 Unpack and interleave 64-bit integers from the low half of "a" and "b"
  • _mm256_unpacklo_epi64 Unpack and interleave 64-bit integers from the low half of each 128-bit lane in "a" and "b"
  • _mm_unpacklo_pd Unpack and interleave double-precision floating-point elements from the low half of "a" and "b"
  • _mm256_unpacklo_pd Unpack and interleave double-precision floating-point elements from the low half of each 128-bit lane in "a" and "b"
  • _mm_unpacklo_pi8 Unpack and interleave 8-bit integers from the low half of "a" and "b"
  • _mm_unpacklo_pi16 Unpack and interleave 16-bit integers from the low half of "a" and "b"
  • _mm_unpacklo_pi32 Unpack and interleave 32-bit integers from the low half of "a" and "b"
  • _mm_unpacklo_ps Unpack and interleave single-precision floating-point elements from the low half of "a" and "b"
  • _mm256_unpacklo_ps Unpack and interleave single-precision floating-point elements from the low half of each 128-bit lane in "a" and "b"
  • _mm_urem_epi32 Divide packed unsigned 32-bit integers in "a" by packed elements in "b", and store the remainders as packed unsigned 32-bit integers in "dst"
  • _mm256_urem_epi32 Divide packed unsigned 32-bit integers in "a" by packed elements in "b", and store the remainders as packed unsigned 32-bit integers in "dst"

W

  • _wbinvd Write back and flush internal caches. Initiate writing-back and flushing of external caches.
  • _wbnoinvd Write back and do not flush internal caches. Initiate writing-back without flushing of external caches.
  • _writefsbase_u32 Write the unsigned 32-bit integer "a" to the FS segment base register
  • _writefsbase_u64 Write the unsigned 64-bit integer "a" to the FS segment base register
  • _writegsbase_u32 Write the unsigned 32-bit integer "a" to the GS segment base register
  • _writegsbase_u64 Write the unsigned 64-bit integer "a" to the GS segment base register
  • _wrssd Write 32-bit value in "val" to a shadow stack page in memory specified by "p"
  • _wrssq Write 64-bit value in "val" to a shadow stack page in memory specified by "p"
  • _wrussd Write 32-bit value in "val" to a user shadow stack page in memory specified by "p"
  • _wrussq Write 64-bit value in "val" to a user shadow stack page in memory specified by "p"

X

  • _xabort Force an RTM abort. The EAX register is updated to reflect an XABORT instruction caused the abort, and the "imm8" parameter will be provided in bits [31:24] of EAX. Following an RTM abort, the logical processor resumes execution at the fallback address computed through the outermost XBEGIN instruction.
  • _xbegin Specify the start of an RTM code region. If the logical processor was not already in transactional execution, then this call causes the logical processor to transition into transactional execution. On an RTM abort, the logical processor discards all architectural register and memory updates performed during the RTM execution, restores architectural state, and starts execution beginning at the fallback address computed from the outermost XBEGIN instruction. Return status of ~0 (0xFFFF) if continuing inside transaction
  • _xend Specify the end of an RTM code region. If this corresponds to the outermost scope, the logical processor will attempt to commit the logical processor state atomically. If the commit fails, the logical processor will perform an RTM abort.
  • _xgetbv Copy up to 64-bits from the value of the extended control register (XCR) specified by "a" into "dst"
  • _mm_xor_pd Compute the bitwise XOR of packed double-precision floating-point elements in "a" and "b"
  • _mm256_xor_pd Compute the bitwise XOR of packed double-precision floating-point elements in "a" and "b"
  • _mm_xor_ps Compute the bitwise XOR of packed single-precision floating-point elements in "a" and "b"
  • _mm256_xor_ps Compute the bitwise XOR of packed single-precision floating-point elements in "a" and "b"
  • _mm_xor_si64 Compute the bitwise XOR of 64 bits (representing integer data) in "a" and "b"
  • _mm_xor_si128 Compute the bitwise XOR of 128 bits (representing integer data) in "a" and "b"
  • _mm256_xor_si256 Compute the bitwise XOR of 256 bits (representing integer data) in "a" and "b"
  • _xrstor Perform a full or partial restore of the enabled processor states using the state information stored in memory at "mem_addr"
  • _xrstor64 Perform a full or partial restore of the enabled processor states using the state information stored in memory at "mem_addr"
  • _xrstors Perform a full or partial restore of the enabled processor states using the state information stored in memory at "mem_addr"
  • _xrstors64 Perform a full or partial restore of the enabled processor states using the state information stored in memory at "mem_addr"
  • _xsave Perform a full or partial save of the enabled processor states to memory at "mem_addr"
  • _xsave64 Perform a full or partial save of the enabled processor states to memory at "mem_addr"
  • _xsavec Perform a full or partial save of the enabled processor states to memory at "mem_addr"
  • _xsavec64 Perform a full or partial save of the enabled processor states to memory at "mem_addr"
  • _xsaveopt Perform a full or partial save of the enabled processor states to memory at "mem_addr"
  • _xsaveopt64 Perform a full or partial save of the enabled processor states to memory at "mem_addr"
  • _xsaves Perform a full or partial save of the enabled processor states to memory at "mem_addr"
  • _xsaves64 Perform a full or partial save of the enabled processor states to memory at "mem_addr"
  • _xsetbv Copy 64-bits from "val" to the extended control register (XCR) specified by "a"
  • _xtest Query the transactional execution status, return 1 if inside a transactionally executing RTM or HLE region

Z

  • _mm256_zeroall Zero the contents of all XMM or YMM registers.
  • _mm256_zeroupper Zero the upper 128 bits of all YMM registers; the lower 128-bits of the registers are unmodified
  • _mm256_zextpd128_pd256 Casts vector of type __m128d to type __m256d; the upper 128 bits of the result are zeroed
  • _mm256_zextps128_ps256 Casts vector of type __m128 to type __m256; the upper 128 bits of the result are zeroed
  • _mm256_zextsi128_si256 Casts vector of type __m128i to type __m256i; the upper 128 bits of the result are zeroed


__rdtscp

unsigned __int64 __rdtscp( unsigned int * mem_addr )

Synopsis

#include "immintrin.h"
Instruction: rdtscp
CPUID Flag: RDTSCP
Category: General Support

Description

Copy the current 64-bit value of the processor's time-stamp counter into "dst", and store the IA32_TSC_AUX MSR (signature value) into memory at "mem_addr".

Operation

dst[63:0] := TimeStampCounter
MEM[mem_addr+31:mem_addr] := IA32_TSC_AUX[31:0]


_addcarry_u32

unsigned char _addcarry_u32( unsigned char c_in, unsigned int a, unsigned int b, unsigned int * out )

Synopsis

#include "immintrin.h"
Instruction: adc
Category: Arithmetic

Description

Add unsigned 32-bit integers "a" and "b" with unsigned 8-bit carry-in "c_in" (carry flag), and store the unsigned 32-bit result in "out", and the carry-out in "dst" (carry or overflow flag).

Operation

out[31:0] := a[31:0] + b[31:0] + c_in
dst := carry_out


_addcarry_u64

unsigned char _addcarry_u64( unsigned char c_in, unsigned __int64 a, unsigned __int64 b, unsigned __int64 * out )

Synopsis

#include "immintrin.h"
Instruction: adc
Category: Arithmetic

Description

Add unsigned 64-bit integers "a" and "b" with unsigned 8-bit carry-in "c_in" (carry flag), and store the unsigned 64-bit result in "out", and the carry-out in "dst" (carry or overflow flag).

Operation

out[63:0] := a[63:0] + b[63:0] + c_in
dst := carry_out


_addcarryx_u32

unsigned char _addcarryx_u32( unsigned char c_in, unsigned int a, unsigned int b, unsigned int * out )

Synopsis

#include "immintrin.h"
Instruction: adcx
CPUID Flag: ADX
Category: Arithmetic

Description

Add unsigned 32-bit integers "a" and "b" with unsigned 8-bit carry-in "c_in" (carry or overflow flag), and store the unsigned 32-bit result in "out", and the carry-out in "dst" (carry or overflow flag).

Operation

out[31:0] := a[31:0] + b[31:0] + c_in
dst := carry_out

Performance

Architecture | Latency | Throughput | μops
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_addcarryx_u64

unsigned char _addcarryx_u64( unsigned char c_in, unsigned __int64 a, unsigned __int64 b, unsigned __int64 * out )

Synopsis

#include "immintrin.h"
Instruction: adcx
CPUID Flag: ADX
Category: Arithmetic

Description

Add unsigned 64-bit integers "a" and "b" with unsigned 8-bit carry-in "c_in" (carry or overflow flag), and store the unsigned 64-bit result in "out", and the carry-out in "dst" (carry or overflow flag).

Operation

out[63:0] := a[63:0] + b[63:0] + c_in
dst := carry_out

Performance

Architecture | Latency | Throughput | μops
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_allow_cpu_features

void _allow_cpu_features( unsigned __int64 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
Category: General Support

Description

Treat the processor-specific feature(s) specified in "a" as available. Multiple features may be OR'd together. See the valid feature flags below:

Operation

_FEATURE_GENERIC_IA32
_FEATURE_FPU
_FEATURE_CMOV
_FEATURE_MMX
_FEATURE_FXSAVE
_FEATURE_SSE
_FEATURE_SSE2
_FEATURE_SSE3
_FEATURE_SSSE3
_FEATURE_SSE4_1
_FEATURE_SSE4_2
_FEATURE_MOVBE
_FEATURE_POPCNT
_FEATURE_PCLMULQDQ
_FEATURE_AES
_FEATURE_F16C
_FEATURE_AVX
_FEATURE_RDRND
_FEATURE_FMA
_FEATURE_BMI
_FEATURE_LZCNT
_FEATURE_HLE
_FEATURE_RTM
_FEATURE_AVX2
_FEATURE_KNCNI
_FEATURE_AVX512F
_FEATURE_ADX
_FEATURE_RDSEED
_FEATURE_AVX512ER
_FEATURE_AVX512PF
_FEATURE_AVX512CD
_FEATURE_SHA
_FEATURE_MPX
_FEATURE_AVX512BW
_FEATURE_AVX512VL
_FEATURE_AVX512VBMI
_FEATURE_AVX512_4FMAPS
_FEATURE_AVX512_4VNNIW
_FEATURE_AVX512_VPOPCNTDQ
_FEATURE_AVX512_BITALG
_FEATURE_AVX512_VBMI2
_FEATURE_GFNI
_FEATURE_VAES
_FEATURE_VPCLMULQDQ
_FEATURE_AVX512_VNNI
_FEATURE_CLWB
_FEATURE_RDPID
_FEATURE_IBT
_FEATURE_SHSTK
_FEATURE_SGX
_FEATURE_WBNOINVD
_FEATURE_PCONFIG


_andn_u32

unsigned int _andn_u32( unsigned int a, unsigned int b )

Synopsis

#include "immintrin.h"
Instruction: andn
CPUID Flag: BMI1
Category: Bit Manipulation

Description

Compute the bitwise NOT of 32-bit integer "a" and then AND with b, and store the results in dst.

Operation

dst[31:0] := ((NOT a[31:0]) AND b[31:0])

Performance

Architecture | Latency | Throughput | μops
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.5 |


_andn_u64

unsigned __int64 _andn_u64( unsigned __int64 a, unsigned __int64 b )

Synopsis

#include "immintrin.h"
Instruction: andn
CPUID Flag: BMI1
Category: Bit Manipulation

Description

Compute the bitwise NOT of 64-bit integer "a" and then AND with b, and store the results in dst.

Operation

dst[63:0] := ((NOT a[63:0]) AND b[63:0])

Performance

Architecture | Latency | Throughput | μops
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.5 |


_bextr_u32

unsigned int _bextr_u32( unsigned int a, unsigned int start, unsigned int len )

Synopsis

#include "immintrin.h"
Instruction: bextr
CPUID Flag: BMI1
Category: Bit Manipulation

Description

Extract contiguous bits from unsigned 32-bit integer "a", and store the result in "dst". Extract the number of bits specified by "len", starting at the bit specified by "start".

Operation

tmp := ZeroExtend_To_512(a)
dst := ZeroExtend(tmp[start+len-1:start])

Performance

Architecture | Latency | Throughput | μops
Haswell | 2 | 0.5 |
Broadwell | 2 | 0.5 |
Skylake | 2 | 0.5 |


_bextr_u64

unsigned __int64 _bextr_u64( unsigned __int64 a, unsigned int start, unsigned int len )

Synopsis

#include "immintrin.h"
Instruction: bextr
CPUID Flag: BMI1
Category: Bit Manipulation

Description

Extract contiguous bits from unsigned 64-bit integer "a", and store the result in "dst". Extract the number of bits specified by "len", starting at the bit specified by "start".

Operation

tmp := ZeroExtend_To_512(a)
dst := ZeroExtend(tmp[start+len-1:start])

Performance

Architecture | Latency | Throughput | μops
Haswell | 2 | 0.5 |
Broadwell | 2 | 0.5 |
Skylake | 2 | 0.5 |


_bextr2_u32

unsigned int _bextr2_u32( unsigned int a, unsigned int control )

Synopsis

#include "immintrin.h"
Instruction: bextr
CPUID Flag: BMI1
Category: Bit Manipulation

Description

Extract contiguous bits from unsigned 32-bit integer "a", and store the result in "dst". Extract the number of bits specified by bits 15:8 of "control", starting at the bit specified by bits 0:7 of "control".

Operation

start := control[7:0]
len := control[15:8]
tmp := ZeroExtend_To_512(a)
dst := ZeroExtend(tmp[start+len-1:start])

Performance

Architecture | Latency | Throughput | μops
Haswell | 2 | 0.5 |
Broadwell | 2 | 0.5 |
Skylake | 2 | 0.5 |


_bextr2_u64

unsigned __int64 _bextr2_u64( unsigned __int64 a, unsigned __int64 control )

Synopsis

#include "immintrin.h"
Instruction: bextr
CPUID Flag: BMI1
Category: Bit Manipulation

Description

Extract contiguous bits from unsigned 64-bit integer "a", and store the result in "dst". Extract the number of bits specified by bits 15:8 of "control", starting at the bit specified by bits 0:7 of "control"..

Operation

start := control[7:0]
len := control[15:8]
tmp := ZeroExtend_To_512(a)
dst := ZeroExtend(tmp[start+len-1:start])

Performance

Architecture | Latency | Throughput | μops
Haswell | 2 | 0.5 |
Broadwell | 2 | 0.5 |
Skylake | 2 | 0.5 |


_bit_scan_forward

int _bit_scan_forward( int a )

Synopsis

#include "immintrin.h"
Instruction: bsf
Category: Bit Manipulation

Description

Set "dst" to the index of the lowest set bit in 32-bit integer "a". If no bits are set in "a" then "dst" is undefined.

Operation

tmp := 0
IF a == 0
    dst := undefined
ELSE
    DO WHILE ((tmp < 32) AND a[tmp] == 0)
        tmp := tmp + 1
        dst := tmp
    OD
FI


_bit_scan_reverse

int _bit_scan_reverse( int a )

Synopsis

#include "immintrin.h"
Instruction: bsr
Category: Bit Manipulation

Description

Set "dst" to the index of the highest set bit in 32-bit integer "a". If no bits are set in "a" then "dst" is undefined.

Operation

tmp := 31
IF a == 0
    dst := undefined
ELSE
    DO WHILE ((tmp > 0) AND a[tmp] == 0)
        tmp := tmp - 1
        dst := tmp
    OD
FI


_BitScanForward

unsigned char _BitScanForward( unsigned __int32* index, unsigned __int32 mask )

Synopsis

#include "immintrin.h"
Instruction: bsf
Category: Bit Manipulation

Description

Set "index" to the index of the lowest set bit in 32-bit integer "mask". If no bits are set in "mask", then set "dst" to 0, otherwise set "dst" to 1.

Operation

tmp := 0
IF mask == 0
    dst := 0
ELSE
    DO WHILE ((tmp < 32) AND mask[tmp] == 0)
        tmp := tmp + 1
        index := tmp
        dst := 1
    OD
FI


_BitScanForward64

unsigned char _BitScanForward64( unsigned __int32* index, unsigned __int64 mask )

Synopsis

#include "immintrin.h"
Instruction: bsf
Category: Bit Manipulation

Description

Set "index" to the index of the lowest set bit in 64-bit integer "mask". If no bits are set in "mask", then set "dst" to 0, otherwise set "dst" to 1.

Operation

tmp := 0
IF mask == 0
    dst := 0
ELSE
    DO WHILE ((tmp < 64) AND mask[tmp] == 0)
        tmp := tmp + 1
        index := tmp
        dst := 1
    OD
FI


_BitScanReverse

unsigned char _BitScanReverse( unsigned __int32* index, unsigned __int32 mask )

Synopsis

#include "immintrin.h"
Instruction: bsr
Category: Bit Manipulation

Description

Set "index" to the index of the highest set bit in 32-bit integer "mask". If no bits are set in "mask", then set "dst" to 0, otherwise set "dst" to 1.

Operation

tmp := 31
IF mask == 0
    dst := 0
ELSE
    DO WHILE ((tmp > 0) AND mask[tmp] == 0)
        tmp := tmp - 1
        index := tmp
        dst := 1
    OD
FI


_BitScanReverse64

unsigned char _BitScanReverse64( unsigned __int32* index, unsigned __int64 mask )

Synopsis

#include "immintrin.h"
Instruction: bsr
Category: Bit Manipulation

Description

Set "index" to the index of the highest set bit in 64-bit integer "mask". If no bits are set in "mask", then set "dst" to 0, otherwise set "dst" to 1.

Operation

tmp := 31
IF mask == 0
    dst := 0
ELSE
    DO WHILE ((tmp > 0) AND mask[tmp] == 0)
        tmp := tmp - 1
        index := tmp
        dst := 1
    OD
FI


_bittest

unsigned char _bittest( __int32* a, __int32 b )

Synopsis

#include "immintrin.h"
Instruction: bt
Category: Bit Manipulation

Description

Return the bit at index "b" of 32-bit integer "a".

Operation

dst := a[b]


_bittest64

unsigned char _bittest64( __int64* a, __int64 b )

Synopsis

#include "immintrin.h"
Instruction: bt
Category: Bit Manipulation

Description

Return the bit at index "b" of 64-bit integer "a".

Operation

dst := a[b]


_bittestandcomplement

unsigned char _bittestandcomplement( __int32* a, __int32 b )

Synopsis

#include "immintrin.h"
Instruction: btc
Category: Bit Manipulation

Description

Return the bit at index "b" of 32-bit integer "a", and set that bit to its complement.

Operation

dst := a[b]
a[b] := ~a[b]


_bittestandcomplement64

unsigned char _bittestandcomplement64( __int64* a, __int64 b )

Synopsis

#include "immintrin.h"
Instruction: btc
Category: Bit Manipulation

Description

Return the bit at index "b" of 64-bit integer "a", and set that bit to its complement.

Operation

dst := a[b]
a[b] := ~a[b]


_bittestandreset

unsigned char _bittestandreset( __int32* a, __int32 b )

Synopsis

#include "immintrin.h"
Instruction: btr
Category: Bit Manipulation

Description

Return the bit at index "b" of 32-bit integer "a", and set that bit to zero.

Operation

dst := a[b]
a[b] := 0


_bittestandreset64

unsigned char _bittestandreset64( __int64* a, __int64 b )

Synopsis

#include "immintrin.h"
Instruction: btr
Category: Bit Manipulation

Description

Return the bit at index "b" of 64-bit integer "a", and set that bit to zero.

Operation

dst := a[b]
a[b] := 0


_bittestandset

unsigned char _bittestandset( __int32* a, __int32 b )

Synopsis

#include "immintrin.h"
Instruction: bts
Category: Bit Manipulation

Description

Return the bit at index "b" of 32-bit integer "a", and set that bit to one.

Operation

dst := a[b]
a[b] := 1


_bittestandset64

unsigned char _bittestandset64( __int64* a, __int64 b )

Synopsis

#include "immintrin.h"
Instruction: bts
Category: Bit Manipulation

Description

Return the bit at index "b" of 64-bit integer "a", and set that bit to one.

Operation

dst := a[b]
a[b] := 1


_blsi_u32

unsigned int _blsi_u32( unsigned int a )

Synopsis

#include "immintrin.h"
Instruction: blsi
CPUID Flag: BMI1
Category: Bit Manipulation

Description

Extract the lowest set bit from unsigned 32-bit integer "a" and set the corresponding bit in "dst". All other bits in "dst" are zeroed, and all bits are zeroed if no bits are set in "a".

Operation

dst := (-a) AND a

Performance

Architecture | Latency | Throughput | μops
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.5 |


_blsi_u64

unsigned __int64 _blsi_u64( unsigned __int64 a )

Synopsis

#include "immintrin.h"
Instruction: blsi
CPUID Flag: BMI1
Category: Bit Manipulation

Description

Extract the lowest set bit from unsigned 64-bit integer "a" and set the corresponding bit in "dst". All other bits in "dst" are zeroed, and all bits are zeroed if no bits are set in "a".

Operation

dst := (-a) AND a

Performance

Architecture | Latency | Throughput | μops
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.5 |


_blsmsk_u32

unsigned int _blsmsk_u32( unsigned int a )

Synopsis

#include "immintrin.h"
Instruction: blsmsk
CPUID Flag: BMI1
Category: Bit Manipulation

Description

Set all the lower bits of "dst" up to and including the lowest set bit in unsigned 32-bit integer "a".

Operation

dst := (a - 1) XOR a

Performance

Architecture | Latency | Throughput | μops
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.5 |


_blsmsk_u64

unsigned __int64 _blsmsk_u64( unsigned __int64 a )

Synopsis

#include "immintrin.h"
Instruction: blsmsk
CPUID Flag: BMI1
Category: Bit Manipulation

Description

Set all the lower bits of "dst" up to and including the lowest set bit in unsigned 64-bit integer "a".

Operation

dst := (a - 1) XOR a

Performance

Architecture | Latency | Throughput | μops
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.5 |


_blsr_u32

unsigned int _blsr_u32( unsigned int a )

Synopsis

#include "immintrin.h"
Instruction: blsr
CPUID Flag: BMI1
Category: Bit Manipulation

Description

Copy all bits from unsigned 32-bit integer "a" to "dst", and reset (set to 0) the bit in "dst" that corresponds to the lowest set bit in "a".

Operation

dst := (a - 1) AND a

Performance

Architecture | Latency | Throughput | μops
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.5 |


_blsr_u64

unsigned __int64 _blsr_u64( unsigned __int64 a )

Synopsis

#include "immintrin.h"
Instruction: blsr
CPUID Flag: BMI1
Category: Bit Manipulation

Description

Copy all bits from unsigned 64-bit integer "a" to "dst", and reset (set to 0) the bit in "dst" that corresponds to the lowest set bit in "a".

Operation

dst := (a - 1) AND a

Performance

Architecture | Latency | Throughput | μops
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.5 |


_bnd_chk_ptr_bounds

void _bnd_chk_ptr_bounds( const void * q, size_t size )

Synopsis

#include "immintrin.h"
Instruction: bndcu
CPUID Flag: MPX
Category: Miscellaneous

Description

Checks if ["q", "q" + "size" - 1] is within the lower and upper bounds of "q" and throws a #BR if not.

Operation

IF (q + size - 1) < q.LB OR (q + size - 1) > q.UB
    #BR
FI


_bnd_chk_ptr_lbounds

void _bnd_chk_ptr_lbounds( const void * q )

Synopsis

#include "immintrin.h"
Instruction: bndcl
CPUID Flag: MPX
Category: Miscellaneous

Description

Checks if "q" is within its lower bound, and throws a #BR if not.

Operation

IF q < q.LB
    #BR
FI


_bnd_chk_ptr_ubounds

void _bnd_chk_ptr_ubounds( const void * q )

Synopsis

#include "immintrin.h"
Instruction: bndcu
CPUID Flag: MPX
Category: Miscellaneous

Description

Checks if "q" is within its upper bound, and throws a #BR if not.

Operation

IF q > q.UB
    #BR
FI


_bnd_copy_ptr_bounds

void * _bnd_copy_ptr_bounds( const void * q, const void * r )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: MPX
Category: Miscellaneous

Description

Make a pointer with the value of "q" and bounds set to the bounds of "r" (e.g. copy the bounds of "r" to pointer "q"), and store the result in "dst".

Operation

dst := q
dst.LB := r.LB
dst.UB := r.UB


_bnd_get_ptr_lbound

const void * _bnd_get_ptr_lbound( const void * q )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: MPX
Category: Miscellaneous

Description

Return the lower bound of "q".

Operation

dst := q.LB


_bnd_get_ptr_ubound

const void * _bnd_get_ptr_ubound( const void * q )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: MPX
Category: Miscellaneous

Description

Return the upper bound of "q".

Operation

dst := q.UB


_bnd_init_ptr_bounds

void * _bnd_init_ptr_bounds( const void * q )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: MPX
Category: Miscellaneous

Description

Make a pointer with the value of "q" and open bounds, which allow the pointer to access the entire virtual address space, and store the result in "dst".

Operation

dst := q
dst.LB := 0
dst.UB := 0


_bnd_narrow_ptr_bounds

void * _bnd_narrow_ptr_bounds( const void * q, const void * r, size_t size )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: MPX
Category: Miscellaneous

Description

Narrow the bounds for pointer "q" to the intersection of the bounds of "r" and the bounds ["q", "q" + "size" - 1], and store the result in "dst".

Operation

dst := q
IF r.LB > (q + size - 1) OR r.UB < q
    dst.LB := 1
    dst.UB := 0
ELSE
    dst.LB := MAX(r.LB, q)
    dst.UB := MIN(r.UB, (q + size - 1))
FI


_bnd_set_ptr_bounds

void * _bnd_set_ptr_bounds( const void * srcmem, size_t size )

Synopsis

#include "immintrin.h"
Instruction: bndmk
CPUID Flag: MPX
Category: Miscellaneous

Description

Make a pointer with the value of "srcmem" and bounds set to ["srcmem", "srcmem" + "size" - 1], and store the result in "dst".

Operation

dst := srcmem
dst.LB := srcmem.LB
dst.UB := srcmem + size - 1


_bnd_store_ptr_bounds

void _bnd_store_ptr_bounds( const void ** ptr_addr, const void * ptr_val )

Synopsis

#include "immintrin.h"
Instruction: bndstx
CPUID Flag: MPX
Category: Miscellaneous

Description

Stores the bounds of "ptr_val" pointer in memory at address "ptr_addr".

Operation

MEM[ptr_addr].LB := ptr_val.LB
MEM[ptr_addr].UB := ptr_val.UB


_bswap

int _bswap( int a )

Synopsis

#include "immintrin.h"
Instruction: bswap
Category: Bit Manipulation

Description

Reverse the byte order of 32-bit integer "a", and store the result in "dst". This intrinsic is provided for conversion between little and big endian values.

Operation

dst[7:0] := a[31:24]
dst[15:8] := a[23:16]
dst[23:16] := a[15:8]
dst[31:24] := a[7:0]


_bswap64

__int64 _bswap64( __int64 a )

Synopsis

#include "immintrin.h"
Instruction: bswap
Category: Bit Manipulation

Description

Reverse the byte order of 64-bit integer "a", and store the result in "dst". This intrinsic is provided for conversion between little and big endian values.

Operation

dst[7:0] := a[63:56]
dst[15:8] := a[55:48]
dst[23:16] := a[47:40]
dst[31:24] := a[39:32]
dst[39:32] := a[31:24]
dst[47:40] := a[23:16]
dst[55:48] := a[15:8]
dst[63:56] := a[7:0]


_bzhi_u32

unsigned int _bzhi_u32( unsigned int a, unsigned int index )

Synopsis

#include "immintrin.h"
Instruction: bzhi
CPUID Flag: BMI2
Category: Bit Manipulation

Description

Copy all bits from unsigned 32-bit integer "a" to "dst", and reset (set to 0) the high bits in "dst" starting at "index".

Operation

n := index[7:0]
dst := a
IF (n < 32)
    dst[31:n] := 0
FI

Performance

Architecture | Latency | Throughput | μops
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.5 |


_bzhi_u64

unsigned __int64 _bzhi_u64( unsigned __int64 a, unsigned int index )

Synopsis

#include "immintrin.h"
Instruction: bzhi
CPUID Flag: BMI2
Category: Bit Manipulation

Description

Copy all bits from unsigned 64-bit integer "a" to "dst", and reset (set to 0) the high bits in "dst" starting at "index".

Operation

n := index[7:0]
dst := a
IF (n < 64)
    dst[63:n] := 0
FI

Performance

Architecture | Latency | Throughput | μops
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.5 |


_castf32_u32

unsigned __int32 _castf32_u32( float a )

Synopsis

#include "immintrin.h"
Instruction: N/A
Category: Cast

Description

Cast from type float to type unsigned __int32 without conversion. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.


_castf64_u64

unsigned __int64 _castf64_u64( double a )

Synopsis

#include "immintrin.h"
Instruction: N/A
Category: Cast

Description

Cast from type double to type unsigned __int64 without conversion. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.


_castu32_f32

float _castu32_f32( unsigned __int32 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
Category: Cast

Description

Cast from type unsigned __int32 to type float without conversion. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.


_castu64_f64

double _castu64_f64( unsigned __int64 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
Category: Cast

Description

Cast from type unsigned __int64 to type double without conversion. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.


_clrssbsy

void _clrssbsy( void * p )

Synopsis

#include "immintrin.h"
Instruction: clrssbsy
Category: Miscellaneous

Description

Mark shadow stack pointed to by "p" as not busy.


_cvtsh_ss

float _cvtsh_ss( unsigned short a )

Synopsis

#include "emmintrin.h"
Instruction: N/A
Category: Convert

Description

Convert the half-precision (16-bit) floating-point value "a" to a single-precision (32-bit) floating-point value, and store the result in "dst".

Operation

dst[31:0] := Convert_FP16_To_FP32(a[15:0])


_cvtss_sh

unsigned short _cvtss_sh( float a, int rounding )

Synopsis

#include "emmintrin.h"
Instruction: N/A
Category: Convert

Description

Convert the single-precision (32-bit) floating-point value "a" to a half-precision (16-bit) floating-point value, and store the result in "dst". [round_note]

Operation

dst[15:0] := Convert_FP32_To_FP16(a[31:0])


_directstoreu_u32

void _directstoreu_u32( void* dst, unsigned int val )

Synopsis

#include "immintrin.h"
Instruction: MOVDIRI
CPUID Flag: MOVDIRI
Category: Store

Description

Store 32-bit integer from "val" into memory using direct store.

Operation

dst[31:0] := val[31:0]


_directstoreu_u64

void _directstoreu_u64( void* dst, unsigned __int64 val )

Synopsis

#include "immintrin.h"
Instruction: MOVDIRI
CPUID Flag: MOVDIRI
Category: Store

Description

Store 64-bit integer from "val" into memory using direct store.

Operation

dst[63:0] := val[63:0]


_encls_u32

unsigned int _encls_u32( const int a, size_t* __data )

Synopsis

#include "immintrin.h"
Instruction: encls
Category: Miscellaneous

Description

Invoke the Intel SGX enclave system (privileged) leaf function specified by "a", and return the error code. The "__data" array contains 3 32-bit elements that may act as input, output, or be unused, depending on the semantics of the specified leaf function; these correspond to ebx, ecx, and edx.


_enclu_u32

unsigned int _enclu_u32( const int a, size_t* __data )

Synopsis

#include "immintrin.h"
Instruction: enclu
Category: Miscellaneous

Description

Invoke the Intel SGX enclave user (non-privilege) leaf function specified by "a", and return the error code. The "__data" array contains 3 32-bit elements that may act as input, output, or be unused, depending on the semantics of the specified leaf function; these correspond to ebx, ecx, and edx.


_enclv_u32

unsigned int _enclv_u32( const int a, size_t* __data )

Synopsis

#include "immintrin.h"
Instruction: enclv
Category: Miscellaneous

Description

Invoke the Intel SGX enclave virtualized (VMM) leaf function specified by "a", and return the error code. The "__data" array contains 3 32-bit elements that may act as input, output, or be unused, depending on the semantics of the specified leaf function; these correspond to ebx, ecx, and edx.


_fxrstor

void _fxrstor( void * mem_addr )

Synopsis

#include "immintrin.h"
Instruction: fxrstor
CPUID Flag: FXSR
Category: OS-Targeted

Description

Reload the x87 FPU, MMX technology, XMM, and MXCSR registers from the 512-byte memory image at "mem_addr". This data should have been written to memory previously using the FXSAVE instruction, and in the same format as required by the operating mode. "mem_addr" must be aligned on a 16-byte boundary.

Operation

state_x87_fpu_mmx_sse := fxrstor(MEM[mem_addr+512*8:mem_addr])


_fxrstor64

void _fxrstor64( void * mem_addr )

Synopsis

#include "immintrin.h"
Instruction: fxrstor64
CPUID Flag: FXSR
Category: OS-Targeted

Description

Reload the x87 FPU, MMX technology, XMM, and MXCSR registers from the 512-byte memory image at "mem_addr". This data should have been written to memory previously using the FXSAVE64 instruction, and in the same format as required by the operating mode. "mem_addr" must be aligned on a 16-byte boundary.

Operation

state_x87_fpu_mmx_sse := fxrstor64(MEM[mem_addr+512*8:mem_addr])


_fxsave

void _fxsave( void * mem_addr )

Synopsis

#include "immintrin.h"
Instruction: fxsave
CPUID Flag: FXSR
Category: OS-Targeted

Description

Save the current state of the x87 FPU, MMX technology, XMM, and MXCSR registers to a 512-byte memory location at "mem_addr". The layout of the 512-byte region depends on the operating mode. Bytes [511:464] are available for software use and will not be overwritten by the processor.

Operation

MEM[mem_addr+512*8:mem_addr] := fxsave(state_x87_fpu_mmx_sse)

Performance

Architecture | Latency | Throughput | μops
Ivy Bridge |  | ~78 |
Haswell |  | ~75 |
Broadwell |  | ~71 |
Skylake |  | ~90 |


_fxsave64

void _fxsave64( void * mem_addr )

Synopsis

#include "immintrin.h"
Instruction: fxsave64
CPUID Flag: FXSR
Category: OS-Targeted

Description

Save the current state of the x87 FPU, MMX technology, XMM, and MXCSR registers to a 512-byte memory location at "mem_addr". The layout of the 512-byte region depends on the operating mode. Bytes [511:464] are available for software use and will not be overwritten by the processor.

Operation

MEM[mem_addr+512*8:mem_addr] := fxsave64(state_x87_fpu_mmx_sse)


_get_ssp

__int32 _get_ssp( void )

Synopsis

#include "immintrin.h"
Instruction: rdsspd
Category: Miscellaneous

Description

If CET is enabled, read the low 32-bits of the current shadow stack pointer, and store the result in "dst". Otherwise return 0.

Operation

dst := SSP[31:0]


_inc_ssp

void _inc_ssp( unsigned int a )

Synopsis

#include "immintrin.h"
Instruction: incsspd
Category: Miscellaneous

Description

Increment the shadow stack pointer by 4 times the value specified in bits [7:0] of "a".

Operation

SSP := SSP + a[7:0] * 4


_incsspd

void _incsspd( int a )

Synopsis

#include "immintrin.h"
Instruction: incsspd
Category: Miscellaneous

Description

Increment the shadow stack pointer by 4 times the value specified in bits [7:0] of "a".

Operation

SSP := SSP + a[7:0] * 4


_incsspq

void _incsspq( int a )

Synopsis

#include "immintrin.h"
Instruction: incsspq
Category: Miscellaneous

Description

Increment the shadow stack pointer by 8 times the value specified in bits [7:0] of "a".

Operation

SSP := SSP + a[7:0] * 8


_invpcid

void _invpcid( unsigned int type, void* descriptor )

Synopsis

#include "immintrin.h"
Instruction: invpcid
CPUID Flag: INVPCID
Category: OS-Targeted

Description

Invalidate mappings in the Translation Lookaside Buffers (TLBs) and paging-structure caches for the processor context identifier (PCID) specified by "descriptor" based on the invalidation type specified in "type". The PCID "descriptor" is specified as a 16-byte memory operand (with no alignment restrictions) where bits [11:0] specify the PCID, and bits [127:64] specify the linear address; bits [63:12] are reserved. The types supported are: 0) Individual-address invalidation: If "type" is 0, the logical processor invalidates mappings for a single linear address and tagged with the PCID specified in "descriptor", except global translations. The instruction may also invalidate global translations, mappings for other linear addresses, or mappings tagged with other PCIDs. 1) Single-context invalidation: If "type" is 1, the logical processor invalidates all mappings tagged with the PCID specified in "descriptor" except global translations. In some cases, it may invalidate mappings for other PCIDs as well. 2) All-context invalidation: If "type" is 2, the logical processor invalidates all mappings tagged with any PCID. 3) All-context invalidation, retaining global translations: If "type" is 3, the logical processor invalidates all mappings tagged with any PCID except global translations, ignoring "descriptor". The instruction may also invalidate global translations as well.

Operation

CASE type OF
0: // individual-address invalidation retaining global translations
    OP_PCID := descriptor[11:0]
    ADDR := descriptor[127:64]
    BREAK
1: // single PCID invalidation retaining globals
    OP_PCID := descriptor[11:0]
    // invalidate all mappings tagged with OP_PCID except global translations
    BREAK
2: // all PCID invalidation
    // invalidate all mappings tagged with any PCID
    BREAK
3: // all PCID invalidation retaining global translations
    // invalidate all mappings tagged with any PCID except global translations
    BREAK
ESAC


_loadbe_i16

short _loadbe_i16( void const * ptr )

Synopsis

#include "immintrin.h"
Instruction: movbe
CPUID Flag: MOVBE
Category: Load

Description

Load 16 bits from memory, perform a byte swap operation, and store the result in "dst".

Operation

addr := MEM[ptr]
FOR j := 0 to 1
    i := j*8
    dst[i+7:i] := addr[15-i:15-i-7]
ENDFOR


_loadbe_i32

int _loadbe_i32( void const * ptr )

Synopsis

#include "immintrin.h"
Instruction: movbe
CPUID Flag: MOVBE
Category: Load

Description

Load 32 bits from memory, perform a byte swap operation, and store the result in "dst".

Operation

addr := MEM[ptr]
FOR j := 0 to 3
    i := j*8
    dst[i+7:i] := addr[31-i:31-i-7]
ENDFOR


_loadbe_i64

__int64 _loadbe_i64( void const * ptr )

Synopsis

#include "immintrin.h"
Instruction: movbe
CPUID Flag: MOVBE
Category: Load

Description

Load 64 bits from memory, perform a byte swap operation, and store the result in "dst".

Operation

addr := MEM[ptr]
FOR j := 0 to 7
    i := j*8
    dst[i+7:i] := addr[63-i:63-i-7]
ENDFOR


_lrotl

unsigned long _lrotl( unsigned long a, int shift )

Synopsis

#include "immintrin.h"
Instruction: rol
Category: Shift

Description

Shift the bits of unsigned long integer "a" left by the number of bits specified in "shift", rotating the most-significant bit to the least-significant bit location, and store the unsigned result in "dst".

Operation

// size := 32 or 64
dst := a
count := shift AND (size - 1)
DO WHILE (count > 0)
    tmp[0] := dst[size - 1]
    dst := (dst << 1) OR tmp[0]
    count := count - 1
OD


_lrotr

unsigned long _lrotr( unsigned long a, int shift )

Synopsis

#include "immintrin.h"
Instruction: ror
Category: Shift

Description

Shift the bits of unsigned long integer "a" right by the number of bits specified in "shift", rotating the least-significant bit to the most-significant bit location, and store the unsigned result in "dst".

Operation

// size := 32 or 64
dst := a
count := shift AND (size - 1)
DO WHILE (count > 0)
    tmp[size - 1] := dst[0]
    dst := (dst >> 1) OR tmp[size - 1]
    count := count - 1
OD


_lzcnt_u32

unsigned int _lzcnt_u32( unsigned int a )

Synopsis

#include "immintrin.h"
Instruction: lzcnt
CPUID Flag: LZCNT
Category: Bit Manipulation

Description

Count the number of leading zero bits in unsigned 32-bit integer "a", and return that count in "dst".

Operation

tmp := 31
dst := 0
DO WHILE (tmp >= 0 AND a[tmp] == 0)
    tmp := tmp - 1
    dst := dst + 1
OD

Performance

Architecture | Latency | Throughput | μops
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 3 | 1 |


_lzcnt_u64

unsigned __int64 _lzcnt_u64( unsigned __int64 a )

Synopsis

#include "immintrin.h"
Instruction: lzcnt
CPUID Flag: LZCNT
Category: Bit Manipulation

Description

Count the number of leading zero bits in unsigned 64-bit integer "a", and return that count in "dst".

Operation

tmp := 63
dst := 0
DO WHILE (tmp >= 0 AND a[tmp] == 0)
    tmp := tmp - 1
    dst := dst + 1
OD

Performance

Architecture | Latency | Throughput | μops
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 3 | 1 |


_m_empty

void _m_empty( void )

Synopsis

#include "mmintrin.h"
Instruction: emms
CPUID Flag: MMX
Category: General Support

Description

Empty the MMX state, which marks the x87 FPU registers as available for use by x87 instructions. This instruction must be used at the end of all MMX technology procedures.

Performance

Architecture | Latency | Throughput | μops
Ryzen |  | 0.25 | 1
Jaguar |  | 0.5 | 1
Sandy Bridge |  | 18 | 31
Ivy Bridge |  | 18 | 31
Haswell |  | 13 | 31
Broadwell |  | 12 | 31
Skylake |  | 6 | 10
Knights Landing |  | 13 | 10


_m_from_int

__m64 _m_from_int( int a )

Synopsis

#include "mmintrin.h"
Instruction: movd
CPUID Flag: MMX
Category: Convert

Description

Copy 32-bit integer "a" to the lower elements of "dst", and zero the upper element of "dst".

Operation

dst[31:0] := a[31:0]
dst[63:32] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 1 | 1
Jaguar | 4 | 1 | 1
Sandy Bridge | 1 |  | 1
Ivy Bridge | 1 | 1 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 2 | 1 | 1
Knights Landing | 4 | 1 | 1


_m_from_int64

__m64 _m_from_int64( __int64 a )

Synopsis

#include "mmintrin.h"
Instruction: movq
CPUID Flag: MMX
Category: Convert

Description

Copy 64-bit integer "a" to "dst".

Operation

dst[63:0] := a[63:0]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.25 | 1
Jaguar | 4 | 1 | 1
Sandy Bridge | 1 |  | 1
Ivy Bridge | 1 | 0.33 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 2 | 1 | 1
Knights Landing | 4 | 1 | 1


_m_maskmovq

void _m_maskmovq( __m64 a, __m64 mask, char* mem_addr )

Synopsis

#include "xmmintrin.h"
Instruction: maskmovq
CPUID Flag: SSE
Category: Store

Description

Conditionally store 8-bit integer elements from "a" into memory using "mask" (elements are not stored when the highest bit is not set in the corresponding element).

Operation

FOR j := 0 to 7
    i := j*8
    IF mask[i+7]
        MEM[mem_addr+i+7:mem_addr+i] := a[i+7:i]
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | ~3000 | ~9 | 30
Jaguar | 432 | 17 | 32
Sandy Bridge |  | 1 | 4
Ivy Bridge |  | 1 | 4
Haswell | 13-413 | 1 | 4
Broadwell | 18-500 | 1 | 4
Skylake | ~450 | 2 | 4
Knights Landing | ~550 | 12 | 6


_m_packssdw

__m64 _m_packssdw( __m64 a, __m64 b )

Synopsis

#include "mmintrin.h"
Instruction: packssdw
CPUID Flag: MMX
Category: Miscellaneous

Description

Convert packed 32-bit integers from "a" and "b" to packed 16-bit integers using signed saturation, and store the results in "dst".

Operation

dst[15:0] := Saturate_Int32_To_Int16 (a[31:0])
dst[31:16] := Saturate_Int32_To_Int16 (a[63:32])
dst[47:32] := Saturate_Int32_To_Int16 (b[31:0])
dst[63:48] := Saturate_Int32_To_Int16 (b[63:32])

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1


_m_packsswb

__m64 _m_packsswb( __m64 a, __m64 b )

Synopsis

#include "mmintrin.h"
Instruction: packsswb
CPUID Flag: MMX
Category: Miscellaneous

Description

Convert packed 16-bit integers from "a" and "b" to packed 8-bit integers using signed saturation, and store the results in "dst".

Operation

dst[7:0] := Saturate_Int16_To_Int8 (a[15:0])
dst[15:8] := Saturate_Int16_To_Int8 (a[31:16])
dst[23:16] := Saturate_Int16_To_Int8 (a[47:32])
dst[31:24] := Saturate_Int16_To_Int8 (a[63:48])
dst[39:32] := Saturate_Int16_To_Int8 (b[15:0])
dst[47:40] := Saturate_Int16_To_Int8 (b[31:16])
dst[55:48] := Saturate_Int16_To_Int8 (b[47:32])
dst[63:56] := Saturate_Int16_To_Int8 (b[63:48])

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1


_m_packuswb

__m64 _m_packuswb( __m64 a, __m64 b )

Synopsis

#include "mmintrin.h"
Instruction: packuswb
CPUID Flag: MMX
Category: Miscellaneous

Description

Convert packed 16-bit integers from "a" and "b" to packed 8-bit integers using unsigned saturation, and store the results in "dst".

Operation

dst[7:0] := Saturate_Int16_To_UnsignedInt8 (a[15:0])
dst[15:8] := Saturate_Int16_To_UnsignedInt8 (a[31:16])
dst[23:16] := Saturate_Int16_To_UnsignedInt8 (a[47:32])
dst[31:24] := Saturate_Int16_To_UnsignedInt8 (a[63:48])
dst[39:32] := Saturate_Int16_To_UnsignedInt8 (b[15:0])
dst[47:40] := Saturate_Int16_To_UnsignedInt8 (b[31:16])
dst[55:48] := Saturate_Int16_To_UnsignedInt8 (b[47:32])
dst[63:56] := Saturate_Int16_To_UnsignedInt8 (b[63:48])

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1


_m_paddb

__m64 _m_paddb( __m64 a, __m64 b )

Synopsis

#include "mmintrin.h"
Instruction: paddb
CPUID Flag: MMX
Category: Arithmetic

Description

Add packed 8-bit integers in "a" and "b", and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*8
    dst[i+7:i] := a[i+7:i] + b[i+7:i]
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.33 | 1
Knights Landing | 2 | 0.5 | 1


_m_paddd

__m64 _m_paddd( __m64 a, __m64 b )

Synopsis

#include "mmintrin.h"
Instruction: paddd
CPUID Flag: MMX
Category: Arithmetic

Description

Add packed 32-bit integers in "a" and "b", and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*32
    dst[i+31:i] := a[i+31:i] + b[i+31:i]
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.33 | 1
Knights Landing | 2 | 0.5 | 1


_m_paddsb

__m64 _m_paddsb( __m64 a, __m64 b )

Synopsis

#include "mmintrin.h"
Instruction: paddsb
CPUID Flag: MMX
Category: Arithmetic

Description

Add packed 8-bit integers in "a" and "b" using saturation, and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*8
    dst[i+7:i] := Saturate_To_Int8( a[i+7:i] + b[i+7:i] )
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.33 | 1
Knights Landing | 2 | 0.5 | 1


_m_paddsw

__m64 _m_paddsw( __m64 a, __m64 b )

Synopsis

#include "mmintrin.h"
Instruction: paddsw
CPUID Flag: MMX
Category: Arithmetic

Description

Add packed 16-bit integers in "a" and "b" using saturation, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*16
    dst[i+15:i] := Saturate_To_Int16( a[i+15:i] + b[i+15:i] )
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.33 | 1
Knights Landing | 2 | 0.5 | 1


_m_paddusb

__m64 _m_paddusb( __m64 a, __m64 b )

Synopsis

#include "mmintrin.h"
Instruction: paddusb
CPUID Flag: MMX
Category: Arithmetic

Description

Add packed unsigned 8-bit integers in "a" and "b" using saturation, and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*8
    dst[i+7:i] := Saturate_To_UnsignedInt8( a[i+7:i] + b[i+7:i] )
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.33 | 1


_m_paddusw

__m64 _m_paddusw( __m64 a, __m64 b )

Synopsis

#include "mmintrin.h"
Instruction: paddusw
CPUID Flag: MMX
Category: Arithmetic

Description

Add packed unsigned 16-bit integers in "a" and "b" using saturation, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*16
    dst[i+15:i] := Saturate_To_UnsignedInt16( a[i+15:i] + b[i+15:i] )
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.33 | 1


_m_paddw

__m64 _m_paddw( __m64 a, __m64 b )

Synopsis

#include "mmintrin.h"
Instruction: paddw
CPUID Flag: MMX
Category: Arithmetic

Description

Add packed 16-bit integers in "a" and "b", and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*16
    dst[i+15:i] := a[i+15:i] + b[i+15:i]
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.33 | 1
Knights Landing | 2 | 0.5 | 1


_m_pand

__m64 _m_pand( __m64 a, __m64 b )

Synopsis

#include "mmintrin.h"
Instruction: pand
CPUID Flag: MMX
Category: Logical

Description

Compute the bitwise AND of 64 bits (representing integer data) in "a" and "b", and store the result in "dst".

Operation

dst[63:0] := (a[63:0] AND b[63:0])

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.25 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 |  | 1
Ivy Bridge | 1 | 0.33 | 1
Haswell | 1 | 0.33 | 1
Broadwell | 1 | 0.33 | 1
Skylake | 1 | 0.33 | 1
Knights Landing | 2 | 0.5 | 1


_m_pandn

__m64 _m_pandn( __m64 a, __m64 b )

Synopsis

#include "mmintrin.h"
Instruction: pandn
CPUID Flag: MMX
Category: Logical

Description

Compute the bitwise NOT of 64 bits (representing integer data) in "a" and then AND with "b", and store the result in "dst".

Operation

dst[63:0] := ((NOT a[63:0]) AND b[63:0])

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.25 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 |  | 1
Ivy Bridge | 1 | 0.33 | 1
Haswell | 1 | 0.33 | 1
Broadwell | 1 | 0.33 | 1
Skylake | 1 | 0.33 | 1
Knights Landing | 2 | 0.5 | 1


_m_pavgb

__m64 _m_pavgb( __m64 a, __m64 b )

Synopsis

#include "xmmintrin.h"
Instruction: pavgb
CPUID Flag: SSE
Category: Probability/Statistics

Description

Average packed unsigned 8-bit integers in "a" and "b", and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*8
    dst[i+7:i] := (a[i+7:i] + b[i+7:i] + 1) >> 1
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1


_m_pavgw

__m64 _m_pavgw( __m64 a, __m64 b )

Synopsis

#include "xmmintrin.h"
Instruction: pavgw
CPUID Flag: SSE
Category: Probability/Statistics

Description

Average packed unsigned 16-bit integers in "a" and "b", and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*16
    dst[i+15:i] := (a[i+15:i] + b[i+15:i] + 1) >> 1
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1


_m_pcmpeqb

__m64 _m_pcmpeqb( __m64 a, __m64 b )

Synopsis

#include "mmintrin.h"
Instruction: pcmpeqb
CPUID Flag: MMX
Category: Compare

Description

Compare packed 8-bit integers in "a" and "b" for equality, and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*8
    dst[i+7:i] := ( a[i+7:i] == b[i+7:i] ) ? 0xFF : 0
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1


_m_pcmpeqd

__m64 _m_pcmpeqd( __m64 a, __m64 b )

Synopsis

#include "mmintrin.h"
Instruction: pcmpeqd
CPUID Flag: MMX
Category: Compare

Description

Compare packed 32-bit integers in "a" and "b" for equality, and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*32
    dst[i+31:i] := ( a[i+31:i] == b[i+31:i] ) ? 0xFFFFFFFF : 0
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1


_m_pcmpeqw

__m64 _m_pcmpeqw( __m64 a, __m64 b )

Synopsis

#include "mmintrin.h"
Instruction: pcmpeqw
CPUID Flag: MMX
Category: Compare

Description

Compare packed 16-bit integers in "a" and "b" for equality, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*16
    dst[i+15:i] := ( a[i+15:i] == b[i+15:i] ) ? 0xFFFF : 0
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1


_m_pcmpgtb

__m64 _m_pcmpgtb( __m64 a, __m64 b )

Synopsis

#include "mmintrin.h"
Instruction: pcmpgtb
CPUID Flag: MMX
Category: Compare

Description

Compare packed 8-bit integers in "a" and "b" for greater-than, and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*8
    dst[i+7:i] := ( a[i+7:i] > b[i+7:i] ) ? 0xFF : 0
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1


_m_pcmpgtd

__m64 _m_pcmpgtd( __m64 a, __m64 b )

Synopsis

#include "mmintrin.h"
Instruction: pcmpgtd
CPUID Flag: MMX
Category: Compare

Description

Compare packed 32-bit integers in "a" and "b" for greater-than, and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*32
    dst[i+31:i] := ( a[i+31:i] > b[i+31:i] ) ? 0xFFFFFFFF : 0
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1


_m_pcmpgtw

__m64 _m_pcmpgtw( __m64 a, __m64 b )

Synopsis

#include "mmintrin.h"
Instruction: pcmpgtw
CPUID Flag: MMX
Category: Compare

Description

Compare packed 16-bit integers in "a" and "b" for greater-than, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*16
    dst[i+15:i] := ( a[i+15:i] > b[i+15:i] ) ? 0xFFFF : 0
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1


_m_pextrw

int _m_pextrw( __m64 a, int imm8 )

Synopsis

#include "xmmintrin.h"
Instruction: pextrw
CPUID Flag: SSE
Category: Swizzle

Description

Extract a 16-bit integer from "a", selected with "imm8", and store the result in the lower element of "dst".

Operation

dst[15:0] := (a[63:0] >> (imm8[1:0] * 16))[15:0]
dst[31:16] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 1 | 2
Jaguar | 4 | 1 | 1
Sandy Bridge | 2 | 1 | 2
Ivy Bridge | 2 | 1 | 2
Haswell | 2 | 1 | 2
Broadwell | 2 | 1 | 2
Skylake | 3 | 1 | 2
Knights Landing | 8 | 7 | 2


_m_pinsrw

__m64 _m_pinsrw( __m64 a, int i, int imm8 )

Synopsis

#include "xmmintrin.h"
Instruction: pinsrw
CPUID Flag: SSE
Category: Swizzle

Description

Copy "a" to "dst", and insert the 16-bit integer "i" into "dst" at the location specified by "imm8".

Operation

dst[63:0] := a[63:0]
sel := imm8[1:0]*16
dst[sel+15:sel] := i[15:0]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 1 | 2
Jaguar | 7 | 1 | 2
Sandy Bridge | 2 | 1 | 2
Ivy Bridge | 2 | 1 | 2
Haswell | 2 | 2 | 2
Broadwell | 2 | 2 | 2
Skylake | 3 | 2 | 2
Knights Landing | 5 | 1 | 1


_m_pmaddwd

__m64 _m_pmaddwd( __m64 a, __m64 b )

Synopsis

#include "mmintrin.h"
Instruction: pmaddwd
CPUID Flag: MMX
Category: Arithmetic

Description

Multiply packed 16-bit integers in "a" and "b", producing intermediate 32-bit integers. Horizontally add adjacent pairs of intermediate 32-bit integers, and pack the results in "dst".

Operation

FOR j := 0 to 1
    i := j*32
    dst[i+31:i] := a[i+31:i+16]*b[i+31:i+16] + a[i+15:i]*b[i+15:i]
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 1 | 1
Jaguar | 2 | 1 | 1
Sandy Bridge | 5 | 1 | 1
Ivy Bridge | 5 | 1 | 1
Haswell | 5 | 1 | 1
Broadwell | 5 | 1 | 1
Skylake | 5 | 0.5 | 1
Knights Landing | 7 | 2 | 1


_m_pmaxsw

__m64 _m_pmaxsw( __m64 a, __m64 b )

Synopsis

#include "xmmintrin.h"
Instruction: pmaxsw
CPUID Flag: SSE
Category: Special Math Functions

Description

Compare packed 16-bit integers in "a" and "b", and store packed maximum values in "dst".

Operation

FOR j := 0 to 3
    i := j*16
    IF a[i+15:i] > b[i+15:i]
        dst[i+15:i] := a[i+15:i]
    ELSE
        dst[i+15:i] := b[i+15:i]
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.5 | 1
Knights Landing | 2 | 2 | 1


_m_pmaxub

__m64 _m_pmaxub( __m64 a, __m64 b )

Synopsis

#include "xmmintrin.h"
Instruction: pmaxub
CPUID Flag: SSE
Category: Special Math Functions

Description

Compare packed unsigned 8-bit integers in "a" and "b", and store packed maximum values in "dst".

Operation

FOR j := 0 to 7
    i := j*8
    IF a[i+7:i] > b[i+7:i]
        dst[i+7:i] := a[i+7:i]
    ELSE
        dst[i+7:i] := b[i+7:i]
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.5 | 1
Knights Landing | 2 | 2 | 1


_m_pminsw

__m64 _m_pminsw( __m64 a, __m64 b )

Synopsis

#include "xmmintrin.h"
Instruction: pminsw
CPUID Flag: SSE
Category: Special Math Functions

Description

Compare packed 16-bit integers in "a" and "b", and store packed minimum values in "dst".

Operation

FOR j := 0 to 3
    i := j*16
    IF a[i+15:i] < b[i+15:i]
        dst[i+15:i] := a[i+15:i]
    ELSE
        dst[i+15:i] := b[i+15:i]
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.5 | 1
Knights Landing | 2 | 2 | 1


_m_pminub

__m64 _m_pminub( __m64 a, __m64 b )

Synopsis

#include "xmmintrin.h"
Instruction: pminub
CPUID Flag: SSE
Category: Special Math Functions

Description

Compare packed unsigned 8-bit integers in "a" and "b", and store packed minimum values in "dst".

Operation

FOR j := 0 to 7
    i := j*8
    IF a[i+7:i] < b[i+7:i]
        dst[i+7:i] := a[i+7:i]
    ELSE
        dst[i+7:i] := b[i+7:i]
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.5 | 1
Knights Landing | 2 | 2 | 1


_m_pmovmskb

int _m_pmovmskb( __m64 a )

Synopsis

#include "xmmintrin.h"
Instruction: pmovmskb
CPUID Flag: SSE
Category: Miscellaneous

Description

Create mask from the most significant bit of each 8-bit element in "a", and store the result in "dst".

Operation

FOR j := 0 to 7
    i := j*8
    dst[j] := a[i+7]
ENDFOR
dst[MAX:8] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 1 | 1
Jaguar | 3 | 1 | 1
Sandy Bridge | 2 | 1 | 1
Ivy Bridge | 2 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 2-3 | 1 | 1
Knights Landing | 26 | 12 | 12


_m_pmulhuw

__m64 _m_pmulhuw( __m64 a, __m64 b )

Synopsis

#include "xmmintrin.h"
Instruction: pmulhuw
CPUID Flag: SSE
Category: Arithmetic

Description

Multiply the packed unsigned 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst".

Operation

FOR j := 0 to 3
    i := j*16
    tmp[31:0] := a[i+15:i] * b[i+15:i]
    dst[i+15:i] := tmp[31:16]
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 1 | 1
Jaguar | 2 | 1 | 1
Sandy Bridge | 5 | 1 | 1
Ivy Bridge | 5 | 1 | 1
Haswell | 5 | 1 | 1
Broadwell | 5 | 1 | 1
Skylake | 5 | 0.5 | 1
Knights Landing | 7 | 2 | 1


_m_pmulhw

__m64 _m_pmulhw( __m64 a, __m64 b )

Synopsis

#include "mmintrin.h"
Instruction: pmulhw
CPUID Flag: MMX
Category: Arithmetic

Description

Multiply the packed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst".

Operation

FOR j := 0 to 3
    i := j*16
    tmp[31:0] := a[i+15:i] * b[i+15:i]
    dst[i+15:i] := tmp[31:16]
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 1 | 1
Jaguar | 2 | 1 | 1
Sandy Bridge | 5 | 1 | 1
Ivy Bridge | 5 | 1 | 1
Haswell | 5 | 1 | 1
Broadwell | 5 | 1 | 1
Skylake | 5 | 0.5 | 1
Knights Landing | 7 | 2 | 1


_m_pmullw

__m64 _m_pmullw( __m64 a, __m64 b )

Synopsis

#include "mmintrin.h"
Instruction: pmullw
CPUID Flag: MMX
Category: Arithmetic

Description

Multiply the packed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the low 16 bits of the intermediate integers in "dst".

Operation

FOR j := 0 to 3
    i := j*16
    tmp[31:0] := a[i+15:i] * b[i+15:i]
    dst[i+15:i] := tmp[15:0]
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 1 | 1
Jaguar | 2 | 1 | 1
Sandy Bridge | 5 | 1 | 1
Ivy Bridge | 5 | 1 | 1
Haswell | 5 | 1 | 1
Broadwell | 5 | 1 | 1
Skylake | 5 | 0.5 | 1
Knights Landing | 7 | 2 | 1


_m_por

__m64 _m_por( __m64 a, __m64 b )

Synopsis

#include "mmintrin.h"
Instruction: por
CPUID Flag: MMX
Category: Logical

Description

Compute the bitwise OR of 64 bits (representing integer data) in "a" and "b", and store the result in "dst".

Operation

dst[63:0] := (a[63:0] OR b[63:0])

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.25 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 |  | 1
Ivy Bridge | 1 | 0.33 | 1
Haswell | 1 | 0.33 | 1
Broadwell | 1 | 0.33 | 1
Skylake | 1 | 0.33 | 1
Knights Landing | 2 | 0.5 | 1


_m_psadbw

__m64 _m_psadbw( __m64 a, __m64 b )

Synopsis

#include "xmmintrin.h"
Instruction: psadbw
CPUID Flag: SSE
Category: Arithmetic

Description

Compute the absolute differences of packed unsigned 8-bit integers in "a" and "b", then horizontally sum each consecutive 8 differences to produce four unsigned 16-bit integers, and pack these unsigned 16-bit integers in the low 16 bits of "dst".

Operation

FOR j := 0 to 7
    i := j*8
    tmp[i+7:i] := ABS(a[i+7:i] - b[i+7:i])
ENDFOR
dst[15:0] := tmp[7:0] + tmp[15:8] + tmp[23:16] + tmp[31:24] + tmp[39:32] + tmp[47:40] + tmp[55:48] + tmp[63:56]
dst[63:16] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 1 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 5 | 1 | 1
Ivy Bridge | 5 | 1 | 1
Haswell | 5 | 1 | 1
Broadwell | 5 | 1 | 1
Skylake | 3 | 1 | 1
Knights Landing | 16 | 9 | 5


_m_pshufw

__m64 _m_pshufw( __m64 a, int imm8 )

Synopsis

#include "xmmintrin.h"
Instruction: pshufw
CPUID Flag: SSE
Category: Swizzle

Description

Shuffle 16-bit integers in "a" using the control in "imm8", and store the results in "dst".

Operation

DEFINE SELECT4(src, control) {
    CASE(control[1:0]) OF
    0:	tmp[15:0] := src[15:0]
    1:	tmp[15:0] := src[31:16]
    2:	tmp[15:0] := src[47:32]
    3:	tmp[15:0] := src[63:48]
    ESAC
    RETURN tmp[15:0]
}
dst[15:0] := SELECT4(a[63:0], imm8[1:0])
dst[31:16] := SELECT4(a[63:0], imm8[3:2])
dst[47:32] := SELECT4(a[63:0], imm8[5:4])
dst[63:48] := SELECT4(a[63:0], imm8[7:6])

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 2-6 | 1 | 1


_m_pslld

__m64 _m_pslld( __m64 a, __m64 count )

Synopsis

#include "mmintrin.h"
Instruction: pslld
CPUID Flag: MMX
Category: Shift

Description

Shift packed 32-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*32
    IF count[63:0] > 31
        dst[i+31:i] := 0
    ELSE
        dst[i+31:i] := ZeroExtend(a[i+31:i] << count[63:0])
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 1 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 2 | 1 | 2
Ivy Bridge | 2 | 1 | 2
Haswell | 2 | 1 | 2
Broadwell | 2 | 1 | 2
Skylake | 1 | 1 | 2
Knights Landing | 13 | 13 | 2


_m_pslldi

__m64 _m_pslldi( __m64 a, int imm8 )

Synopsis

#include "mmintrin.h"
Instruction: pslld
CPUID Flag: MMX
Category: Shift

Description

Shift packed 32-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*32
    IF imm8[7:0] > 31
        dst[i+31:i] := 0
    ELSE
        dst[i+31:i] := ZeroExtend(a[i+31:i] << imm8[7:0])
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 1 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 2 | 1 | 2
Ivy Bridge | 2 | 1 | 2
Haswell | 2 | 1 | 2
Broadwell | 2 | 1 | 2
Skylake | 1 | 1 | 2
Knights Landing | 13 | 13 | 2


_m_psllq

__m64 _m_psllq( __m64 a, __m64 count )

Synopsis

#include "mmintrin.h"
Instruction: psllq
CPUID Flag: MMX
Category: Shift

Description

Shift 64-bit integer "a" left by "count" while shifting in zeros, and store the result in "dst".

Operation

IF count[63:0] > 63
    dst[63:0] := 0
ELSE
    dst[63:0] := ZeroExtend(a[63:0] << count[63:0])
FI

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 1 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 2 | 1 | 2
Ivy Bridge | 2 | 1 | 2
Haswell | 2 | 1 | 2
Broadwell | 2 | 1 | 2
Skylake | 1 | 1 | 2
Knights Landing | 13 | 13 | 2


_m_psllqi

__m64 _m_psllqi( __m64 a, int imm8 )

Synopsis

#include "mmintrin.h"
Instruction: psllq
CPUID Flag: MMX
Category: Shift

Description

Shift 64-bit integer "a" left by "imm8" while shifting in zeros, and store the result in "dst".

Operation

IF imm8[7:0] > 63
    dst[63:0] := 0
ELSE
    dst[63:0] := ZeroExtend(a[63:0] << imm8[7:0])
FI

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 1 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 2 | 1 | 2
Ivy Bridge | 2 | 1 | 2
Haswell | 2 | 1 | 2
Broadwell | 2 | 1 | 2
Skylake | 1 | 1 | 2
Knights Landing | 13 | 13 | 2


_m_psllw

__m64 _m_psllw( __m64 a, __m64 count )

Synopsis

#include "mmintrin.h"
Instruction: psllw
CPUID Flag: MMX
Category: Shift

Description

Shift packed 16-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*16
    IF count[63:0] > 15
        dst[i+15:i] := 0
    ELSE
        dst[i+15:i] := ZeroExtend(a[i+15:i] << count[63:0])
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 1 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 2 | 1 | 2
Ivy Bridge | 2 | 1 | 2
Haswell | 2 | 1 | 2
Broadwell | 2 | 1 | 2
Skylake | 1 | 1 | 2
Knights Landing | 13 | 13 | 2


_m_psllwi

__m64 _m_psllwi( __m64 a, int imm8 )

Synopsis

#include "mmintrin.h"
Instruction: psllw
CPUID Flag: MMX
Category: Shift

Description

Shift packed 16-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*16
    IF imm8[7:0] > 15
        dst[i+15:i] := 0
    ELSE
        dst[i+15:i] := ZeroExtend(a[i+15:i] << imm8[7:0])
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 1 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 2 | 1 | 2
Ivy Bridge | 2 | 1 | 2
Haswell | 2 | 1 | 2
Broadwell | 2 | 1 | 2
Skylake | 1 | 1 | 2
Knights Landing | 13 | 13 | 2


_m_psrad

__m64 _m_psrad( __m64 a, __m64 count )

Synopsis

#include "mmintrin.h"
Instruction: psrad
CPUID Flag: MMX
Category: Shift

Description

Shift packed 32-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*32
    IF count[63:0] > 31
        dst[i+31:i] := SignBit
    ELSE
        dst[i+31:i] := SignExtend(a[i+31:i] >> count[63:0])
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 1 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 2 | 1 | 2
Ivy Bridge | 2 | 1 | 2
Haswell | 2 | 1 | 2
Broadwell | 2 | 1 | 2
Skylake | 1 | 1 | 2
Knights Landing | 13 | 13 | 2


_m_psradi

__m64 _m_psradi( __m64 a, int imm8 )

Synopsis

#include "mmintrin.h"
Instruction: psrad
CPUID Flag: MMX
Category: Shift

Description

Shift packed 32-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*32
    IF imm8[7:0] > 31
        dst[i+31:i] := SignBit
    ELSE
        dst[i+31:i] := SignExtend(a[i+31:i] >> imm8[7:0])
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 1 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 2 | 1 | 2
Ivy Bridge | 2 | 1 | 2
Haswell | 2 | 1 | 2
Broadwell | 2 | 1 | 2
Skylake | 1 | 1 | 2
Knights Landing | 13 | 13 | 2


_m_psraw

__m64 _m_psraw( __m64 a, __m64 count )

Synopsis

#include "mmintrin.h"
Instruction: psraw
CPUID Flag: MMX
Category: Shift

Description

Shift packed 16-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*16
    IF count[63:0] > 15
        dst[i+15:i] := SignBit
    ELSE
        dst[i+15:i] := SignExtend(a[i+15:i] >> count[63:0])
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 1 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 2 | 1 | 2
Ivy Bridge | 2 | 1 | 2
Haswell | 2 | 1 | 2
Broadwell | 2 | 1 | 2
Skylake | 1 | 1 | 2
Knights Landing | 13 | 13 | 2


_m_psrawi

__m64 _m_psrawi( __m64 a, int imm8 )

Synopsis

#include "mmintrin.h"
Instruction: psraw
CPUID Flag: MMX
Category: Shift

Description

Shift packed 16-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*16
    IF imm8[7:0] > 15
        dst[i+15:i] := SignBit
    ELSE
        dst[i+15:i] := SignExtend(a[i+15:i] >> imm8[7:0])
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 1 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 2 | 1 | 2
Ivy Bridge | 2 | 1 | 2
Haswell | 2 | 1 | 2
Broadwell | 2 | 1 | 2
Skylake | 1 | 1 | 2
Knights Landing | 13 | 13 | 2


_m_psrld

__m64 _m_psrld( __m64 a, __m64 count )

Synopsis

#include "mmintrin.h"
Instruction: psrld
CPUID Flag: MMX
Category: Shift

Description

Shift packed 32-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*32
    IF count[63:0] > 31
        dst[i+31:i] := 0
    ELSE
        dst[i+31:i] := ZeroExtend(a[i+31:i] >> count[63:0])
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 1 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 2 | 1 | 2
Ivy Bridge | 2 | 1 | 2
Haswell | 2 | 1 | 2
Broadwell | 2 | 1 | 2
Skylake | 1 | 1 | 2
Knights Landing | 13 | 13 | 2


_m_psrldi

__m64 _m_psrldi( __m64 a, int imm8 )

Synopsis

#include "mmintrin.h"
Instruction: psrld
CPUID Flag: MMX
Category: Shift

Description

Shift packed 32-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*32
    IF imm8[7:0] > 31
        dst[i+31:i] := 0
    ELSE
        dst[i+31:i] := ZeroExtend(a[i+31:i] >> imm8[7:0])
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 1 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 2 | 1 | 2
Ivy Bridge | 2 | 1 | 2
Haswell | 2 | 1 | 2
Broadwell | 2 | 1 | 2
Skylake | 1 | 1 | 2
Knights Landing | 13 | 13 | 2


_m_psrlq

__m64 _m_psrlq( __m64 a, __m64 count )

Synopsis

#include "mmintrin.h"
Instruction: psrlq
CPUID Flag: MMX
Category: Shift

Description

Shift 64-bit integer "a" right by "count" while shifting in zeros, and store the result in "dst".

Operation

IF count[63:0] > 63
    dst[63:0] := 0
ELSE
    dst[63:0] := ZeroExtend(a[63:0] >> count[63:0])
FI

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 1 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 2 | 1 | 2
Ivy Bridge | 2 | 1 | 2
Haswell | 2 | 1 | 2
Broadwell | 2 | 1 | 2
Skylake | 1 | 1 | 2
Knights Landing | 13 | 13 | 2


_m_psrlqi

__m64 _m_psrlqi( __m64 a, int imm8 )

Synopsis

#include "mmintrin.h"
Instruction: psrlq
CPUID Flag: MMX
Category: Shift

Description

Shift 64-bit integer "a" right by "imm8" while shifting in zeros, and store the result in "dst".

Operation

IF imm8[7:0] > 63
    dst[63:0] := 0
ELSE
    dst[63:0] := ZeroExtend(a[63:0] >> imm8[7:0])
FI

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 1 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 2 | 1 | 2
Ivy Bridge | 2 | 1 | 2
Haswell | 2 | 1 | 2
Broadwell | 2 | 1 | 2
Skylake | 1 | 1 | 2
Knights Landing | 13 | 13 | 2


_m_psrlw

__m64 _m_psrlw( __m64 a, __m64 count )

Synopsis

#include "mmintrin.h"
Instruction: psrlw
CPUID Flag: MMX
Category: Shift

Description

Shift packed 16-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*16
    IF count[63:0] > 15
        dst[i+15:i] := 0
    ELSE
        dst[i+15:i] := ZeroExtend(a[i+15:i] >> count[63:0])
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 1 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 2 | 1 | 2
Ivy Bridge | 2 | 1 | 2
Haswell | 2 | 1 | 2
Broadwell | 2 | 1 | 2
Skylake | 1 | 1 | 2
Knights Landing | 13 | 13 | 2


_m_psrlwi

__m64 _m_psrlwi( __m64 a, int imm8 )

Synopsis

#include "mmintrin.h"
Instruction: psrlw
CPUID Flag: MMX
Category: Shift

Description

Shift packed 16-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*16
    IF imm8[7:0] > 15
        dst[i+15:i] := 0
    ELSE
        dst[i+15:i] := ZeroExtend(a[i+15:i] >> imm8[7:0])
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 1 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 2 | 1 | 2
Ivy Bridge | 2 | 1 | 2
Haswell | 2 | 1 | 2
Broadwell | 2 | 1 | 2
Skylake | 1 | 1 | 2
Knights Landing | 13 | 13 | 2


_m_psubb

__m64 _m_psubb( __m64 a, __m64 b )

Synopsis

#include "mmintrin.h"
Instruction: psubb
CPUID Flag: MMX
Category: Arithmetic

Description

Subtract packed 8-bit integers in "b" from packed 8-bit integers in "a", and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*8
    dst[i+7:i] := a[i+7:i] - b[i+7:i]
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.33 | 1
Knights Landing | 2 | 0.5 | 1


_m_psubd

__m64 _m_psubd( __m64 a, __m64 b )

Synopsis

#include "mmintrin.h"
Instruction: psubd
CPUID Flag: MMX
Category: Arithmetic

Description

Subtract packed 32-bit integers in "b" from packed 32-bit integers in "a", and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*32
    dst[i+31:i] := a[i+31:i] - b[i+31:i]
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.33 | 1
Knights Landing | 2 | 0.5 | 1


_m_psubsb

__m64 _m_psubsb( __m64 a, __m64 b )

Synopsis

#include "mmintrin.h"
Instruction: psubsb
CPUID Flag: MMX
Category: Arithmetic

Description

Subtract packed 8-bit integers in "b" from packed 8-bit integers in "a" using saturation, and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*8
    dst[i+7:i] := Saturate_To_Int8(a[i+7:i] - b[i+7:i])
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.33 | 1
Knights Landing | 2 | 0.5 | 1


_m_psubsw

__m64 _m_psubsw( __m64 a, __m64 b )

Synopsis

#include "mmintrin.h"
Instruction: psubsw
CPUID Flag: MMX
Category: Arithmetic

Description

Subtract packed 16-bit integers in "b" from packed 16-bit integers in "a" using saturation, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*16
    dst[i+15:i] := Saturate_To_Int16(a[i+15:i] - b[i+15:i])
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.33 | 1
Knights Landing | 2 | 0.5 | 1


_m_psubusb

__m64 _m_psubusb( __m64 a, __m64 b )

Synopsis

#include "mmintrin.h"
Instruction: psubusb
CPUID Flag: MMX
Category: Arithmetic

Description

Subtract packed unsigned 8-bit integers in "b" from packed unsigned 8-bit integers in "a" using saturation, and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*8
    dst[i+7:i] := Saturate_To_UnsignedInt8(a[i+7:i] - b[i+7:i])
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Jaguar | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.33 | 1


_m_psubusw

__m64 _m_psubusw( __m64 a, __m64 b )

Synopsis

#include "mmintrin.h"
Instruction: psubusw
CPUID Flag: MMX
Category: Arithmetic

Description

Subtract packed unsigned 16-bit integers in "b" from packed unsigned 16-bit integers in "a" using saturation, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*16
    dst[i+15:i] := Saturate_To_UnsignedInt16(a[i+15:i] - b[i+15:i])
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Jaguar | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.33 | 1


_m_psubw

__m64 _m_psubw( __m64 a, __m64 b )

Synopsis

#include "mmintrin.h"
Instruction: psubw
CPUID Flag: MMX
Category: Arithmetic

Description

Subtract packed 16-bit integers in "b" from packed 16-bit integers in "a", and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*16
    dst[i+15:i] := a[i+15:i] - b[i+15:i]
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.33 | 1
Knights Landing | 2 | 0.5 | 1


_m_punpckhbw

__m64 _m_punpckhbw( __m64 a, __m64 b )

Synopsis

#include "mmintrin.h"
Instruction: punpckhbw
CPUID Flag: MMX
Category: Swizzle

Description

Unpack and interleave 8-bit integers from the high half of "a" and "b", and store the results in "dst".

Operation

DEFINE INTERLEAVE_HIGH_BYTES(src1[63:0], src2[63:0]) {
    dst[7:0] := src1[39:32]
    dst[15:8] := src2[39:32]
    dst[23:16] := src1[47:40]
    dst[31:24] := src2[47:40]
    dst[39:32] := src1[55:48]
    dst[47:40] := src2[55:48]
    dst[55:48] := src1[63:56]
    dst[63:56] := src2[63:56]
    RETURN dst[63:0]
}
dst[63:0] := INTERLEAVE_HIGH_BYTES(a[63:0], b[63:0])

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 2-6 | 1 | 1


_m_punpckhdq

__m64 _m_punpckhdq( __m64 a, __m64 b )

Synopsis

#include "mmintrin.h"
Instruction: punpckhdq
CPUID Flag: MMX
Category: Swizzle

Description

Unpack and interleave 32-bit integers from the high half of "a" and "b", and store the results in "dst".

Operation

dst[31:0] := a[63:32]
dst[63:32] := b[63:32]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 2-6 | 1 | 1


_m_punpckhwd

__m64 _m_punpckhwd( __m64 a, __m64 b )

Synopsis

#include "mmintrin.h"
Instruction: punpcklbw
CPUID Flag: MMX
Category: Swizzle

Description

Unpack and interleave 16-bit integers from the high half of "a" and "b", and store the results in "dst".

Operation

DEFINE INTERLEAVE_HIGH_WORDS(src1[63:0], src2[63:0]) {
    dst[15:0] := src1[47:32]
    dst[31:16] := src2[47:32]
    dst[47:32] := src1[63:48]
    dst[63:48] := src2[63:48]
    RETURN dst[63:0]
}
dst[63:0] := INTERLEAVE_HIGH_WORDS(a[63:0], b[63:0])

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 2-6 | 1 | 1


_m_punpcklbw

__m64 _m_punpcklbw( __m64 a, __m64 b )

Synopsis

#include "mmintrin.h"
Instruction: punpcklbw
CPUID Flag: MMX
Category: Swizzle

Description

Unpack and interleave 8-bit integers from the low half of "a" and "b", and store the results in "dst".

Operation

DEFINE INTERLEAVE_BYTES(src1[63:0], src2[63:0]) {
    dst[7:0] := src1[7:0]
    dst[15:8] := src2[7:0]
    dst[23:16] := src1[15:8]
    dst[31:24] := src2[15:8]
    dst[39:32] := src1[23:16]
    dst[47:40] := src2[23:16]
    dst[55:48] := src1[31:24]
    dst[63:56] := src2[31:24]
    RETURN dst[63:0]
}
dst[63:0] := INTERLEAVE_BYTES(a[63:0], b[63:0])

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 2-6 | 1 | 1


_m_punpckldq

__m64 _m_punpckldq( __m64 a, __m64 b )

Synopsis

#include "mmintrin.h"
Instruction: punpckldq
CPUID Flag: MMX
Category: Swizzle

Description

Unpack and interleave 32-bit integers from the low half of "a" and "b", and store the results in "dst".

Operation

dst[31:0] := a[31:0]
dst[63:32] := b[31:0]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 2-6 | 1 | 1


_m_punpcklwd

__m64 _m_punpcklwd( __m64 a, __m64 b )

Synopsis

#include "mmintrin.h"
Instruction: punpcklwd
CPUID Flag: MMX
Category: Swizzle

Description

Unpack and interleave 16-bit integers from the low half of "a" and "b", and store the results in "dst".

Operation

DEFINE INTERLEAVE_WORDS(src1[63:0], src2[63:0]) {
    dst[15:0] := src1[15:0]
    dst[31:16] := src2[15:0]
    dst[47:32] := src1[31:16]
    dst[63:48] := src2[31:16]
    RETURN dst[63:0]
}
dst[63:0] := INTERLEAVE_WORDS(a[63:0], b[63:0])

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 2-6 | 1 | 1


_m_pxor

__m64 _m_pxor( __m64 a, __m64 b )

Synopsis

#include "mmintrin.h"
Instruction: pxor
CPUID Flag: MMX
Category: Logical

Description

Compute the bitwise OR of 64 bits (representing integer data) in "a" and "b", and store the result in "dst".

Operation

dst[63:0] := (a[63:0] XOR b[63:0])

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.25 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 |  | 1
Ivy Bridge | 1 | 0.33 | 1
Haswell | 1 | 0.33 | 1
Broadwell | 1 | 0.33 | 1
Skylake | 1 | 0.33 | 1
Knights Landing | 2 | 0.5 | 1


_m_to_int

int _m_to_int( __m64 a )

Synopsis

#include "mmintrin.h"
Instruction: movd
CPUID Flag: MMX
Category: Convert

Description

Copy the lower 32-bit integer in "a" to "dst".

Operation

dst[31:0] := a[31:0]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 1 | 1
Jaguar | 4 | 1 | 1
Sandy Bridge | 1 |  | 1
Ivy Bridge | 1 | 1 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 2 | 1 | 1
Knights Landing | 4 | 1 | 1


_m_to_int64

__int64 _m_to_int64( __m64 a )

Synopsis

#include "mmintrin.h"
Instruction: movq
CPUID Flag: MMX
Category: Convert

Description

Copy 64-bit integer "a" to "dst".

Operation

dst[63:0] := a[63:0]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.25 | 1
Jaguar | 4 | 1 | 1
Sandy Bridge | 1 |  | 1
Ivy Bridge | 1 | 0.33 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 2 | 1 | 1
Knights Landing | 4 | 1 | 1


_may_i_use_cpu_feature

int _may_i_use_cpu_feature( unsigned __int64 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
Category: General Support

Description

Dynamically query the processor to determine if the processor-specific feature(s) specified in "a" are available, and return true or false (1 or 0) if the set of features is available. Multiple features may be OR'd together. This intrinsic does not check the processor vendor. See the valid feature flags below:

Operation

_FEATURE_GENERIC_IA32
_FEATURE_FPU
_FEATURE_CMOV
_FEATURE_MMX
_FEATURE_FXSAVE
_FEATURE_SSE
_FEATURE_SSE2
_FEATURE_SSE3
_FEATURE_SSSE3
_FEATURE_SSE4_1
_FEATURE_SSE4_2
_FEATURE_MOVBE
_FEATURE_POPCNT
_FEATURE_PCLMULQDQ
_FEATURE_AES
_FEATURE_F16C
_FEATURE_AVX
_FEATURE_RDRND
_FEATURE_FMA
_FEATURE_BMI
_FEATURE_LZCNT
_FEATURE_HLE
_FEATURE_RTM
_FEATURE_AVX2
_FEATURE_KNCNI
_FEATURE_AVX512F
_FEATURE_ADX
_FEATURE_RDSEED
_FEATURE_AVX512ER
_FEATURE_AVX512PF
_FEATURE_AVX512CD
_FEATURE_SHA
_FEATURE_MPX
_FEATURE_AVX512BW
_FEATURE_AVX512VL
_FEATURE_AVX512VBMI
_FEATURE_AVX512_4FMAPS
_FEATURE_AVX512_4VNNIW
_FEATURE_AVX512_VPOPCNTDQ
_FEATURE_AVX512_BITALG
_FEATURE_AVX512_VBMI2
_FEATURE_GFNI
_FEATURE_VAES
_FEATURE_VPCLMULQDQ
_FEATURE_AVX512_VNNI
_FEATURE_CLWB
_FEATURE_RDPID
_FEATURE_IBT
_FEATURE_SHSTK
_FEATURE_SGX
_FEATURE_WBNOINVD
_FEATURE_PCONFIG


_mm_abs_epi16

__m128i _mm_abs_epi16( __m128i a )

Synopsis

#include "tmmintrin.h"
Instruction: pabsw
CPUID Flag: SSSE3
Category: Special Math Functions

Description

Compute the absolute value of packed 16-bit integers in "a", and store the unsigned results in "dst".

Operation

FOR j := 0 to 7
    i := j*16
    dst[i+15:i] := ABS(a[i+15:i])
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.5 | 1
Knights Landing | 2 | 2 | 1
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.5 |


_mm_abs_epi32

__m128i _mm_abs_epi32( __m128i a )

Synopsis

#include "tmmintrin.h"
Instruction: pabsd
CPUID Flag: SSSE3
Category: Special Math Functions

Description

Compute the absolute value of packed 32-bit integers in "a", and store the unsigned results in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := ABS(a[i+31:i])
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.5 | 1
Knights Landing | 2 | 2 | 1
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.5 |


_mm_abs_epi8

__m128i _mm_abs_epi8( __m128i a )

Synopsis

#include "tmmintrin.h"
Instruction: pabsb
CPUID Flag: SSSE3
Category: Special Math Functions

Description

Compute the absolute value of packed 8-bit integers in "a", and store the unsigned results in "dst".

Operation

FOR j := 0 to 15
    i := j*8
    dst[i+7:i] := ABS(a[i+7:i])
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.5 | 1
Knights Landing | 2 | 2 | 1
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.5 |


_mm_abs_pi16

__m64 _mm_abs_pi16( __m64 a )

Synopsis

#include "tmmintrin.h"
Instruction: pabsw
CPUID Flag: SSSE3
Category: Special Math Functions

Description

Compute the absolute value of packed 16-bit integers in "a", and store the unsigned results in "dst".

Operation

FOR j := 0 to 3
    i := j*16
    dst[i+15:i] := ABS(a[i+15:i])
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.5 | 1
Knights Landing | 2 | 2 | 1
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.5 |


_mm_abs_pi32

__m64 _mm_abs_pi32( __m64 a )

Synopsis

#include "tmmintrin.h"
Instruction: pabsd
CPUID Flag: SSSE3
Category: Special Math Functions

Description

Compute the absolute value of packed 32-bit integers in "a", and store the unsigned results in "dst".

Operation

FOR j := 0 to 1
    i := j*32
    dst[i+31:i] := ABS(a[i+31:i])
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.5 | 1
Knights Landing | 2 | 2 | 1
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.5 |


_mm_abs_pi8

__m64 _mm_abs_pi8( __m64 a )

Synopsis

#include "tmmintrin.h"
Instruction: pabsb
CPUID Flag: SSSE3
Category: Special Math Functions

Description

Compute the absolute value of packed 8-bit integers in "a", and store the unsigned results in "dst".

Operation

FOR j := 0 to 7
    i := j*8
    dst[i+7:i] := ABS(a[i+7:i])
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.5 | 1
Knights Landing | 2 | 2 | 1
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.5 |


_mm_acos_pd

__m128d _mm_acos_pd( __m128d a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Trigonometry

Description

Compute the inverse cosine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*64
    dst[i+63:i] := ACOS(a[i+63:i])
ENDFOR
dst[MAX:128] := 0


_mm_acos_ps

__m128 _mm_acos_ps( __m128 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Trigonometry

Description

Compute the inverse cosine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := ACOS(a[i+31:i])
ENDFOR
dst[MAX:128] := 0


_mm_acosh_pd

__m128d _mm_acosh_pd( __m128d a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Trigonometry

Description

Compute the inverse hyperbolic cosine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*64
    dst[i+63:i] := ACOSH(a[i+63:i])
ENDFOR
dst[MAX:128] := 0


_mm_acosh_ps

__m128 _mm_acosh_ps( __m128 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Trigonometry

Description

Compute the inverse hyperbolic cosine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := ACOSH(a[i+31:i])
ENDFOR
dst[MAX:128] := 0


_mm_add_epi16

__m128i _mm_add_epi16( __m128i a, __m128i b )

Synopsis

#include "emmintrin.h"
Instruction: paddw
CPUID Flag: SSE2
Category: Arithmetic

Description

Add packed 16-bit integers in "a" and "b", and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*16
    dst[i+15:i] := a[i+15:i] + b[i+15:i]
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.33 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.33 |


_mm_add_epi32

__m128i _mm_add_epi32( __m128i a, __m128i b )

Synopsis

#include "emmintrin.h"
Instruction: paddd
CPUID Flag: SSE2
Category: Arithmetic

Description

Add packed 32-bit integers in "a" and "b", and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := a[i+31:i] + b[i+31:i]
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.33 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.33 |


_mm_add_epi64

__m128i _mm_add_epi64( __m128i a, __m128i b )

Synopsis

#include "emmintrin.h"
Instruction: paddq
CPUID Flag: SSE2
Category: Arithmetic

Description

Add packed 64-bit integers in "a" and "b", and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*64
    dst[i+63:i] := a[i+63:i] + b[i+63:i]
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.33 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.33 |


_mm_add_epi8

__m128i _mm_add_epi8( __m128i a, __m128i b )

Synopsis

#include "emmintrin.h"
Instruction: paddb
CPUID Flag: SSE2
Category: Arithmetic

Description

Add packed 8-bit integers in "a" and "b", and store the results in "dst".

Operation

FOR j := 0 to 15
    i := j*8
    dst[i+7:i] := a[i+7:i] + b[i+7:i]
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.33 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.33 |


_mm_add_pd

__m128d _mm_add_pd( __m128d a, __m128d b )

Synopsis

#include "emmintrin.h"
Instruction: addpd
CPUID Flag: SSE2
Category: Arithmetic

Description

Add packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*64
    dst[i+63:i] := a[i+63:i] + b[i+63:i]
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 0.5 | 1
Jaguar | 3 | 1 | 1
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 4 | 0.5 | 1
Knights Landing | 6 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 4 | 0.5 |


_mm_add_pi16

__m64 _mm_add_pi16( __m64 a, __m64 b )

Synopsis

#include "mmintrin.h"
Instruction: paddw
CPUID Flag: MMX
Category: Arithmetic

Description

Add packed 16-bit integers in "a" and "b", and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*16
    dst[i+15:i] := a[i+15:i] + b[i+15:i]
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.33 | 1
Knights Landing | 2 | 0.5 | 1


_mm_add_pi32

__m64 _mm_add_pi32( __m64 a, __m64 b )

Synopsis

#include "mmintrin.h"
Instruction: paddd
CPUID Flag: MMX
Category: Arithmetic

Description

Add packed 32-bit integers in "a" and "b", and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*32
    dst[i+31:i] := a[i+31:i] + b[i+31:i]
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.33 | 1
Knights Landing | 2 | 0.5 | 1


_mm_add_pi8

__m64 _mm_add_pi8( __m64 a, __m64 b )

Synopsis

#include "mmintrin.h"
Instruction: paddb
CPUID Flag: MMX
Category: Arithmetic

Description

Add packed 8-bit integers in "a" and "b", and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*8
    dst[i+7:i] := a[i+7:i] + b[i+7:i]
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.33 | 1
Knights Landing | 2 | 0.5 | 1


_mm_add_ps

__m128 _mm_add_ps( __m128 a, __m128 b )

Synopsis

#include "xmmintrin.h"
Instruction: addps
CPUID Flag: SSE
Category: Arithmetic

Description

Add packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := a[i+31:i] + b[i+31:i]
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 0.5 | 1
Jaguar | 3 | 1 | 1
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 4 | 0.5 | 1
Knights Landing | 6 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 4 | 0.5 |


_mm_add_sd

__m128d _mm_add_sd( __m128d a, __m128d b )

Synopsis

#include "emmintrin.h"
Instruction: addsd
CPUID Flag: SSE2
Category: Arithmetic

Description

Add the lower double-precision (64-bit) floating-point element in "a" and "b", store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".

Operation

dst[63:0] := a[63:0] + b[63:0]
dst[127:64] := a[127:64]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 0.5 | 1
Jaguar | 3 | 1 | 1
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 4 | 0.5 | 1
Knights Landing | 6 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 4 | 0.5 |


_mm_add_si64

__m64 _mm_add_si64( __m64 a, __m64 b )

Synopsis

#include "emmintrin.h"
Instruction: paddq
CPUID Flag: SSE2
Category: Arithmetic

Description

Add 64-bit integers "a" and "b", and store the result in "dst".

Operation

dst[63:0] := a[63:0] + b[63:0]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.33 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.33 |


_mm_add_ss

__m128 _mm_add_ss( __m128 a, __m128 b )

Synopsis

#include "xmmintrin.h"
Instruction: addss
CPUID Flag: SSE
Category: Arithmetic

Description

Add the lower single-precision (32-bit) floating-point element in "a" and "b", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".

Operation

dst[31:0] := a[31:0] + b[31:0]
dst[127:32] := a[127:32]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 0.5 | 1
Jaguar | 3 | 1 | 1
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 4 | 0.5 | 1
Knights Landing | 6 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 4 | 0.5 |


_mm_adds_epi16

__m128i _mm_adds_epi16( __m128i a, __m128i b )

Synopsis

#include "emmintrin.h"
Instruction: paddsw
CPUID Flag: SSE2
Category: Arithmetic

Description

Add packed 16-bit integers in "a" and "b" using saturation, and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*16
    dst[i+15:i] := Saturate_To_Int16( a[i+15:i] + b[i+15:i] )
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.33 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.5 |


_mm_adds_epi8

__m128i _mm_adds_epi8( __m128i a, __m128i b )

Synopsis

#include "emmintrin.h"
Instruction: paddsb
CPUID Flag: SSE2
Category: Arithmetic

Description

Add packed 8-bit integers in "a" and "b" using saturation, and store the results in "dst".

Operation

FOR j := 0 to 15
    i := j*8
    dst[i+7:i] := Saturate_To_Int8( a[i+7:i] + b[i+7:i] )
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.33 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.5 |


_mm_adds_epu16

__m128i _mm_adds_epu16( __m128i a, __m128i b )

Synopsis

#include "emmintrin.h"
Instruction: paddusw
CPUID Flag: SSE2
Category: Arithmetic

Description

Add packed unsigned 16-bit integers in "a" and "b" using saturation, and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*16
    dst[i+15:i] := Saturate_To_UnsignedInt16( a[i+15:i] + b[i+15:i] )
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.33 | 1
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.5 |


_mm_adds_epu8

__m128i _mm_adds_epu8( __m128i a, __m128i b )

Synopsis

#include "emmintrin.h"
Instruction: paddusb
CPUID Flag: SSE2
Category: Arithmetic

Description

Add packed unsigned 8-bit integers in "a" and "b" using saturation, and store the results in "dst".

Operation

FOR j := 0 to 15
    i := j*8
    dst[i+7:i] := Saturate_To_UnsignedInt8( a[i+7:i] + b[i+7:i] )
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.33 | 1
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.5 |


_mm_adds_pi16

__m64 _mm_adds_pi16( __m64 a, __m64 b )

Synopsis

#include "mmintrin.h"
Instruction: paddsw
CPUID Flag: MMX
Category: Arithmetic

Description

Add packed 16-bit integers in "a" and "b" using saturation, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*16
    dst[i+15:i] := Saturate_To_Int16( a[i+15:i] + b[i+15:i] )
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.33 | 1
Knights Landing | 2 | 0.5 | 1


_mm_adds_pi8

__m64 _mm_adds_pi8( __m64 a, __m64 b )

Synopsis

#include "mmintrin.h"
Instruction: paddsb
CPUID Flag: MMX
Category: Arithmetic

Description

Add packed 8-bit integers in "a" and "b" using saturation, and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*8
    dst[i+7:i] := Saturate_To_Int8( a[i+7:i] + b[i+7:i] )
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.33 | 1
Knights Landing | 2 | 0.5 | 1


_mm_adds_pu16

__m64 _mm_adds_pu16( __m64 a, __m64 b )

Synopsis

#include "mmintrin.h"
Instruction: paddusw
CPUID Flag: MMX
Category: Arithmetic

Description

Add packed unsigned 16-bit integers in "a" and "b" using saturation, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*16
    dst[i+15:i] := Saturate_To_UnsignedInt16( a[i+15:i] + b[i+15:i] )
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.33 | 1


_mm_adds_pu8

__m64 _mm_adds_pu8( __m64 a, __m64 b )

Synopsis

#include "mmintrin.h"
Instruction: paddusb
CPUID Flag: MMX
Category: Arithmetic

Description

Add packed unsigned 8-bit integers in "a" and "b" using saturation, and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*8
    dst[i+7:i] := Saturate_To_UnsignedInt8( a[i+7:i] + b[i+7:i] )
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.33 | 1


_mm_addsub_pd

__m128d _mm_addsub_pd( __m128d a, __m128d b )

Synopsis

#include "pmmintrin.h"
Instruction: addsubpd
CPUID Flag: SSE3
Category: Arithmetic

Description

Alternatively add and subtract packed double-precision (64-bit) floating-point elements in "a" to/from packed elements in "b", and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*64
    IF (j % 1 == 0)
        dst[i+63:i] := a[i+63:i] - b[i+63:i]
    ELSE
        dst[i+63:i] := a[i+63:i] + b[i+63:i]
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 0.5 | 1
Jaguar | 3 | 1 | 1
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 4 | 0.5 | 1
Knights Landing | 6 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 4 | 0.5 |


_mm_addsub_ps

__m128 _mm_addsub_ps( __m128 a, __m128 b )

Synopsis

#include "pmmintrin.h"
Instruction: addsubps
CPUID Flag: SSE3
Category: Arithmetic

Description

Alternatively add and subtract packed single-precision (32-bit) floating-point elements in "a" to/from packed elements in "b", and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    IF (j % 1 == 0)
        dst[i+31:i] := a[i+31:i] - b[i+31:i]
    ELSE
        dst[i+31:i] := a[i+31:i] + b[i+31:i]
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 0.5 | 1
Jaguar | 3 | 1 | 1
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 4 | 0.5 | 1
Knights Landing | 6 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 4 | 0.5 |


_mm_aesdec_si128

__m128i _mm_aesdec_si128( __m128i a, __m128i RoundKey )

Synopsis

#include "wmmintrin.h"
Instruction: aesdec
CPUID Flag: AES
Category: Cryptography

Description

Perform one round of an AES decryption flow on data (state) in "a" using the round key in "RoundKey", and store the result in "dst".

Operation

state := a
a[127:0] := InvShiftRows(a[127:0])
a[127:0] := InvSubBytes(a[127:0])
a[127:0] := InvMixColumns(a[127:0])
dst[127:0] := a[127:0] XOR RoundKey[127:0]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 4 | 0.5 | 1
Jaguar | 5 | 1 | 2
Sandy Bridge | 8 | 4 | 2
Ivy Bridge | 4 | 1 | 2
Haswell | 7 | 1 | 1
Broadwell | 7 | 1 | 1
Skylake | 4 | 1 | 1
Knights Landing | 3-6 | 2 | 1
Ivy Bridge | 8 | 1 |
Haswell | 7 | 1 |
Broadwell | 7 | 1 |
Skylake | 4 | 1 |


_mm_aesdeclast_si128

__m128i _mm_aesdeclast_si128( __m128i a, __m128i RoundKey )

Synopsis

#include "wmmintrin.h"
Instruction: aesdeclast
CPUID Flag: AES
Category: Cryptography

Description

Perform the last round of an AES decryption flow on data (state) in "a" using the round key in "RoundKey", and store the result in "dst".

Operation

state := a
a[127:0] := InvShiftRows(a[127:0])
a[127:0] := InvSubBytes(a[127:0])
dst[127:0] := a[127:0] XOR RoundKey[127:0]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 4 | 0.5 | 1
Jaguar | 5 | 1 | 2
Sandy Bridge | 8 | 4 | 2
Ivy Bridge | 4 | 1 | 2
Haswell | 7 | 1 | 1
Broadwell | 7 | 1 | 1
Skylake | 4 | 1 | 1
Knights Landing | 3-6 | 2 | 1
Ivy Bridge | 8 | 1 |
Haswell | 7 | 1 |
Broadwell | 7 | 1 |
Skylake | 4 | 1 |


_mm_aesenc_si128

__m128i _mm_aesenc_si128( __m128i a, __m128i RoundKey )

Synopsis

#include "wmmintrin.h"
Instruction: aesenc
CPUID Flag: AES
Category: Cryptography

Description

Perform one round of an AES encryption flow on data (state) in "a" using the round key in "RoundKey", and store the result in "dst"."

Operation

state := a
a[127:0] := ShiftRows(a[127:0])
a[127:0] := SubBytes(a[127:0])
a[127:0] := MixColumns(a[127:0])
dst[127:0] := a[127:0] XOR RoundKey[127:0]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 4 | 0.5 | 1
Jaguar | 5 | 1 | 2
Sandy Bridge | 8 | 4 | 2
Ivy Bridge | 4 | 1 | 2
Haswell | 7 | 1 | 1
Broadwell | 7 | 1 | 1
Skylake | 4 | 1 | 1
Knights Landing | 3-6 | 2 | 1
Ivy Bridge | 8 | 1 |
Haswell | 7 | 1 |
Broadwell | 7 | 1 |
Skylake | 4 | 1 |


_mm_aesenclast_si128

__m128i _mm_aesenclast_si128( __m128i a, __m128i RoundKey )

Synopsis

#include "wmmintrin.h"
Instruction: aesenclast
CPUID Flag: AES
Category: Cryptography

Description

Perform the last round of an AES encryption flow on data (state) in "a" using the round key in "RoundKey", and store the result in "dst"."

Operation

state := a
a[127:0] := ShiftRows(a[127:0])
a[127:0] := SubBytes(a[127:0])
dst[127:0] := a[127:0] XOR RoundKey[127:0]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 4 | 0.5 | 1
Jaguar | 5 | 1 | 2
Sandy Bridge | 8 | 4 | 2
Ivy Bridge | 4 | 1 | 2
Haswell | 7 | 1 | 1
Broadwell | 7 | 1 | 1
Skylake | 4 | 1 | 1
Knights Landing | 3-6 | 2 | 1
Ivy Bridge | 8 | 1 |
Haswell | 7 | 1 |
Broadwell | 7 | 1 |
Skylake | 4 | 1 |


_mm_aesimc_si128

__m128i _mm_aesimc_si128( __m128i a )

Synopsis

#include "wmmintrin.h"
Instruction: aesimc
CPUID Flag: AES
Category: Cryptography

Description

Perform the InvMixColumns transformation on "a" and store the result in "dst".

Operation

dst[127:0] := InvMixColumns(a[127:0])

Performance

Architecture | Latency | Throughput | μops
Ryzen | 4 | 0.5 | 1
Jaguar | 2 | 1 | 1
Sandy Bridge |  | 2 | 2
Ivy Bridge | 14 | 2 | 2
Haswell | 14 | 2 | 2
Broadwell | 14 | 2 | 2
Skylake | 8 | 2 | 2
Knights Landing | 3-6 | 2 | 1
Ivy Bridge | 14 | 2 |
Haswell | 14 | 2 |
Broadwell | 14 | 2 |
Skylake | 8 | 2 |


_mm_aeskeygenassist_si128

__m128i _mm_aeskeygenassist_si128( __m128i a, const int imm8 )

Synopsis

#include "wmmintrin.h"
Instruction: aeskeygenassist
CPUID Flag: AES
Category: Cryptography

Description

Assist in expanding the AES cipher key by computing steps towards generating a round key for encryption cipher using data from "a" and an 8-bit round constant specified in "imm8", and store the result in "dst"."

Operation

X3[31:0] := a[127:96]
X2[31:0] := a[95:64]
X1[31:0] := a[63:32]
X0[31:0] := a[31:0]
RCON[31:0] := ZeroExtend(imm8[7:0])
dst[31:0] := SubWord(X1)
dst[63:32] := RotWord(SubWord(X1)) XOR RCON
dst[95:64] := SubWord(X3)
dst[127:96] := RotWord(SubWord(X3)) XOR RCON

Performance

Architecture | Latency | Throughput | μops
Ryzen | 4 | 0.5 | 1
Jaguar | 2 | 1 | 1
Sandy Bridge | 8 | 8 | 11
Ivy Bridge | 10 | 8 | 11
Haswell | 10 | 9 | 10
Broadwell | 10 | 9 | 10
Skylake | 12 | 12 | 13
Knights Landing | 3-6 | 2 | 1
Ivy Bridge | 10 | 8 |
Haswell | 10 | 8 |
Broadwell | 10 | 8 |
Skylake | 12 | 12 |


_mm_alignr_epi8

__m128i _mm_alignr_epi8( __m128i a, __m128i b, int count )

Synopsis

#include "tmmintrin.h"
Instruction: palignr
CPUID Flag: SSSE3
Category: Miscellaneous

Description

Concatenate 16-byte blocks in "a" and "b" into a 32-byte temporary result, shift the result right by "count" bytes, and store the low 16 bytes in "dst".

Operation

tmp[255:0] := ((a[127:0] << 128) OR b[127:0]) >> (count[7:0]*8)
dst[127:0] := tmp[127:0]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 2-6 | 2 | 1
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm_alignr_pi8

__m64 _mm_alignr_pi8( __m64 a, __m64 b, int count )

Synopsis

#include "tmmintrin.h"
Instruction: palignr
CPUID Flag: SSSE3
Category: Miscellaneous

Description

Concatenate 8-byte blocks in "a" and "b" into a 16-byte temporary result, shift the result right by "count" bytes, and store the low 16 bytes in "dst".

Operation

tmp[127:0] := ((a[63:0] << 64) OR b[63:0]) >> (count[7:0]*8)
dst[63:0] := tmp[63:0]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 2-6 | 2 | 1
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm_and_pd

__m128d _mm_and_pd( __m128d a, __m128d b )

Synopsis

#include "emmintrin.h"
Instruction: andpd
CPUID Flag: SSE2
Category: Logical

Description

Compute the bitwise AND of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*64
    dst[i+63:i] := (a[i+63:i] AND b[i+63:i])
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.25 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 1 | 1
Ivy Bridge | 1 | 1 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 0.33 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 1 | 1 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 0.33 |


_mm_and_ps

__m128 _mm_and_ps( __m128 a, __m128 b )

Synopsis

#include "xmmintrin.h"
Instruction: andps
CPUID Flag: SSE
Category: Logical

Description

Compute the bitwise AND of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := (a[i+31:i] AND b[i+31:i])
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.25 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 1 | 1
Ivy Bridge | 1 | 1 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 0.33 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 1 | 1 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 0.33 |


_mm_and_si128

__m128i _mm_and_si128( __m128i a, __m128i b )

Synopsis

#include "emmintrin.h"
Instruction: pand
CPUID Flag: SSE2
Category: Logical

Description

Compute the bitwise AND of 128 bits (representing integer data) in "a" and "b", and store the result in "dst".

Operation

dst[127:0] := (a[127:0] AND b[127:0])

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.25 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 |  | 1
Ivy Bridge | 1 | 0.33 | 1
Haswell | 1 | 0.33 | 1
Broadwell | 1 | 0.33 | 1
Skylake | 1 | 0.33 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 1 | 0.33 |
Haswell | 1 | 0.33 |
Broadwell | 1 | 0.33 |
Skylake | 1 | 0.33 |


_mm_and_si64

__m64 _mm_and_si64( __m64 a, __m64 b )

Synopsis

#include "mmintrin.h"
Instruction: pand
CPUID Flag: MMX
Category: Logical

Description

Compute the bitwise AND of 64 bits (representing integer data) in "a" and "b", and store the result in "dst".

Operation

dst[63:0] := (a[63:0] AND b[63:0])

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.25 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 |  | 1
Ivy Bridge | 1 | 0.33 | 1
Haswell | 1 | 0.33 | 1
Broadwell | 1 | 0.33 | 1
Skylake | 1 | 0.33 | 1
Knights Landing | 2 | 0.5 | 1


_mm_andnot_pd

__m128d _mm_andnot_pd( __m128d a, __m128d b )

Synopsis

#include "emmintrin.h"
Instruction: andnpd
CPUID Flag: SSE2
Category: Logical

Description

Compute the bitwise NOT of packed double-precision (64-bit) floating-point elements in "a" and then AND with "b", and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*64
    dst[i+63:i] := ((NOT a[i+63:i]) AND b[i+63:i])
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.25 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 1 | 1
Ivy Bridge | 1 | 1 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 0.33 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 1 | 1 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 0.33 |


_mm_andnot_ps

__m128 _mm_andnot_ps( __m128 a, __m128 b )

Synopsis

#include "xmmintrin.h"
Instruction: andnps
CPUID Flag: SSE
Category: Logical

Description

Compute the bitwise NOT of packed single-precision (32-bit) floating-point elements in "a" and then AND with "b", and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := ((NOT a[i+31:i]) AND b[i+31:i])
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.25 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 1 | 1
Ivy Bridge | 1 | 1 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 0.33 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 1 | 1 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 0.33 |


_mm_andnot_si128

__m128i _mm_andnot_si128( __m128i a, __m128i b )

Synopsis

#include "emmintrin.h"
Instruction: pandn
CPUID Flag: SSE2
Category: Logical

Description

Compute the bitwise NOT of 128 bits (representing integer data) in "a" and then AND with "b", and store the result in "dst".

Operation

dst[127:0] := ((NOT a[127:0]) AND b[127:0])

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.25 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 |  | 1
Ivy Bridge | 1 | 0.33 | 1
Haswell | 1 | 0.33 | 1
Broadwell | 1 | 0.33 | 1
Skylake | 1 | 0.33 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 1 | 0.33 |
Haswell | 1 | 0.33 |
Broadwell | 1 | 0.33 |
Skylake | 1 | 0.33 |


_mm_andnot_si64

__m64 _mm_andnot_si64( __m64 a, __m64 b )

Synopsis

#include "mmintrin.h"
Instruction: pandn
CPUID Flag: MMX
Category: Logical

Description

Compute the bitwise NOT of 64 bits (representing integer data) in "a" and then AND with "b", and store the result in "dst".

Operation

dst[63:0] := ((NOT a[63:0]) AND b[63:0])

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.25 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 |  | 1
Ivy Bridge | 1 | 0.33 | 1
Haswell | 1 | 0.33 | 1
Broadwell | 1 | 0.33 | 1
Skylake | 1 | 0.33 | 1
Knights Landing | 2 | 0.5 | 1


_mm_asin_pd

__m128d _mm_asin_pd( __m128d a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Trigonometry

Description

Compute the inverse sine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*64
    dst[i+63:i] := ASIN(a[i+63:i])
ENDFOR
dst[MAX:128] := 0


_mm_asin_ps

__m128 _mm_asin_ps( __m128 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Trigonometry

Description

Compute the inverse sine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := ASIN(a[i+31:i])
ENDFOR
dst[MAX:128] := 0


_mm_asinh_pd

__m128d _mm_asinh_pd( __m128d a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Trigonometry

Description

Compute the inverse hyperbolic sine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*64
    dst[i+63:i] := ASINH(a[i+63:i])
ENDFOR
dst[MAX:128] := 0


_mm_asinh_ps

__m128 _mm_asinh_ps( __m128 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Trigonometry

Description

Compute the inverse hyperbolic sine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := ASINH(a[i+31:i])
ENDFOR
dst[MAX:128] := 0


_mm_atan_pd

__m128d _mm_atan_pd( __m128d a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Trigonometry

Description

Compute the inverse tangent of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*64
    dst[i+63:i] := ATAN(a[i+63:i])
ENDFOR
dst[MAX:128] := 0


_mm_atan_ps

__m128 _mm_atan_ps( __m128 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Trigonometry

Description

Compute the inverse tangent of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := ATAN(a[i+31:i])
ENDFOR
dst[MAX:128] := 0


_mm_atan2_pd

__m128d _mm_atan2_pd( __m128d a, __m128d b )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Trigonometry

Description

Compute the inverse tangent of packed double-precision (64-bit) floating-point elements in "a" divided by packed elements in "b", and store the results in "dst" expressed in radians.

Operation

FOR j := 0 to 1
    i := j*64
    dst[i+63:i] := ATAN(a[i+63:i] / b[i+63:i])
ENDFOR
dst[MAX:128] := 0


_mm_atan2_ps

__m128 _mm_atan2_ps( __m128 a, __m128 b )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Trigonometry

Description

Compute the inverse tangent of packed single-precision (32-bit) floating-point elements in "a" divided by packed elements in "b", and store the results in "dst" expressed in radians.

Operation

FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := ATAN(a[i+31:i] / b[i+31:i])
ENDFOR
dst[MAX:128] := 0


_mm_atanh_pd

__m128d _mm_atanh_pd( __m128d a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Trigonometry

Description

Compute the inverse hyperbolic tangent of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*64
    dst[i+63:i] := ATANH(a[i+63:i])
ENDFOR
dst[MAX:128] := 0


_mm_atanh_ps

__m128 _mm_atanh_ps( __m128 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Trigonometry

Description

Compute the inverse hyperbolic tangent of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := ATANH(a[i+31:i])
ENDFOR
dst[MAX:128] := 0


_mm_avg_epu16

__m128i _mm_avg_epu16( __m128i a, __m128i b )

Synopsis

#include "emmintrin.h"
Instruction: pavgw
CPUID Flag: SSE2
Category: Probability/Statistics

Description

Average packed unsigned 16-bit integers in "a" and "b", and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*16
    dst[i+15:i] := (a[i+15:i] + b[i+15:i] + 1) >> 1
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.5 |


_mm_avg_epu8

__m128i _mm_avg_epu8( __m128i a, __m128i b )

Synopsis

#include "emmintrin.h"
Instruction: pavgb
CPUID Flag: SSE2
Category: Probability/Statistics

Description

Average packed unsigned 8-bit integers in "a" and "b", and store the results in "dst".

Operation

FOR j := 0 to 15
    i := j*8
    dst[i+7:i] := (a[i+7:i] + b[i+7:i] + 1) >> 1
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.5 |


_mm_avg_pu16

__m64 _mm_avg_pu16( __m64 a, __m64 b )

Synopsis

#include "xmmintrin.h"
Instruction: pavgw
CPUID Flag: SSE
Category: Probability/Statistics

Description

Average packed unsigned 16-bit integers in "a" and "b", and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*16
    dst[i+15:i] := (a[i+15:i] + b[i+15:i] + 1) >> 1
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1


_mm_avg_pu8

__m64 _mm_avg_pu8( __m64 a, __m64 b )

Synopsis

#include "xmmintrin.h"
Instruction: pavgb
CPUID Flag: SSE
Category: Probability/Statistics

Description

Average packed unsigned 8-bit integers in "a" and "b", and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*8
    dst[i+7:i] := (a[i+7:i] + b[i+7:i] + 1) >> 1
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1


_mm_blend_epi16

__m128i _mm_blend_epi16( __m128i a, __m128i b, const int imm8 )

Synopsis

#include "smmintrin.h"
Instruction: pblendw
CPUID Flag: SSE4.1
Category: Swizzle

Description

Blend packed 16-bit integers from "a" and "b" using control mask "imm8", and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*16
    IF imm8[j]
        dst[i+15:i] := b[i+15:i]
    ELSE
        dst[i+15:i] := a[i+15:i]
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 2 | 2 | 1
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm_blend_epi32

__m128i _mm_blend_epi32( __m128i a, __m128i b, const int imm8 )

Synopsis

#include "immintrin.h"
Instruction: vpblendd
CPUID Flag: AVX2
Category: Swizzle

Description

Blend packed 32-bit integers from "a" and "b" using control mask "imm8", and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    IF imm8[j]
        dst[i+31:i] := b[i+31:i]
    ELSE
        dst[i+31:i] := a[i+31:i]
    FI
ENDFOR
dst[MAX:128] := 0

Performance

Architecture | Latency | Throughput | μops
Haswell | 1 | 0.33 | 1
Broadwell | 1 | 0.33 | 1
Skylake | 1 | 0.33 | 1
Knights Landing | 2 | 0.5 | 1
Haswell | 1 | 0.33 |
Broadwell | 1 | 0.33 |
Skylake | 1 | 0.33 |


_mm_blend_pd

__m128d _mm_blend_pd( __m128d a, __m128d b, const int imm8 )

Synopsis

#include "smmintrin.h"
Instruction: blendpd
CPUID Flag: SSE4.1
Category: Swizzle

Description

Blend packed double-precision (64-bit) floating-point elements from "a" and "b" using control mask "imm8", and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*64
    IF imm8[j]
        dst[i+63:i] := b[i+63:i]
    ELSE
        dst[i+63:i] := a[i+63:i]
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.33 | 1
Broadwell | 1 | 0.33 | 1
Skylake | 1 | 0.33 | 1
Knights Landing | 2 | 2 | 1
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 0.33 |
Broadwell | 1 | 0.33 |
Skylake | 1 | 0.33 |


_mm_blend_ps

__m128 _mm_blend_ps( __m128 a, __m128 b, const int imm8 )

Synopsis

#include "smmintrin.h"
Instruction: blendps
CPUID Flag: SSE4.1
Category: Swizzle

Description

Blend packed single-precision (32-bit) floating-point elements from "a" and "b" using control mask "imm8", and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    IF imm8[j]
        dst[i+31:i] := b[i+31:i]
    ELSE
        dst[i+31:i] := a[i+31:i]
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.33 | 1
Broadwell | 1 | 0.33 | 1
Skylake | 1 | 0.33 | 1
Knights Landing | 2 | 2 | 1
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 0.33 |
Broadwell | 1 | 0.33 |
Skylake | 1 | 0.33 |


_mm_blendv_epi8

__m128i _mm_blendv_epi8( __m128i a, __m128i b, __m128i mask )

Synopsis

#include "smmintrin.h"
Instruction: pblendvb
CPUID Flag: SSE4.1
Category: Swizzle

Description

Blend packed 8-bit integers from "a" and "b" using "mask", and store the results in "dst".

Operation

FOR j := 0 to 15
    i := j*8
    IF mask[i+7]
        dst[i+7:i] := b[i+7:i]
    ELSE
        dst[i+7:i] := a[i+7:i]
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Sandy Bridge | 2 | 1 | 2
Ivy Bridge | 2 | 1 | 2
Haswell | 2 | 2 | 2
Broadwell | 2 | 2 | 2
Skylake | 1 | 1 | 1
Knights Landing | 9-10 | 9 | 5


_mm_blendv_pd

__m128d _mm_blendv_pd( __m128d a, __m128d b, __m128d mask )

Synopsis

#include "smmintrin.h"
Instruction: blendvpd
CPUID Flag: SSE4.1
Category: Swizzle

Description

Blend packed double-precision (64-bit) floating-point elements from "a" and "b" using "mask", and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*64
    IF mask[i+63]
        dst[i+63:i] := b[i+63:i]
    ELSE
        dst[i+63:i] := a[i+63:i]
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Sandy Bridge | 2 | 1 | 2
Ivy Bridge | 2 | 1 | 2
Haswell | 2 | 2 | 2
Broadwell | 2 | 2 | 2
Skylake | 1 | 1 | 1
Knights Landing | 7 | 7 | 2
Ivy Bridge | 2 | 1 |
Haswell | 2 | 2 |
Broadwell | 2 | 2 |
Skylake | 1 | 1 |


_mm_blendv_ps

__m128 _mm_blendv_ps( __m128 a, __m128 b, __m128 mask )

Synopsis

#include "smmintrin.h"
Instruction: blendvps
CPUID Flag: SSE4.1
Category: Swizzle

Description

Blend packed single-precision (32-bit) floating-point elements from "a" and "b" using "mask", and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    IF mask[i+31]
        dst[i+31:i] := b[i+31:i]
    ELSE
        dst[i+31:i] := a[i+31:i]
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Sandy Bridge | 2 | 1 | 2
Ivy Bridge | 2 | 1 | 2
Haswell | 2 | 2 | 2
Broadwell | 2 | 2 | 2
Skylake | 1 | 1 | 1
Knights Landing | 7 | 7 | 2
Ivy Bridge | 2 | 1 |
Haswell | 2 | 2 |
Broadwell | 2 | 2 |
Skylake | 1 | 1 |


_mm_broadcast_ss

__m128 _mm_broadcast_ss( float const * mem_addr )

Synopsis

#include "immintrin.h"
Instruction: vbroadcastss
CPUID Flag: AVX
Category: Load

Description

Broadcast a single-precision (32-bit) floating-point element from memory to all elements of "dst".

Operation

tmp[31:0] := MEM[mem_addr+31:mem_addr]
FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := tmp[31:0]
ENDFOR
dst[MAX:128] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 1 | 2
Sandy Bridge |  | 1 | 1
Ivy Bridge | 5 | 1 | 2
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 3 | 1 | 1
Knights Landing | 3-6 | 1 | 1


_mm_broadcastb_epi8

__m128i _mm_broadcastb_epi8( __m128i a )

Synopsis

#include "immintrin.h"
Instruction: vpbroadcastb
CPUID Flag: AVX2
Category: Swizzle

Description

Broadcast the low packed 8-bit integer from "a" to all elements of "dst".

Operation

FOR j := 0 to 15
    i := j*8
    dst[i+7:i] := a[7:0]
ENDFOR
dst[MAX:128] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Haswell | 7 | 1 | 3
Broadwell | 7 | 1 | 3
Skylake | 7 | 1 | 2
Knights Landing | 8 | 7 | 2
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 3 | 1 |


_mm_broadcastd_epi32

__m128i _mm_broadcastd_epi32( __m128i a )

Synopsis

#include "immintrin.h"
Instruction: vpbroadcastd
CPUID Flag: AVX2
Category: Swizzle

Description

Broadcast the low packed 32-bit integer from "a" to all elements of "dst".

Operation

FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := a[31:0]
ENDFOR
dst[MAX:128] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Haswell | 5 | 0.5 | 1
Broadwell | 5 | 0.5 | 1
Skylake | 4 | 0.5 | 1
Knights Landing | 3 | 1 | 1
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 3 | 1 |


_mm_broadcastq_epi64

__m128i _mm_broadcastq_epi64( __m128i a )

Synopsis

#include "immintrin.h"
Instruction: vpbroadcastq
CPUID Flag: AVX2
Category: Swizzle

Description

Broadcast the low packed 64-bit integer from "a" to all elements of "dst".

Operation

FOR j := 0 to 1
    i := j*64
    dst[i+63:i] := a[63:0]
ENDFOR
dst[MAX:128] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Haswell | 5 | 0.5 | 1
Broadwell | 5 | 0.5 | 1
Skylake | 4 | 0.5 | 1
Knights Landing | 3 | 1 | 1


_mm_broadcastsd_pd

__m128d _mm_broadcastsd_pd( __m128d a )

Synopsis

#include "immintrin.h"
Instruction: movddup
CPUID Flag: AVX2
Category: Swizzle

Description

Broadcast the low double-precision (64-bit) floating-point element from "a" to all elements of "dst".

Operation

FOR j := 0 to 1
    i := j*64
    dst[i+63:i] := a[63:0]
ENDFOR
dst[MAX:128] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 1 | 1 | 1
Ivy Bridge | 1 | 1 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 3-6 | 1 | 1


_mm_broadcastsi128_si256

__m256i _mm_broadcastsi128_si256( __m128i a )

Synopsis

#include "immintrin.h"
Instruction: vbroadcasti128
CPUID Flag: AVX2
Category: Swizzle

Description

Broadcast 128 bits of integer data from "a" to all 128-bit lanes in "dst".

Operation

dst[127:0] := a[127:0]
dst[255:128] := a[127:0]
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 0.5 | 2
Haswell | 3 | 0.5 | 1
Broadwell | 3 | 0.5 | 1
Skylake | 3 | 0.5 | 1
Knights Landing | 5 | 0.5 | 1


_mm_broadcastss_ps

__m128 _mm_broadcastss_ps( __m128 a )

Synopsis

#include "immintrin.h"
Instruction: vbroadcastss
CPUID Flag: AVX2
Category: Swizzle

Description

Broadcast the low single-precision (32-bit) floating-point element from "a" to all elements of "dst".

Operation

FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := a[31:0]
ENDFOR
dst[MAX:128] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 1 | 2
Sandy Bridge |  | 1 | 1
Ivy Bridge | 5 | 1 | 2
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 3 | 1 | 1
Knights Landing | 3-6 | 1 | 1


_mm_broadcastw_epi16

__m128i _mm_broadcastw_epi16( __m128i a )

Synopsis

#include "immintrin.h"
Instruction: vpbroadcastw
CPUID Flag: AVX2
Category: Swizzle

Description

Broadcast the low packed 16-bit integer from "a" to all elements of "dst".

Operation

FOR j := 0 to 7
    i := j*16
    dst[i+15:i] := a[15:0]
ENDFOR
dst[MAX:128] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Haswell | 7 | 1 | 3
Broadwell | 7 | 1 | 3
Skylake | 7 | 1 | 2
Knights Landing | 8 | 7 | 2


_mm_bslli_si128

__m128i _mm_bslli_si128( __m128i a, int imm8 )

Synopsis

#include "emmintrin.h"
Instruction: pslldq
CPUID Flag: SSE2
Category: Shift

Description

Shift "a" left by "imm8" bytes while shifting in zeros, and store the results in "dst".

Operation

tmp := imm8[7:0]
IF tmp > 15
    tmp := 16
FI
dst[127:0] := a[127:0] << (tmp*8)

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 1 | 1 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm_bsrli_si128

__m128i _mm_bsrli_si128( __m128i a, int imm8 )

Synopsis

#include "emmintrin.h"
Instruction: psrldq
CPUID Flag: SSE2
Category: Shift

Description

Shift "a" right by "imm8" bytes while shifting in zeros, and store the results in "dst".

Operation

tmp := imm8[7:0]
IF tmp > 15
    tmp := 16
FI
dst[127:0] := a[127:0] >> (tmp*8)

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 1 | 1 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm_castpd_ps

__m128 _mm_castpd_ps( __m128d a )

Synopsis

#include "emmintrin.h"
Instruction: N/A
CPUID Flag: SSE2
Category: Cast

Description

Cast vector of type __m128d to type __m128. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.


_mm_castpd_si128

__m128i _mm_castpd_si128( __m128d a )

Synopsis

#include "emmintrin.h"
Instruction: N/A
CPUID Flag: SSE2
Category: Cast

Description

Cast vector of type __m128d to type __m128i. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.


_mm_castps_pd

__m128d _mm_castps_pd( __m128 a )

Synopsis

#include "emmintrin.h"
Instruction: N/A
CPUID Flag: SSE2
Category: Cast

Description

Cast vector of type __m128 to type __m128d. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.


_mm_castps_si128

__m128i _mm_castps_si128( __m128 a )

Synopsis

#include "emmintrin.h"
Instruction: N/A
CPUID Flag: SSE2
Category: Cast

Description

Cast vector of type __m128 to type __m128i. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.


_mm_castsi128_pd

__m128d _mm_castsi128_pd( __m128i a )

Synopsis

#include "emmintrin.h"
Instruction: N/A
CPUID Flag: SSE2
Category: Cast

Description

Cast vector of type __m128i to type __m128d. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.


_mm_castsi128_ps

__m128 _mm_castsi128_ps( __m128i a )

Synopsis

#include "emmintrin.h"
Instruction: N/A
CPUID Flag: SSE2
Category: Cast

Description

Cast vector of type __m128i to type __m128. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.


_mm_cbrt_pd

__m128d _mm_cbrt_pd( __m128d a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Elementary Math Functions

Description

Compute the cube root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*64
    dst[i+63:i] := CubeRoot(a[i+63:i])
ENDFOR
dst[MAX:128] := 0


_mm_cbrt_ps

__m128 _mm_cbrt_ps( __m128 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Elementary Math Functions

Description

Compute the cube root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := CubeRoot(a[i+31:i])
ENDFOR
dst[MAX:128] := 0


_mm_cdfnorm_pd

__m128d _mm_cdfnorm_pd( __m128d a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Probability/Statistics

Description

Compute the cumulative distribution function of packed double-precision (64-bit) floating-point elements in "a" using the normal distribution, and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*64
    dst[i+63:i] := CDFNormal(a[i+63:i])
ENDFOR
dst[MAX:128] := 0


_mm_cdfnorm_ps

__m128 _mm_cdfnorm_ps( __m128 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Probability/Statistics

Description

Compute the cumulative distribution function of packed single-precision (32-bit) floating-point elements in "a" using the normal distribution, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := CDFNormal(a[i+31:i])
ENDFOR
dst[MAX:128] := 0


_mm_cdfnorminv_pd

__m128d _mm_cdfnorminv_pd( __m128d a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Probability/Statistics

Description

Compute the inverse cumulative distribution function of packed double-precision (64-bit) floating-point elements in "a" using the normal distribution, and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*64
    dst[i+63:i] := InverseCDFNormal(a[i+63:i])
ENDFOR
dst[MAX:128] := 0


_mm_cdfnorminv_ps

__m128 _mm_cdfnorminv_ps( __m128 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Probability/Statistics

Description

Compute the inverse cumulative distribution function of packed single-precision (32-bit) floating-point elements in "a" using the normal distribution, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := InverseCDFNormal(a[i+31:i])
ENDFOR
dst[MAX:128] := 0


_mm_ceil_pd

__m128d _mm_ceil_pd( __m128d a )

Synopsis

#include "smmintrin.h"
Instruction: roundpd
CPUID Flag: SSE4.1
Category: Special Math Functions

Description

Round the packed double-precision (64-bit) floating-point elements in "a" up to an integer value, and store the results as packed double-precision floating-point elements in "dst".

Operation

FOR j := 0 to 1
    i := j*64
    dst[i+63:i] := CEIL(a[i+63:i])
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 4 | 1 | 1
Jaguar | 4 | 1 | 1
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 6 | 2 | 2
Broadwell | 6 | 2 | 2
Skylake | 8 | 1 | 2
Knights Landing | 6 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 6 | 2 |
Broadwell | 6 | 2 |
Skylake | 6 | 2 |


_mm_ceil_ps

__m128 _mm_ceil_ps( __m128 a )

Synopsis

#include "smmintrin.h"
Instruction: roundps
CPUID Flag: SSE4.1
Category: Special Math Functions

Description

Round the packed single-precision (32-bit) floating-point elements in "a" up to an integer value, and store the results as packed single-precision floating-point elements in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := CEIL(a[i+31:i])
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 4 | 1 | 1
Jaguar | 4 | 1 | 1
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 6 | 2 | 2
Broadwell | 6 | 2 | 2
Skylake | 8 | 1 | 2
Knights Landing | 6 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 6 | 2 |
Broadwell | 6 | 2 |
Skylake | 6 | 2 |


_mm_ceil_sd

__m128d _mm_ceil_sd( __m128d a, __m128d b )

Synopsis

#include "smmintrin.h"
Instruction: roundsd
CPUID Flag: SSE4.1
Category: Special Math Functions

Description

Round the lower double-precision (64-bit) floating-point element in "b" up to an integer value, store the result as a double-precision floating-point element in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".

Operation

dst[63:0] := CEIL(b[63:0])
dst[127:64] := a[127:64]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 4 | 1 | 1
Jaguar | 4 | 1 | 1
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 6 | 2 | 2
Broadwell | 6 | 2 | 2
Skylake | 8 | 1 | 2
Knights Landing | 6 | 2 | 1
Ivy Bridge | 3 | 1 |
Haswell | 6 | 2 |
Broadwell | 6 | 2 |
Skylake | 6 | 2 |


_mm_ceil_ss

__m128 _mm_ceil_ss( __m128 a, __m128 b )

Synopsis

#include "smmintrin.h"
Instruction: roundss
CPUID Flag: SSE4.1
Category: Special Math Functions

Description

Round the lower single-precision (32-bit) floating-point element in "b" up to an integer value, store the result as a single-precision floating-point element in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".

Operation

dst[31:0] := CEIL(b[31:0])
dst[127:32] := a[127:32]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 4 | 1 | 1
Jaguar | 4 | 1 | 1
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 6 | 2 | 2
Broadwell | 6 | 2 | 2
Skylake | 8 | 1 | 2
Knights Landing | 6 | 2 | 1
Ivy Bridge | 3 | 1 |
Haswell | 6 | 2 |
Broadwell | 6 | 2 |
Skylake | 6 | 2 |


_mm_cexp_ps

__m128 _mm_cexp_ps( __m128 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Elementary Math Functions

Description

Compute the exponential value of "e" raised to the power of packed complex single-precision (32-bit) floating-point elements in "a", and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := e^(a[i+31:i])
ENDFOR
dst[MAX:128] := 0


_mm_cldemote

void _mm_cldemote( void const * p )

Synopsis

#include "immintrin.h"
Instruction: cldemote
CPUID Flag: CLDEMOTE
Category: Miscellaneous

Description

Hint to hardware that the cache line that contains "p" should be demoted from the cache closest to the processor core to a level more distant from the processor core.


_mm_clflush

void _mm_clflush( void const* p )

Synopsis

#include "emmintrin.h"
Instruction: clflush
CPUID Flag: SSE2
Category: General Support

Description

Invalidate and flush the cache line that contains "p" from all levels of the cache hierarchy.


_mm_clflushopt

void _mm_clflushopt( void const * p )

Synopsis

#include "immintrin.h"
Instruction: clflushopt
CPUID Flag: CLFLUSHOPT
Category: General Support

Description

Invalidate and flush the cache line that contains "p" from all levels of the cache hierarchy.


_mm_clmulepi64_si128

__m128i _mm_clmulepi64_si128( __m128i a, __m128i b, const int imm8 )

Synopsis

#include "wmmintrin.h"
Instruction: pclmulqdq
CPUID Flag: PCLMULQDQ
Category: Application-Targeted

Description

Perform a carry-less multiplication of two 64-bit integers, selected from "a" and "b" according to "imm8", and store the results in "dst".

Operation

IF (imm8[0] == 0)
    TEMP1 := a[63:0]
ELSE
    TEMP1 := a[127:64]
FI
IF (imm8[4] == 0)
    TEMP2 := b[63:0]
ELSE
    TEMP2 := b[127:64]
FI
FOR i := 0 to 63
    TEMP[i] := (TEMP1[0] and TEMP2[i])
    FOR j := 1 to i
        TEMP[i] := TEMP[i] XOR (TEMP1[j] AND TEMP2[i-j])
    ENDFOR
    dst[i] := TEMP[i]
ENDFOR
FOR i := 64 to 127
    TEMP[i] := 0
    FOR j := (i - 63) to 63
        TEMP[i] := TEMP[i] XOR (TEMP1[j] AND TEMP2[i-j])
    ENDFOR
    dst[i] := TEMP[i]
ENDFOR
dst[127] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 4 | 2 | 4
Jaguar | 3 | 1 | 1
Sandy Bridge | 14 | 8 | 18
Ivy Bridge | 14 | 8 | 18
Haswell | 7 | 2 | 3
Broadwell | 5 | 1 | 1
Skylake | 7 | 1 | 1
Knights Landing | 3-6 | 2 | 1
Ivy Bridge | 14 | 8 |
Haswell | 7 | 2 |
Broadwell | 5 | 1 |
Skylake | 7 | 1 |


_mm_clog_ps

__m128 _mm_clog_ps( __m128 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Elementary Math Functions

Description

Compute the natural logarithm of packed complex single-precision (32-bit) floating-point elements in "a", and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := ln(a[i+31:i])
ENDFOR
dst[MAX:128] := 0


_mm_clwb

void _mm_clwb( void const * p )

Synopsis

#include "immintrin.h"
Instruction: clwb
CPUID Flag: CLWB
Category: General Support

Description

Write back to memory the cache line that contains "p" from any level of the cache hierarchy in the cache coherence domain.


_mm_cmp_pd

__m128d _mm_cmp_pd( __m128d a, __m128d b, const int imm8 )

Synopsis

#include "immintrin.h"
Instruction: vcmppd
CPUID Flag: AVX
Category: Compare

Description

Compare packed double-precision (64-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in "dst".

Operation

CASE (imm8[7:0]) OF
0: OP := _CMP_EQ_OQ
1: OP := _CMP_LT_OS
2: OP := _CMP_LE_OS
3: OP := _CMP_UNORD_Q
4: OP := _CMP_NEQ_UQ
5: OP := _CMP_NLT_US
6: OP := _CMP_NLE_US
7: OP := _CMP_ORD_Q
8: OP := _CMP_EQ_UQ
9: OP := _CMP_NGE_US
10: OP := _CMP_NGT_US
11: OP := _CMP_FALSE_OQ
12: OP := _CMP_NEQ_OQ
13: OP := _CMP_GE_OS
14: OP := _CMP_GT_OS
15: OP := _CMP_TRUE_UQ
16: OP := _CMP_EQ_OS
17: OP := _CMP_LT_OQ
18: OP := _CMP_LE_OQ
19: OP := _CMP_UNORD_S
20: OP := _CMP_NEQ_US
21: OP := _CMP_NLT_UQ
22: OP := _CMP_NLE_UQ
23: OP := _CMP_ORD_S
24: OP := _CMP_EQ_US
25: OP := _CMP_NGE_UQ
26: OP := _CMP_NGT_UQ
27: OP := _CMP_FALSE_OS
28: OP := _CMP_NEQ_OS
29: OP := _CMP_GE_OQ
30: OP := _CMP_GT_OQ
31: OP := _CMP_TRUE_US
ESAC
FOR j := 0 to 1
    i := j*64
    dst[i+63:i] := ( a[i+63:i] OP b[i+63:i] ) ? 0xFFFFFFFFFFFFFFFF : 0
ENDFOR
dst[MAX:128] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 1 | 2
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 4 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 4 | 0.5 |


_mm_cmp_ps

__m128 _mm_cmp_ps( __m128 a, __m128 b, const int imm8 )

Synopsis

#include "immintrin.h"
Instruction: vcmpps
CPUID Flag: AVX
Category: Compare

Description

Compare packed single-precision (32-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in "dst".

Operation

CASE (imm8[7:0]) OF
0: OP := _CMP_EQ_OQ
1: OP := _CMP_LT_OS
2: OP := _CMP_LE_OS
3: OP := _CMP_UNORD_Q
4: OP := _CMP_NEQ_UQ
5: OP := _CMP_NLT_US
6: OP := _CMP_NLE_US
7: OP := _CMP_ORD_Q
8: OP := _CMP_EQ_UQ
9: OP := _CMP_NGE_US
10: OP := _CMP_NGT_US
11: OP := _CMP_FALSE_OQ
12: OP := _CMP_NEQ_OQ
13: OP := _CMP_GE_OS
14: OP := _CMP_GT_OS
15: OP := _CMP_TRUE_UQ
16: OP := _CMP_EQ_OS
17: OP := _CMP_LT_OQ
18: OP := _CMP_LE_OQ
19: OP := _CMP_UNORD_S
20: OP := _CMP_NEQ_US
21: OP := _CMP_NLT_UQ
22: OP := _CMP_NLE_UQ
23: OP := _CMP_ORD_S
24: OP := _CMP_EQ_US
25: OP := _CMP_NGE_UQ
26: OP := _CMP_NGT_UQ
27: OP := _CMP_FALSE_OS
28: OP := _CMP_NEQ_OS
29: OP := _CMP_GE_OQ
30: OP := _CMP_GT_OQ
31: OP := _CMP_TRUE_US
ESAC
FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := ( a[i+31:i] OP b[i+31:i] ) ? 0xFFFFFFFF : 0
ENDFOR
dst[MAX:128] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 1 | 2
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 4 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 4 | 0.5 |


_mm_cmp_sd

__m128d _mm_cmp_sd( __m128d a, __m128d b, const int imm8 )

Synopsis

#include "immintrin.h"
Instruction: vcmpsd
CPUID Flag: AVX
Category: Compare

Description

Compare the lower double-precision (64-bit) floating-point element in "a" and "b" based on the comparison operand specified by "imm8", store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".

Operation

CASE (imm8[7:0]) OF
0: OP := _CMP_EQ_OQ
1: OP := _CMP_LT_OS
2: OP := _CMP_LE_OS
3: OP := _CMP_UNORD_Q
4: OP := _CMP_NEQ_UQ
5: OP := _CMP_NLT_US
6: OP := _CMP_NLE_US
7: OP := _CMP_ORD_Q
8: OP := _CMP_EQ_UQ
9: OP := _CMP_NGE_US
10: OP := _CMP_NGT_US
11: OP := _CMP_FALSE_OQ
12: OP := _CMP_NEQ_OQ
13: OP := _CMP_GE_OS
14: OP := _CMP_GT_OS
15: OP := _CMP_TRUE_UQ
16: OP := _CMP_EQ_OS
17: OP := _CMP_LT_OQ
18: OP := _CMP_LE_OQ
19: OP := _CMP_UNORD_S
20: OP := _CMP_NEQ_US
21: OP := _CMP_NLT_UQ
22: OP := _CMP_NLE_UQ
23: OP := _CMP_ORD_S
24: OP := _CMP_EQ_US
25: OP := _CMP_NGE_UQ
26: OP := _CMP_NGT_UQ
27: OP := _CMP_FALSE_OS
28: OP := _CMP_NEQ_OS
29: OP := _CMP_GE_OQ
30: OP := _CMP_GT_OQ
31: OP := _CMP_TRUE_US
ESAC
dst[63:0] := ( a[63:0] OP b[63:0] ) ? 0xFFFFFFFFFFFFFFFF : 0
dst[127:64] := a[127:64]
dst[MAX:128] := 0

Performance

Architecture | Latency | Throughput | μops
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 4 | 0.5 | 1


_mm_cmp_ss

__m128 _mm_cmp_ss( __m128 a, __m128 b, const int imm8 )

Synopsis

#include "immintrin.h"
Instruction: vcmpss
CPUID Flag: AVX
Category: Compare

Description

Compare the lower single-precision (32-bit) floating-point element in "a" and "b" based on the comparison operand specified by "imm8", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".

Operation

CASE (imm8[7:0]) OF
0: OP := _CMP_EQ_OQ
1: OP := _CMP_LT_OS
2: OP := _CMP_LE_OS
3: OP := _CMP_UNORD_Q
4: OP := _CMP_NEQ_UQ
5: OP := _CMP_NLT_US
6: OP := _CMP_NLE_US
7: OP := _CMP_ORD_Q
8: OP := _CMP_EQ_UQ
9: OP := _CMP_NGE_US
10: OP := _CMP_NGT_US
11: OP := _CMP_FALSE_OQ
12: OP := _CMP_NEQ_OQ
13: OP := _CMP_GE_OS
14: OP := _CMP_GT_OS
15: OP := _CMP_TRUE_UQ
16: OP := _CMP_EQ_OS
17: OP := _CMP_LT_OQ
18: OP := _CMP_LE_OQ
19: OP := _CMP_UNORD_S
20: OP := _CMP_NEQ_US
21: OP := _CMP_NLT_UQ
22: OP := _CMP_NLE_UQ
23: OP := _CMP_ORD_S
24: OP := _CMP_EQ_US
25: OP := _CMP_NGE_UQ
26: OP := _CMP_NGT_UQ
27: OP := _CMP_FALSE_OS
28: OP := _CMP_NEQ_OS
29: OP := _CMP_GE_OQ
30: OP := _CMP_GT_OQ
31: OP := _CMP_TRUE_US
ESAC
dst[31:0] := ( a[31:0] OP b[31:0] ) ? 0xFFFFFFFF : 0
dst[127:32] := a[127:32]
dst[MAX:128] := 0

Performance

Architecture | Latency | Throughput | μops
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 4 | 0.5 | 1


_mm_cmpeq_epi16

__m128i _mm_cmpeq_epi16( __m128i a, __m128i b )

Synopsis

#include "emmintrin.h"
Instruction: pcmpeqw
CPUID Flag: SSE2
Category: Compare

Description

Compare packed 16-bit integers in "a" and "b" for equality, and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*16
    dst[i+15:i] := ( a[i+15:i] == b[i+15:i] ) ? 0xFFFF : 0
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.5 |


_mm_cmpeq_epi32

__m128i _mm_cmpeq_epi32( __m128i a, __m128i b )

Synopsis

#include "emmintrin.h"
Instruction: pcmpeqd
CPUID Flag: SSE2
Category: Compare

Description

Compare packed 32-bit integers in "a" and "b" for equality, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := ( a[i+31:i] == b[i+31:i] ) ? 0xFFFFFFFF : 0
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.5 |


_mm_cmpeq_epi64

__m128i _mm_cmpeq_epi64( __m128i a, __m128i b )

Synopsis

#include "smmintrin.h"
Instruction: pcmpeqq
CPUID Flag: SSE4.1
Category: Compare

Description

Compare packed 64-bit integers in "a" and "b" for equality, and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*64
    dst[i+63:i] := ( a[i+63:i] == b[i+63:i] ) ? 0xFFFFFFFFFFFFFFFF : 0
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.5 | 1
Knights Landing | 2 | 2 | 1
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.5 |


_mm_cmpeq_epi8

__m128i _mm_cmpeq_epi8( __m128i a, __m128i b )

Synopsis

#include "emmintrin.h"
Instruction: pcmpeqb
CPUID Flag: SSE2
Category: Compare

Description

Compare packed 8-bit integers in "a" and "b" for equality, and store the results in "dst".

Operation

FOR j := 0 to 15
    i := j*8
    dst[i+7:i] := ( a[i+7:i] == b[i+7:i] ) ? 0xFF : 0
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.5 |


_mm_cmpeq_pd

__m128d _mm_cmpeq_pd( __m128d a, __m128d b )

Synopsis

#include "emmintrin.h"
Instruction: cmppd
CPUID Flag: SSE2
Category: Compare

Description

Compare packed double-precision (64-bit) floating-point elements in "a" and "b" for equality, and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*64
    dst[i+63:i] := (a[i+63:i] == b[i+63:i]) ? 0xFFFFFFFFFFFFFFFF : 0
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 1 | 1
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 4 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 4 | 0.5 |


_mm_cmpeq_pi16

__m64 _mm_cmpeq_pi16( __m64 a, __m64 b )

Synopsis

#include "mmintrin.h"
Instruction: pcmpeqw
CPUID Flag: MMX
Category: Compare

Description

Compare packed 16-bit integers in "a" and "b" for equality, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*16
    dst[i+15:i] := ( a[i+15:i] == b[i+15:i] ) ? 0xFFFF : 0
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1


_mm_cmpeq_pi32

__m64 _mm_cmpeq_pi32( __m64 a, __m64 b )

Synopsis

#include "mmintrin.h"
Instruction: pcmpeqd
CPUID Flag: MMX
Category: Compare

Description

Compare packed 32-bit integers in "a" and "b" for equality, and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*32
    dst[i+31:i] := ( a[i+31:i] == b[i+31:i] ) ? 0xFFFFFFFF : 0
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1


_mm_cmpeq_pi8

__m64 _mm_cmpeq_pi8( __m64 a, __m64 b )

Synopsis

#include "mmintrin.h"
Instruction: pcmpeqb
CPUID Flag: MMX
Category: Compare

Description

Compare packed 8-bit integers in "a" and "b" for equality, and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*8
    dst[i+7:i] := ( a[i+7:i] == b[i+7:i] ) ? 0xFF : 0
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1


_mm_cmpeq_ps

__m128 _mm_cmpeq_ps( __m128 a, __m128 b )

Synopsis

#include "xmmintrin.h"
Instruction: cmpps
CPUID Flag: SSE
Category: Compare

Description

Compare packed single-precision (32-bit) floating-point elements in "a" and "b" for equality, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := ( a[i+31:i] == b[i+31:i] ) ? 0xffffffff : 0
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 1 | 1
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 4 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 4 | 0.5 |


_mm_cmpeq_sd

__m128d _mm_cmpeq_sd( __m128d a, __m128d b )

Synopsis

#include "emmintrin.h"
Instruction: cmpsd
CPUID Flag: SSE2
Category: Compare

Description

Compare the lower double-precision (64-bit) floating-point elements in "a" and "b" for equality, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".

Operation

dst[63:0] := (a[63:0] == b[63:0]) ? 0xFFFFFFFFFFFFFFFF : 0
dst[127:64] := a[127:64]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 1 | 1
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 4 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 4 | 0.5 |


_mm_cmpeq_ss

__m128 _mm_cmpeq_ss( __m128 a, __m128 b )

Synopsis

#include "xmmintrin.h"
Instruction: cmpss
CPUID Flag: SSE
Category: Compare

Description

Compare the lower single-precision (32-bit) floating-point elements in "a" and "b" for equality, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".

Operation

dst[31:0] := ( a[31:0] == b[31:0] ) ? 0xffffffff : 0
dst[127:32] := a[127:32]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 1 | 1
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 4 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 4 | 0.5 |


_mm_cmpestra

int _mm_cmpestra( __m128i a, int la, __m128i b, int lb, const int imm8 )

Synopsis

#include "nmmintrin.h"
Instruction: pcmpestri
CPUID Flag: SSE4.2
Category: String Compare

Description

Compare packed strings in "a" and "b" with lengths "la" and "lb" using the control in "imm8", and returns 1 if "b" did not contain a null character and the resulting mask was zero, and 0 otherwise. [strcmp_note]

Operation

size := (imm8[0] ? 16 : 8) // 8 or 16-bit characters
UpperBound := (128 / size) - 1
// compare all characters
aInvalid := 0
bInvalid := 0
FOR i := 0 to UpperBound
    m := i*size
    FOR j := 0 to UpperBound
        n := j*size
        BoolRes[i][j] := (a[m+size-1:m] == b[n+size-1:n])

        // invalidate characters after EOS
        IF i == la
            aInvalid := 1
        FI
        IF j == lb
            bInvalid := 1
        FI

        // override comparisons for invalid characters
        CASE (imm8[3:2]) OF
        0:  // equal any
            IF (!aInvalid && bInvalid)
                BoolRes[i][j] := 0
            ELSE IF (aInvalid && !bInvalid)
                BoolRes[i][j] := 0
            ELSE IF (aInvalid && bInvalid)
                BoolRes[i][j] := 0
            FI
        1:  // ranges
            IF (!aInvalid && bInvalid)
                BoolRes[i][j] := 0
            ELSE IF (aInvalid && !bInvalid)
                BoolRes[i][j] := 0
            ELSE IF (aInvalid && bInvalid)
                BoolRes[i][j] := 0
            FI
        2:  // equal each
            IF (!aInvalid && bInvalid)
                BoolRes[i][j] := 0
            ELSE IF (aInvalid && !bInvalid)
                BoolRes[i][j] := 0
            ELSE IF (aInvalid && bInvalid)
                BoolRes[i][j] := 1
            FI
        3:  // equal ordered
            IF (!aInvalid && bInvalid)
                BoolRes[i][j] := 0
            ELSE IF (aInvalid && !bInvalid)
                BoolRes[i][j] := 1
            ELSE IF (aInvalid && bInvalid)
                BoolRes[i][j] := 1
            FI
        ESAC
    ENDFOR
ENDFOR
// aggregate results
CASE (imm8[3:2]) OF
0:  // equal any
    IntRes1 := 0
    FOR i := 0 to UpperBound
        FOR j := 0 to UpperBound
            IntRes1[i] := IntRes1[i] OR BoolRes[i][j]
        ENDFOR
    ENDFOR
1:  // ranges
    IntRes1 := 0
    FOR i := 0 to UpperBound
        FOR j := 0 to UpperBound, j += 2
            IntRes1[i] := IntRes1[i] OR (BoolRes[i][j] AND BoolRes[i][j+1])
        ENDFOR
    ENDFOR
2:  // equal each
    IntRes1 := 0
    FOR i := 0 to UpperBound
        IntRes1[i] := BoolRes[i][i]
    ENDFOR
3:  // equal ordered
    IntRes1 := (imm8[0] ? 0xFF : 0xFFFF)
    FOR i := 0 to UpperBound
        k := i
        FOR j := 0 to UpperBound-i
            IntRes1[i] := IntRes1[i] AND BoolRes[k][j]
            k := k+1
        ENDFOR
    ENDFOR
ESAC
// optionally negate results
FOR i := 0 to UpperBound
    IF imm8[4]
        IF imm8[5] // only negate valid
            IF i >= lb // invalid, don't negate
                IntRes2[i] := IntRes1[i]
            ELSE // valid, negate
                IntRes2[i] := -1 XOR IntRes1[i]
            FI
        ELSE // negate all
            IntRes2[i] := -1 XOR IntRes1[i]
        FI
    ELSE // don't negate
        IntRes2[i] := IntRes1[i]
    FI
ENDFOR
// output
dst := (IntRes2 == 0) AND (lb > UpperBound)

Performance

Architecture | Latency | Throughput | μops
Ryzen | 8 | 3 | 6
Jaguar | 5 | 5 | 9
Sandy Bridge | 4 | 4 | 8
Ivy Bridge | 4 | 4 | 8
Haswell | 11 | 4 | 8
Broadwell | 4 | 4 | 8
Skylake | 12 | 4 | 8
Knights Landing | 21 | 21 | 9
Ivy Bridge | 11 | 4 |
Haswell | 10 | 4 |
Broadwell | 10 | 4 |
Skylake | 15 | 5 |


_mm_cmpestrc

int _mm_cmpestrc( __m128i a, int la, __m128i b, int lb, const int imm8 )

Synopsis

#include "nmmintrin.h"
Instruction: pcmpestri
CPUID Flag: SSE4.2
Category: String Compare

Description

Compare packed strings in "a" and "b" with lengths "la" and "lb" using the control in "imm8", and returns 1 if the resulting mask was non-zero, and 0 otherwise. [strcmp_note]

Operation

size := (imm8[0] ? 16 : 8) // 8 or 16-bit characters
UpperBound := (128 / size) - 1
// compare all characters
aInvalid := 0
bInvalid := 0
FOR i := 0 to UpperBound
    m := i*size
    FOR j := 0 to UpperBound
        n := j*size
        BoolRes[i][j] := (a[m+size-1:m] == b[n+size-1:n])

        // invalidate characters after EOS
        IF i == la
            aInvalid := 1
        FI
        IF j == lb
            bInvalid := 1
        FI

        // override comparisons for invalid characters
        CASE (imm8[3:2]) OF
        0:  // equal any
            IF (!aInvalid && bInvalid)
                BoolRes[i][j] := 0
            ELSE IF (aInvalid && !bInvalid)
                BoolRes[i][j] := 0
            ELSE IF (aInvalid && bInvalid)
                BoolRes[i][j] := 0
            FI
        1:  // ranges
            IF (!aInvalid && bInvalid)
                BoolRes[i][j] := 0
            ELSE IF (aInvalid && !bInvalid)
                BoolRes[i][j] := 0
            ELSE IF (aInvalid && bInvalid)
                BoolRes[i][j] := 0
            FI
        2:  // equal each
            IF (!aInvalid && bInvalid)
                BoolRes[i][j] := 0
            ELSE IF (aInvalid && !bInvalid)
                BoolRes[i][j] := 0
            ELSE IF (aInvalid && bInvalid)
                BoolRes[i][j] := 1
            FI
        3:  // equal ordered
            IF (!aInvalid && bInvalid)
                BoolRes[i][j] := 0
            ELSE IF (aInvalid && !bInvalid)
                BoolRes[i][j] := 1
            ELSE IF (aInvalid && bInvalid)
                BoolRes[i][j] := 1
            FI
        ESAC
    ENDFOR
ENDFOR
// aggregate results
CASE (imm8[3:2]) OF
0:  // equal any
    IntRes1 := 0
    FOR i := 0 to UpperBound
        FOR j := 0 to UpperBound
            IntRes1[i] := IntRes1[i] OR BoolRes[i][j]
        ENDFOR
    ENDFOR
1:  // ranges
    IntRes1 := 0
    FOR i := 0 to UpperBound
        FOR j := 0 to UpperBound, j += 2
            IntRes1[i] := IntRes1[i] OR (BoolRes[i][j] AND BoolRes[i][j+1])
        ENDFOR
    ENDFOR
2:  // equal each
    IntRes1 := 0
    FOR i := 0 to UpperBound
        IntRes1[i] := BoolRes[i][i]
    ENDFOR
3:  // equal ordered
    IntRes1 := (imm8[0] ? 0xFF : 0xFFFF)
    FOR i := 0 to UpperBound
        k := i
        FOR j := 0 to UpperBound-i
            IntRes1[i] := IntRes1[i] AND BoolRes[k][j]
            k := k+1
        ENDFOR
    ENDFOR
ESAC
// optionally negate results
FOR i := 0 to UpperBound
    IF imm8[4]
        IF imm8[5] // only negate valid
            IF i >= lb // invalid, don't negate
                IntRes2[i] := IntRes1[i]
            ELSE // valid, negate
                IntRes2[i] := -1 XOR IntRes1[i]
            FI
        ELSE // negate all
            IntRes2[i] := -1 XOR IntRes1[i]
        FI
    ELSE // don't negate
        IntRes2[i] := IntRes1[i]
    FI
ENDFOR
// output
dst := (IntRes2 != 0)

Performance

Architecture | Latency | Throughput | μops
Ryzen | 8 | 3 | 6
Jaguar | 5 | 5 | 9
Sandy Bridge | 4 | 4 | 8
Ivy Bridge | 4 | 4 | 8
Haswell | 11 | 4 | 8
Broadwell | 4 | 4 | 8
Skylake | 12 | 4 | 8
Knights Landing | 21 | 21 | 9
Ivy Bridge | 11 | 4 |
Haswell | 10 | 4 |
Broadwell | 10 | 4 |
Skylake | 15 | 5 |


_mm_cmpestri

int _mm_cmpestri( __m128i a, int la, __m128i b, int lb, const int imm8 )

Synopsis

#include "nmmintrin.h"
Instruction: pcmpestri
CPUID Flag: SSE4.2
Category: String Compare

Description

Compare packed strings in "a" and "b" with lengths "la" and "lb" using the control in "imm8", and store the generated index in "dst". [strcmp_note]

Operation

size := (imm8[0] ? 16 : 8) // 8 or 16-bit characters
UpperBound := (128 / size) - 1
// compare all characters
aInvalid := 0
bInvalid := 0
FOR i := 0 to UpperBound
    m := i*size
    FOR j := 0 to UpperBound
        n := j*size
        BoolRes[i][j] := (a[m+size-1:m] == b[n+size-1:n])

        // invalidate characters after EOS
        IF i == la
            aInvalid := 1
        FI
        IF j == lb
            bInvalid := 1
        FI

        // override comparisons for invalid characters
        CASE (imm8[3:2]) OF
        0:  // equal any
            IF (!aInvalid && bInvalid)
                BoolRes[i][j] := 0
            ELSE IF (aInvalid && !bInvalid)
                BoolRes[i][j] := 0
            ELSE IF (aInvalid && bInvalid)
                BoolRes[i][j] := 0
            FI
        1:  // ranges
            IF (!aInvalid && bInvalid)
                BoolRes[i][j] := 0
            ELSE IF (aInvalid && !bInvalid)
                BoolRes[i][j] := 0
            ELSE IF (aInvalid && bInvalid)
                BoolRes[i][j] := 0
            FI
        2:  // equal each
            IF (!aInvalid && bInvalid)
                BoolRes[i][j] := 0
            ELSE IF (aInvalid && !bInvalid)
                BoolRes[i][j] := 0
            ELSE IF (aInvalid && bInvalid)
                BoolRes[i][j] := 1
            FI
        3:  // equal ordered
            IF (!aInvalid && bInvalid)
                BoolRes[i][j] := 0
            ELSE IF (aInvalid && !bInvalid)
                BoolRes[i][j] := 1
            ELSE IF (aInvalid && bInvalid)
                BoolRes[i][j] := 1
            FI
        ESAC
    ENDFOR
ENDFOR
// aggregate results
CASE (imm8[3:2]) OF
0:  // equal any
    IntRes1 := 0
    FOR i := 0 to UpperBound
        FOR j := 0 to UpperBound
            IntRes1[i] := IntRes1[i] OR BoolRes[i][j]
        ENDFOR
    ENDFOR
1:  // ranges
    IntRes1 := 0
    FOR i := 0 to UpperBound
        FOR j := 0 to UpperBound, j += 2
            IntRes1[i] := IntRes1[i] OR (BoolRes[i][j] AND BoolRes[i][j+1])
        ENDFOR
    ENDFOR
2:  // equal each
    IntRes1 := 0
    FOR i := 0 to UpperBound
        IntRes1[i] := BoolRes[i][i]
    ENDFOR
3:  // equal ordered
    IntRes1 := (imm8[0] ? 0xFF : 0xFFFF)
    FOR i := 0 to UpperBound
        k := i
        FOR j := 0 to UpperBound-i
            IntRes1[i] := IntRes1[i] AND BoolRes[k][j]
            k := k+1
        ENDFOR
    ENDFOR
ESAC
// optionally negate results
FOR i := 0 to UpperBound
    IF imm8[4]
        IF imm8[5] // only negate valid
            IF i >= lb // invalid, don't negate
                IntRes2[i] := IntRes1[i]
            ELSE // valid, negate
                IntRes2[i] := -1 XOR IntRes1[i]
            FI
        ELSE // negate all
            IntRes2[i] := -1 XOR IntRes1[i]
        FI
    ELSE // don't negate
        IntRes2[i] := IntRes1[i]
    FI
ENDFOR
// output
IF imm8[6] // most significant bit
    tmp := UpperBound
    dst := tmp
    DO WHILE ((tmp >= 0) AND a[tmp] == 0)
        tmp := tmp - 1
        dst := tmp
    OD
ELSE // least significant bit
    tmp := 0
    dst := tmp
    DO WHILE ((tmp <= UpperBound) AND a[tmp] == 0)
        tmp := tmp + 1
        dst := tmp
    OD
FI

Performance

Architecture | Latency | Throughput | μops
Ryzen | 8 | 3 | 6
Jaguar | 5 | 5 | 9
Sandy Bridge | 4 | 4 | 8
Ivy Bridge | 4 | 4 | 8
Haswell | 11 | 4 | 8
Broadwell | 4 | 4 | 8
Skylake | 12 | 4 | 8
Knights Landing | 21 | 21 | 9
Ivy Bridge | 11 | 4 |
Haswell | 10 | 4 |
Broadwell | 10 | 4 |
Skylake | 15 | 5 |


_mm_cmpestrm

__m128i _mm_cmpestrm( __m128i a, int la, __m128i b, int lb, const int imm8 )

Synopsis

#include "nmmintrin.h"
Instruction: pcmpestrm
CPUID Flag: SSE4.2
Category: String Compare

Description

Compare packed strings in "a" and "b" with lengths "la" and "lb" using the control in "imm8", and store the generated mask in "dst". [strcmp_note]

Operation

size := (imm8[0] ? 16 : 8) // 8 or 16-bit characters
UpperBound := (128 / size) - 1
// compare all characters
aInvalid := 0
bInvalid := 0
FOR i := 0 to UpperBound
    m := i*size
    FOR j := 0 to UpperBound
        n := j*size
        BoolRes[i][j] := (a[m+size-1:m] == b[n+size-1:n])

        // invalidate characters after EOS
        IF i == la
            aInvalid := 1
        FI
        IF j == lb
            bInvalid := 1
        FI

        // override comparisons for invalid characters
        CASE (imm8[3:2]) OF
        0:  // equal any
            IF (!aInvalid && bInvalid)
                BoolRes[i][j] := 0
            ELSE IF (aInvalid && !bInvalid)
                BoolRes[i][j] := 0
            ELSE IF (aInvalid && bInvalid)
                BoolRes[i][j] := 0
            FI
        1:  // ranges
            IF (!aInvalid && bInvalid)
                BoolRes[i][j] := 0
            ELSE IF (aInvalid && !bInvalid)
                BoolRes[i][j] := 0
            ELSE IF (aInvalid && bInvalid)
                BoolRes[i][j] := 0
            FI
        2:  // equal each
            IF (!aInvalid && bInvalid)
                BoolRes[i][j] := 0
            ELSE IF (aInvalid && !bInvalid)
                BoolRes[i][j] := 0
            ELSE IF (aInvalid && bInvalid)
                BoolRes[i][j] := 1
            FI
        3:  // equal ordered
            IF (!aInvalid && bInvalid)
                BoolRes[i][j] := 0
            ELSE IF (aInvalid && !bInvalid)
                BoolRes[i][j] := 1
            ELSE IF (aInvalid && bInvalid)
                BoolRes[i][j] := 1
            FI
        ESAC
    ENDFOR
ENDFOR
// aggregate results
CASE (imm8[3:2]) OF
0:  // equal any
    IntRes1 := 0
    FOR i := 0 to UpperBound
        FOR j := 0 to UpperBound
            IntRes1[i] := IntRes1[i] OR BoolRes[i][j]
        ENDFOR
    ENDFOR
1:  // ranges
    IntRes1 := 0
    FOR i := 0 to UpperBound
        FOR j := 0 to UpperBound, j += 2
            IntRes1[i] := IntRes1[i] OR (BoolRes[i][j] AND BoolRes[i][j+1])
        ENDFOR
    ENDFOR
2:  // equal each
    IntRes1 := 0
    FOR i := 0 to UpperBound
        IntRes1[i] := BoolRes[i][i]
    ENDFOR
3:  // equal ordered
    IntRes1 := (imm8[0] ? 0xFF : 0xFFFF)
    FOR i := 0 to UpperBound
        k := i
        FOR j := 0 to UpperBound-i
            IntRes1[i] := IntRes1[i] AND BoolRes[k][j]
            k := k+1
        ENDFOR
    ENDFOR
ESAC
// optionally negate results
FOR i := 0 to UpperBound
    IF imm8[4]
        IF imm8[5] // only negate valid
            IF i >= lb // invalid, don't negate
                IntRes2[i] := IntRes1[i]
            ELSE // valid, negate
                IntRes2[i] := -1 XOR IntRes1[i]
            FI
        ELSE // negate all
            IntRes2[i] := -1 XOR IntRes1[i]
        FI
    ELSE // don't negate
        IntRes2[i] := IntRes1[i]
    FI
ENDFOR
// output
IF imm8[6] // byte / word mask
    FOR i := 0 to UpperBound
        j := i*size
        IF IntRes2[i]
            dst[j+size-1:j] := (imm8[0] ? 0xFF : 0xFFFF)
        ELSE
            dst[j+size-1:j] := 0
        FI
    ENDFOR
ELSE // bit mask
    dst[UpperBound:0] := IntRes2[UpperBound:0]
    dst[127:UpperBound+1] := 0
FI

Performance

Architecture | Latency | Throughput | μops
Ryzen | 8 | 3 | 7
Jaguar | 9 | 9 | 9
Sandy Bridge | 11-12 | 4 | 8
Ivy Bridge | 12 | 4 | 8
Haswell | 10 | 5 | 9
Broadwell | 11 | 11 | 9
Skylake | 9 | 5 | 9
Knights Landing | 17 | 17 | 8
Ivy Bridge | 11 | 4 |
Haswell | 10 | 5 |
Broadwell | 10 | 5 |
Skylake | 10 | 6 |


_mm_cmpestro

int _mm_cmpestro( __m128i a, int la, __m128i b, int lb, const int imm8 )

Synopsis

#include "nmmintrin.h"
Instruction: pcmpestri
CPUID Flag: SSE4.2
Category: String Compare

Description

Compare packed strings in "a" and "b" with lengths "la" and "lb" using the control in "imm8", and returns bit 0 of the resulting bit mask. [strcmp_note]

Operation

size := (imm8[0] ? 16 : 8) // 8 or 16-bit characters
UpperBound := (128 / size) - 1
// compare all characters
aInvalid := 0
bInvalid := 0
FOR i := 0 to UpperBound
    m := i*size
    FOR j := 0 to UpperBound
        n := j*size
        BoolRes[i][j] := (a[m+size-1:m] == b[n+size-1:n])

        // invalidate characters after EOS
        IF i == la
            aInvalid := 1
        FI
        IF j == lb
            bInvalid := 1
        FI

        // override comparisons for invalid characters
        CASE (imm8[3:2]) OF
        0:  // equal any
            IF (!aInvalid && bInvalid)
                BoolRes[i][j] := 0
            ELSE IF (aInvalid && !bInvalid)
                BoolRes[i][j] := 0
            ELSE IF (aInvalid && bInvalid)
                BoolRes[i][j] := 0
            FI
        1:  // ranges
            IF (!aInvalid && bInvalid)
                BoolRes[i][j] := 0
            ELSE IF (aInvalid && !bInvalid)
                BoolRes[i][j] := 0
            ELSE IF (aInvalid && bInvalid)
                BoolRes[i][j] := 0
            FI
        2:  // equal each
            IF (!aInvalid && bInvalid)
                BoolRes[i][j] := 0
            ELSE IF (aInvalid && !bInvalid)
                BoolRes[i][j] := 0
            ELSE IF (aInvalid && bInvalid)
                BoolRes[i][j] := 1
            FI
        3:  // equal ordered
            IF (!aInvalid && bInvalid)
                BoolRes[i][j] := 0
            ELSE IF (aInvalid && !bInvalid)
                BoolRes[i][j] := 1
            ELSE IF (aInvalid && bInvalid)
                BoolRes[i][j] := 1
            FI
        ESAC
    ENDFOR
ENDFOR
// aggregate results
CASE (imm8[3:2]) OF
0:  // equal any
    IntRes1 := 0
    FOR i := 0 to UpperBound
        FOR j := 0 to UpperBound
            IntRes1[i] := IntRes1[i] OR BoolRes[i][j]
        ENDFOR
    ENDFOR
1:  // ranges
    IntRes1 := 0
    FOR i := 0 to UpperBound
        FOR j := 0 to UpperBound, j += 2
            IntRes1[i] := IntRes1[i] OR (BoolRes[i][j] AND BoolRes[i][j+1])
        ENDFOR
    ENDFOR
2:  // equal each
    IntRes1 := 0
    FOR i := 0 to UpperBound
        IntRes1[i] := BoolRes[i][i]
    ENDFOR
3:  // equal ordered
    IntRes1 := (imm8[0] ? 0xFF : 0xFFFF)
    FOR i := 0 to UpperBound
        k := i
        FOR j := 0 to UpperBound-i
            IntRes1[i] := IntRes1[i] AND BoolRes[k][j]
            k := k+1
        ENDFOR
    ENDFOR
ESAC
// optionally negate results
FOR i := 0 to UpperBound
    IF imm8[4]
        IF imm8[5] // only negate valid
            IF i >= lb // invalid, don't negate
                IntRes2[i] := IntRes1[i]
            ELSE // valid, negate
                IntRes2[i] := -1 XOR IntRes1[i]
            FI
        ELSE // negate all
            IntRes2[i] := -1 XOR IntRes1[i]
        FI
    ELSE // don't negate
        IntRes2[i] := IntRes1[i]
    FI
ENDFOR
// output
dst := IntRes2[0]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 8 | 3 | 6
Jaguar | 5 | 5 | 9
Sandy Bridge | 4 | 4 | 8
Ivy Bridge | 4 | 4 | 8
Haswell | 11 | 4 | 8
Broadwell | 4 | 4 | 8
Skylake | 12 | 4 | 8
Knights Landing | 21 | 21 | 9
Ivy Bridge | 11 | 4 |
Haswell | 10 | 4 |
Broadwell | 10 | 4 |
Skylake | 15 | 5 |


_mm_cmpestrs

int _mm_cmpestrs( __m128i a, int la, __m128i b, int lb, const int imm8 )

Synopsis

#include "nmmintrin.h"
Instruction: pcmpestri
CPUID Flag: SSE4.2
Category: String Compare

Description

Compare packed strings in "a" and "b" with lengths "la" and "lb" using the control in "imm8", and returns 1 if any character in "a" was null, and 0 otherwise. [strcmp_note]

Operation

size := (imm8[0] ? 16 : 8) // 8 or 16-bit characters
UpperBound := (128 / size) - 1
dst := (la <= UpperBound)

Performance

Architecture | Latency | Throughput | μops
Ryzen | 8 | 3 | 6
Jaguar | 5 | 5 | 9
Sandy Bridge | 4 | 4 | 8
Ivy Bridge | 4 | 4 | 8
Haswell | 11 | 4 | 8
Broadwell | 4 | 4 | 8
Skylake | 12 | 4 | 8
Knights Landing | 21 | 21 | 9
Ivy Bridge | 11 | 4 |
Haswell | 10 | 4 |
Broadwell | 10 | 4 |
Skylake | 15 | 5 |


_mm_cmpestrz

int _mm_cmpestrz( __m128i a, int la, __m128i b, int lb, const int imm8 )

Synopsis

#include "nmmintrin.h"
Instruction: pcmpestri
CPUID Flag: SSE4.2
Category: String Compare

Description

Compare packed strings in "a" and "b" with lengths "la" and "lb" using the control in "imm8", and returns 1 if any character in "b" was null, and 0 otherwise. [strcmp_note]

Operation

size := (imm8[0] ? 16 : 8) // 8 or 16-bit characters
UpperBound := (128 / size) - 1
dst := (lb <= UpperBound)

Performance

Architecture | Latency | Throughput | μops
Ryzen | 8 | 3 | 6
Jaguar | 5 | 5 | 9
Sandy Bridge | 4 | 4 | 8
Ivy Bridge | 4 | 4 | 8
Haswell | 11 | 4 | 8
Broadwell | 4 | 4 | 8
Skylake | 12 | 4 | 8
Knights Landing | 21 | 21 | 9
Ivy Bridge | 11 | 4 |
Haswell | 10 | 4 |
Broadwell | 10 | 4 |
Skylake | 15 | 5 |


_mm_cmpge_pd

__m128d _mm_cmpge_pd( __m128d a, __m128d b )

Synopsis

#include "emmintrin.h"
Instruction: cmppd
CPUID Flag: SSE2
Category: Compare

Description

Compare packed double-precision (64-bit) floating-point elements in "a" and "b" for greater-than-or-equal, and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*64
    dst[i+63:i] := (a[i+63:i] >= b[i+63:i]) ? 0xFFFFFFFFFFFFFFFF : 0
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 1 | 1
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 4 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 4 | 0.5 |


_mm_cmpge_ps

__m128 _mm_cmpge_ps( __m128 a, __m128 b )

Synopsis

#include "xmmintrin.h"
Instruction: cmpps
CPUID Flag: SSE
Category: Compare

Description

Compare packed single-precision (32-bit) floating-point elements in "a" and "b" for greater-than-or-equal, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := ( a[i+31:i] >= b[i+31:i] ) ? 0xffffffff : 0
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 1 | 1
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 4 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 4 | 0.5 |


_mm_cmpge_sd

__m128d _mm_cmpge_sd( __m128d a, __m128d b )

Synopsis

#include "emmintrin.h"
Instruction: cmpsd
CPUID Flag: SSE2
Category: Compare

Description

Compare the lower double-precision (64-bit) floating-point elements in "a" and "b" for greater-than-or-equal, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".

Operation

dst[63:0] := (a[63:0] >= b[63:0]) ? 0xFFFFFFFFFFFFFFFF : 0
dst[127:64] := a[127:64]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 1 | 1
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 4 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 4 | 0.5 |


_mm_cmpge_ss

__m128 _mm_cmpge_ss( __m128 a, __m128 b )

Synopsis

#include "xmmintrin.h"
Instruction: cmpss
CPUID Flag: SSE
Category: Compare

Description

Compare the lower single-precision (32-bit) floating-point elements in "a" and "b" for greater-than-or-equal, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".

Operation

dst[31:0] := ( a[31:0] >= b[31:0] ) ? 0xffffffff : 0
dst[127:32] := a[127:32]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 1 | 1
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 4 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 4 | 0.5 |


_mm_cmpgt_epi16

__m128i _mm_cmpgt_epi16( __m128i a, __m128i b )

Synopsis

#include "emmintrin.h"
Instruction: pcmpgtw
CPUID Flag: SSE2
Category: Compare

Description

Compare packed 16-bit integers in "a" and "b" for greater-than, and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*16
    dst[i+15:i] := ( a[i+15:i] > b[i+15:i] ) ? 0xFFFF : 0
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.5 |


_mm_cmpgt_epi32

__m128i _mm_cmpgt_epi32( __m128i a, __m128i b )

Synopsis

#include "emmintrin.h"
Instruction: pcmpgtd
CPUID Flag: SSE2
Category: Compare

Description

Compare packed 32-bit integers in "a" and "b" for greater-than, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := ( a[i+31:i] > b[i+31:i] ) ? 0xFFFFFFFF : 0
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.5 |


_mm_cmpgt_epi64

__m128i _mm_cmpgt_epi64( __m128i a, __m128i b )

Synopsis

#include "nmmintrin.h"
Instruction: pcmpgtq
CPUID Flag: SSE4.2
Category: Compare

Description

Compare packed 64-bit integers in "a" and "b" for greater-than, and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*64
    dst[i+63:i] := ( a[i+63:i] > b[i+63:i] ) ? 0xFFFFFFFFFFFFFFFF : 0
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 1 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 5 | 1 | 1
Ivy Bridge | 5 | 1 | 1
Haswell | 5 | 1 | 1
Broadwell | 5 | 1 | 1
Skylake | 3 | 1 | 1
Knights Landing | 2 | 2 | 1
Ivy Bridge | 5 | 1 |
Haswell | 5 | 1 |
Broadwell | 5 | 1 |
Skylake | 3 | 0.33 |


_mm_cmpgt_epi8

__m128i _mm_cmpgt_epi8( __m128i a, __m128i b )

Synopsis

#include "emmintrin.h"
Instruction: pcmpgtb
CPUID Flag: SSE2
Category: Compare

Description

Compare packed 8-bit integers in "a" and "b" for greater-than, and store the results in "dst".

Operation

FOR j := 0 to 15
    i := j*8
    dst[i+7:i] := ( a[i+7:i] > b[i+7:i] ) ? 0xFF : 0
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.5 |


_mm_cmpgt_pd

__m128d _mm_cmpgt_pd( __m128d a, __m128d b )

Synopsis

#include "emmintrin.h"
Instruction: cmppd
CPUID Flag: SSE2
Category: Compare

Description

Compare packed double-precision (64-bit) floating-point elements in "a" and "b" for greater-than, and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*64
    dst[i+63:i] := (a[i+63:i] > b[i+63:i]) ? 0xFFFFFFFFFFFFFFFF : 0
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 1 | 1
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 4 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 4 | 0.5 |


_mm_cmpgt_pi16

__m64 _mm_cmpgt_pi16( __m64 a, __m64 b )

Synopsis

#include "mmintrin.h"
Instruction: pcmpgtw
CPUID Flag: MMX
Category: Compare

Description

Compare packed 16-bit integers in "a" and "b" for greater-than, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*16
    dst[i+15:i] := ( a[i+15:i] > b[i+15:i] ) ? 0xFFFF : 0
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1


_mm_cmpgt_pi32

__m64 _mm_cmpgt_pi32( __m64 a, __m64 b )

Synopsis

#include "mmintrin.h"
Instruction: pcmpgtd
CPUID Flag: MMX
Category: Compare

Description

Compare packed 32-bit integers in "a" and "b" for greater-than, and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*32
    dst[i+31:i] := ( a[i+31:i] > b[i+31:i] ) ? 0xFFFFFFFF : 0
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1


_mm_cmpgt_pi8

__m64 _mm_cmpgt_pi8( __m64 a, __m64 b )

Synopsis

#include "mmintrin.h"
Instruction: pcmpgtb
CPUID Flag: MMX
Category: Compare

Description

Compare packed 8-bit integers in "a" and "b" for greater-than, and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*8
    dst[i+7:i] := ( a[i+7:i] > b[i+7:i] ) ? 0xFF : 0
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1


_mm_cmpgt_ps

__m128 _mm_cmpgt_ps( __m128 a, __m128 b )

Synopsis

#include "xmmintrin.h"
Instruction: cmpps
CPUID Flag: SSE
Category: Compare

Description

Compare packed single-precision (32-bit) floating-point elements in "a" and "b" for greater-than, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := ( a[i+31:i] > b[i+31:i] ) ? 0xffffffff : 0
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 1 | 1
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 4 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 4 | 0.5 |


_mm_cmpgt_sd

__m128d _mm_cmpgt_sd( __m128d a, __m128d b )

Synopsis

#include "emmintrin.h"
Instruction: cmpsd
CPUID Flag: SSE2
Category: Compare

Description

Compare the lower double-precision (64-bit) floating-point elements in "a" and "b" for greater-than, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".

Operation

dst[63:0] := (a[63:0] > b[63:0]) ? 0xFFFFFFFFFFFFFFFF : 0
dst[127:64] := a[127:64]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 1 | 1
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 4 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 4 | 0.5 |


_mm_cmpgt_ss

__m128 _mm_cmpgt_ss( __m128 a, __m128 b )

Synopsis

#include "xmmintrin.h"
Instruction: cmpss
CPUID Flag: SSE
Category: Compare

Description

Compare the lower single-precision (32-bit) floating-point elements in "a" and "b" for greater-than, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".

Operation

dst[31:0] := ( a[31:0] > b[31:0] ) ? 0xffffffff : 0
dst[127:32] := a[127:32]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 1 | 1
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 4 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 4 | 0.5 |


_mm_cmpistra

int _mm_cmpistra( __m128i a, __m128i b, const int imm8 )

Synopsis

#include "nmmintrin.h"
Instruction: pcmpistri
CPUID Flag: SSE4.2
Category: String Compare

Description

Compare packed strings with implicit lengths in "a" and "b" using the control in "imm8", and returns 1 if "b" did not contain a null character and the resulting mask was zero, and 0 otherwise. [strcmp_note]

Operation

size := (imm8[0] ? 16 : 8) // 8 or 16-bit characters
UpperBound := (128 / size) - 1
// compare all characters
aInvalid := 0
bInvalid := 0
FOR i := 0 to UpperBound
    m := i*size
    FOR j := 0 to UpperBound
        n := j*size
        BoolRes[i][j] := (a[m+size-1:m] == b[n+size-1:n])

        // invalidate characters after EOS
        IF a[m+size-1:m] == 0
            aInvalid := 1
        FI
        IF b[n+size-1:n] == 0
            bInvalid := 1
        FI

        // override comparisons for invalid characters
        CASE (imm8[3:2]) OF
        0:  // equal any
            IF (!aInvalid && bInvalid)
                BoolRes[i][j] := 0
            ELSE IF (aInvalid && !bInvalid)
                BoolRes[i][j] := 0
            ELSE IF (aInvalid && bInvalid)
                BoolRes[i][j] := 0
            FI
        1:  // ranges
            IF (!aInvalid && bInvalid)
                BoolRes[i][j] := 0
            ELSE IF (aInvalid && !bInvalid)
                BoolRes[i][j] := 0
            ELSE IF (aInvalid && bInvalid)
                BoolRes[i][j] := 0
            FI
        2:  // equal each
            IF (!aInvalid && bInvalid)
                BoolRes[i][j] := 0
            ELSE IF (aInvalid && !bInvalid)
                BoolRes[i][j] := 0
            ELSE IF (aInvalid && bInvalid)
                BoolRes[i][j] := 1
            FI
        3:  // equal ordered
            IF (!aInvalid && bInvalid)
                BoolRes[i][j] := 0
            ELSE IF (aInvalid && !bInvalid)
                BoolRes[i][j] := 1
            ELSE IF (aInvalid && bInvalid)
                BoolRes[i][j] := 1
            FI
        ESAC
    ENDFOR
ENDFOR
// aggregate results
CASE (imm8[3:2]) OF
0:  // equal any
    IntRes1 := 0
    FOR i := 0 to UpperBound
        FOR j := 0 to UpperBound
            IntRes1[i] := IntRes1[i] OR BoolRes[i][j]
        ENDFOR
    ENDFOR
1:  // ranges
    IntRes1 := 0
    FOR i := 0 to UpperBound
        FOR j := 0 to UpperBound, j += 2
            IntRes1[i] := IntRes1[i] OR (BoolRes[i][j] AND BoolRes[i][j+1])
        ENDFOR
    ENDFOR
2:  // equal each
    IntRes1 := 0
    FOR i := 0 to UpperBound
        IntRes1[i] := BoolRes[i][i]
    ENDFOR
3:  // equal ordered
    IntRes1 := (imm8[0] ? 0xFF : 0xFFFF)
    FOR i := 0 to UpperBound
        k := i
        FOR j := 0 to UpperBound-i
            IntRes1[i] := IntRes1[i] AND BoolRes[k][j]
            k := k+1
        ENDFOR
    ENDFOR
ESAC
// optionally negate results
bInvalid := 0
FOR i := 0 to UpperBound
    IF imm8[4]
        IF imm8[5] // only negate valid
            IF b[n+size-1:n] == 0
                bInvalid := 1
            FI
            IF bInvalid // invalid, don't negate
                IntRes2[i] := IntRes1[i]
            ELSE // valid, negate
                IntRes2[i] := -1 XOR IntRes1[i]
            FI
        ELSE // negate all
            IntRes2[i] := -1 XOR IntRes1[i]
        FI
    ELSE // don't negate
        IntRes2[i] := IntRes1[i]
    FI
ENDFOR
// output
dst := (IntRes2 == 0) AND bInvalid

Performance

Architecture | Latency | Throughput | μops
Ryzen | 11 | 2 | 2
Jaguar | 2 | 2 | 3
Sandy Bridge | 3 | 3 | 3
Ivy Bridge | 3 |  | 3
Haswell | 11 | 3 | 3
Broadwell | 3 | 3 | 3
Skylake | 10 | 3 | 3
Knights Landing | 17 | 17 | 6
Ivy Bridge | 11 | 3 |
Haswell | 10 | 3 |
Broadwell | 10 | 3 |
Skylake | 15 | 3 |


_mm_cmpistrc

int _mm_cmpistrc( __m128i a, __m128i b, const int imm8 )

Synopsis

#include "nmmintrin.h"
Instruction: pcmpistri
CPUID Flag: SSE4.2
Category: String Compare

Description

Compare packed strings with implicit lengths in "a" and "b" using the control in "imm8", and returns 1 if the resulting mask was non-zero, and 0 otherwise. [strcmp_note]

Operation

size := (imm8[0] ? 16 : 8) // 8 or 16-bit characters
UpperBound := (128 / size) - 1
// compare all characters
aInvalid := 0
bInvalid := 0
FOR i := 0 to UpperBound
    m := i*size
    FOR j := 0 to UpperBound
        n := j*size
        BoolRes[i][j] := (a[m+size-1:m] == b[n+size-1:n])

        // invalidate characters after EOS
        IF a[m+size-1:m] == 0
            aInvalid := 1
        FI
        IF b[n+size-1:n] == 0
            bInvalid := 1
        FI

        // override comparisons for invalid characters
        CASE (imm8[3:2]) OF
        0:  // equal any
            IF (!aInvalid && bInvalid)
                BoolRes[i][j] := 0
            ELSE IF (aInvalid && !bInvalid)
                BoolRes[i][j] := 0
            ELSE IF (aInvalid && bInvalid)
                BoolRes[i][j] := 0
            FI
        1:  // ranges
            IF (!aInvalid && bInvalid)
                BoolRes[i][j] := 0
            ELSE IF (aInvalid && !bInvalid)
                BoolRes[i][j] := 0
            ELSE IF (aInvalid && bInvalid)
                BoolRes[i][j] := 0
            FI
        2:  // equal each
            IF (!aInvalid && bInvalid)
                BoolRes[i][j] := 0
            ELSE IF (aInvalid && !bInvalid)
                BoolRes[i][j] := 0
            ELSE IF (aInvalid && bInvalid)
                BoolRes[i][j] := 1
            FI
        3:  // equal ordered
            IF (!aInvalid && bInvalid)
                BoolRes[i][j] := 0
            ELSE IF (aInvalid && !bInvalid)
                BoolRes[i][j] := 1
            ELSE IF (aInvalid && bInvalid)
                BoolRes[i][j] := 1
            FI
        ESAC
    ENDFOR
ENDFOR
// aggregate results
CASE (imm8[3:2]) OF
0:  // equal any
    IntRes1 := 0
    FOR i := 0 to UpperBound
        FOR j := 0 to UpperBound
            IntRes1[i] := IntRes1[i] OR BoolRes[i][j]
        ENDFOR
    ENDFOR
1:  // ranges
    IntRes1 := 0
    FOR i := 0 to UpperBound
        FOR j := 0 to UpperBound, j += 2
            IntRes1[i] := IntRes1[i] OR (BoolRes[i][j] AND BoolRes[i][j+1])
        ENDFOR
    ENDFOR
2:  // equal each
    IntRes1 := 0
    FOR i := 0 to UpperBound
        IntRes1[i] := BoolRes[i][i]
    ENDFOR
3:  // equal ordered
    IntRes1 := (imm8[0] ? 0xFF : 0xFFFF)
    FOR i := 0 to UpperBound
        k := i
        FOR j := 0 to UpperBound-i
            IntRes1[i] := IntRes1[i] AND BoolRes[k][j]
            k := k+1
        ENDFOR
    ENDFOR
ESAC
// optionally negate results
bInvalid := 0
FOR i := 0 to UpperBound
    IF imm8[4]
        IF imm8[5] // only negate valid
            IF b[n+size-1:n] == 0
                bInvalid := 1
            FI
            IF bInvalid // invalid, don't negate
                IntRes2[i] := IntRes1[i]
            ELSE // valid, negate
                IntRes2[i] := -1 XOR IntRes1[i]
            FI
        ELSE // negate all
            IntRes2[i] := -1 XOR IntRes1[i]
        FI
    ELSE // don't negate
        IntRes2[i] := IntRes1[i]
    FI
ENDFOR
// output
dst := (IntRes2 != 0)

Performance

Architecture | Latency | Throughput | μops
Ryzen | 11 | 2 | 2
Jaguar | 2 | 2 | 3
Sandy Bridge | 3 | 3 | 3
Ivy Bridge | 3 |  | 3
Haswell | 11 | 3 | 3
Broadwell | 3 | 3 | 3
Skylake | 10 | 3 | 3
Knights Landing | 17 | 17 | 6
Ivy Bridge | 11 | 3 |
Haswell | 10 | 3 |
Broadwell | 10 | 3 |
Skylake | 15 | 3 |


_mm_cmpistri

int _mm_cmpistri( __m128i a, __m128i b, const int imm8 )

Synopsis

#include "nmmintrin.h"
Instruction: pcmpistri
CPUID Flag: SSE4.2
Category: String Compare

Description

Compare packed strings with implicit lengths in "a" and "b" using the control in "imm8", and store the generated index in "dst". [strcmp_note]

Operation

size := (imm8[0] ? 16 : 8) // 8 or 16-bit characters
UpperBound := (128 / size) - 1
// compare all characters
aInvalid := 0
bInvalid := 0
FOR i := 0 to UpperBound
    m := i*size
    FOR j := 0 to UpperBound
        n := j*size
        BoolRes[i][j] := (a[m+size-1:m] == b[n+size-1:n])

        // invalidate characters after EOS
        IF a[m+size-1:m] == 0
            aInvalid := 1
        FI
        IF b[n+size-1:n] == 0
            bInvalid := 1
        FI

        // override comparisons for invalid characters
        CASE (imm8[3:2]) OF
        0:  // equal any
            IF (!aInvalid && bInvalid)
                BoolRes[i][j] := 0
            ELSE IF (aInvalid && !bInvalid)
                BoolRes[i][j] := 0
            ELSE IF (aInvalid && bInvalid)
                BoolRes[i][j] := 0
            FI
        1:  // ranges
            IF (!aInvalid && bInvalid)
                BoolRes[i][j] := 0
            ELSE IF (aInvalid && !bInvalid)
                BoolRes[i][j] := 0
            ELSE IF (aInvalid && bInvalid)
                BoolRes[i][j] := 0
            FI
        2:  // equal each
            IF (!aInvalid && bInvalid)
                BoolRes[i][j] := 0
            ELSE IF (aInvalid && !bInvalid)
                BoolRes[i][j] := 0
            ELSE IF (aInvalid && bInvalid)
                BoolRes[i][j] := 1
            FI
        3:  // equal ordered
            IF (!aInvalid && bInvalid)
                BoolRes[i][j] := 0
            ELSE IF (aInvalid && !bInvalid)
                BoolRes[i][j] := 1
            ELSE IF (aInvalid && bInvalid)
                BoolRes[i][j] := 1
            FI
        ESAC
    ENDFOR
ENDFOR
// aggregate results
CASE (imm8[3:2]) OF
0:  // equal any
    IntRes1 := 0
    FOR i := 0 to UpperBound
        FOR j := 0 to UpperBound
            IntRes1[i] := IntRes1[i] OR BoolRes[i][j]
        ENDFOR
    ENDFOR
1:  // ranges
    IntRes1 := 0
    FOR i := 0 to UpperBound
        FOR j := 0 to UpperBound, j += 2
            IntRes1[i] := IntRes1[i] OR (BoolRes[i][j] AND BoolRes[i][j+1])
        ENDFOR
    ENDFOR
2:  // equal each
    IntRes1 := 0
    FOR i := 0 to UpperBound
        IntRes1[i] := BoolRes[i][i]
    ENDFOR
3:  // equal ordered
    IntRes1 := (imm8[0] ? 0xFF : 0xFFFF)
    FOR i := 0 to UpperBound
        k := i
        FOR j := 0 to UpperBound-i
            IntRes1[i] := IntRes1[i] AND BoolRes[k][j]
            k := k+1
        ENDFOR
    ENDFOR
ESAC
// optionally negate results
bInvalid := 0
FOR i := 0 to UpperBound
    IF imm8[4]
        IF imm8[5] // only negate valid
            IF b[n+size-1:n] == 0
                bInvalid := 1
            FI
            IF bInvalid // invalid, don't negate
                IntRes2[i] := IntRes1[i]
            ELSE // valid, negate
                IntRes2[i] := -1 XOR IntRes1[i]
            FI
        ELSE // negate all
            IntRes2[i] := -1 XOR IntRes1[i]
        FI
    ELSE // don't negate
        IntRes2[i] := IntRes1[i]
    FI
ENDFOR
// output
IF imm8[6] // most significant bit
    tmp := UpperBound
    dst := tmp
    DO WHILE ((tmp >= 0) AND a[tmp] == 0)
        tmp := tmp - 1
        dst := tmp
    OD
ELSE // least significant bit
    tmp := 0
    dst := tmp
    DO WHILE ((tmp <= UpperBound) AND a[tmp] == 0)
        tmp := tmp + 1
        dst := tmp
    OD
FI

Performance

Architecture | Latency | Throughput | μops
Ryzen | 11 | 2 | 2
Jaguar | 2 | 2 | 3
Sandy Bridge | 3 | 3 | 3
Ivy Bridge | 3 |  | 3
Haswell | 11 | 3 | 3
Broadwell | 3 | 3 | 3
Skylake | 10 | 3 | 3
Knights Landing | 17 | 17 | 6
Ivy Bridge | 11 | 3 |
Haswell | 10 | 3 |
Broadwell | 10 | 3 |
Skylake | 15 | 3 |


_mm_cmpistrm

__m128i _mm_cmpistrm( __m128i a, __m128i b, const int imm8 )

Synopsis

#include "nmmintrin.h"
Instruction: pcmpistrm
CPUID Flag: SSE4.2
Category: String Compare

Description

Compare packed strings with implicit lengths in "a" and "b" using the control in "imm8", and store the generated mask in "dst". [strcmp_note]

Operation

size := (imm8[0] ? 16 : 8) // 8 or 16-bit characters
UpperBound := (128 / size) - 1
// compare all characters
aInvalid := 0
bInvalid := 0
FOR i := 0 to UpperBound
    m := i*size
    FOR j := 0 to UpperBound
        n := j*size
        BoolRes[i][j] := (a[m+size-1:m] == b[n+size-1:n])

        // invalidate characters after EOS
        IF a[m+size-1:m] == 0
            aInvalid := 1
        FI
        IF b[n+size-1:n] == 0
            bInvalid := 1
        FI

        // override comparisons for invalid characters
        CASE (imm8[3:2]) OF
        0:  // equal any
            IF (!aInvalid && bInvalid)
                BoolRes[i][j] := 0
            ELSE IF (aInvalid && !bInvalid)
                BoolRes[i][j] := 0
            ELSE IF (aInvalid && bInvalid)
                BoolRes[i][j] := 0
            FI
        1:  // ranges
            IF (!aInvalid && bInvalid)
                BoolRes[i][j] := 0
            ELSE IF (aInvalid && !bInvalid)
                BoolRes[i][j] := 0
            ELSE IF (aInvalid && bInvalid)
                BoolRes[i][j] := 0
            FI
        2:  // equal each
            IF (!aInvalid && bInvalid)
                BoolRes[i][j] := 0
            ELSE IF (aInvalid && !bInvalid)
                BoolRes[i][j] := 0
            ELSE IF (aInvalid && bInvalid)
                BoolRes[i][j] := 1
            FI
        3:  // equal ordered
            IF (!aInvalid && bInvalid)
                BoolRes[i][j] := 0
            ELSE IF (aInvalid && !bInvalid)
                BoolRes[i][j] := 1
            ELSE IF (aInvalid && bInvalid)
                BoolRes[i][j] := 1
            FI
        ESAC
    ENDFOR
ENDFOR
// aggregate results
CASE (imm8[3:2]) OF
0:  // equal any
    IntRes1 := 0
    FOR i := 0 to UpperBound
        FOR j := 0 to UpperBound
            IntRes1[i] := IntRes1[i] OR BoolRes[i][j]
        ENDFOR
    ENDFOR
1:  // ranges
    IntRes1 := 0
    FOR i := 0 to UpperBound
        FOR j := 0 to UpperBound, j += 2
            IntRes1[i] := IntRes1[i] OR (BoolRes[i][j] AND BoolRes[i][j+1])
        ENDFOR
    ENDFOR
2:  // equal each
    IntRes1 := 0
    FOR i := 0 to UpperBound
        IntRes1[i] := BoolRes[i][i]
    ENDFOR
3:  // equal ordered
    IntRes1 := (imm8[0] ? 0xFF : 0xFFFF)
    FOR i := 0 to UpperBound
        k := i
        FOR j := 0 to UpperBound-i
            IntRes1[i] := IntRes1[i] AND BoolRes[k][j]
            k := k+1
        ENDFOR
    ENDFOR
ESAC
// optionally negate results
bInvalid := 0
FOR i := 0 to UpperBound
    IF imm8[4]
        IF imm8[5] // only negate valid
            IF b[n+size-1:n] == 0
                bInvalid := 1
            FI
            IF bInvalid // invalid, don't negate
                IntRes2[i] := IntRes1[i]
            ELSE // valid, negate
                IntRes2[i] := -1 XOR IntRes1[i]
            FI
        ELSE // negate all
            IntRes2[i] := -1 XOR IntRes1[i]
        FI
    ELSE // don't negate
        IntRes2[i] := IntRes1[i]
    FI
ENDFOR
// output
IF imm8[6] // byte / word mask
    FOR i := 0 to UpperBound
        j := i*size
        IF IntRes2[i]
            dst[j+size-1:j] := (imm8[0] ? 0xFF : 0xFFFF)
        ELSE
            dst[j+size-1:j] := 0
        FI
    ENDFOR
ELSE // bit mask
    dst[UpperBound:0] := IntRes2[UpperBound:0]
    dst[127:UpperBound+1] := 0
FI

Performance

Architecture | Latency | Throughput | μops
Ryzen | 7 | 2 | 3
Jaguar | 8 | 8 | 3
Sandy Bridge | 11 | 3 | 3
Ivy Bridge | 11 |  | 3
Haswell | 10 | 3 | 3
Broadwell | 11 | 11 | 3
Skylake | 9 | 3 | 3
Knights Landing | 13 | 13 | 5
Ivy Bridge | 11 | 3 |
Haswell | 11 | 3 |
Broadwell | 11 | 3 |
Skylake | 15 | 3 |


_mm_cmpistro

int _mm_cmpistro( __m128i a, __m128i b, const int imm8 )

Synopsis

#include "nmmintrin.h"
Instruction: pcmpistri
CPUID Flag: SSE4.2
Category: String Compare

Description

Compare packed strings with implicit lengths in "a" and "b" using the control in "imm8", and returns bit 0 of the resulting bit mask. [strcmp_note]

Operation

size := (imm8[0] ? 16 : 8) // 8 or 16-bit characters
UpperBound := (128 / size) - 1
// compare all characters
aInvalid := 0
bInvalid := 0
FOR i := 0 to UpperBound
    m := i*size
    FOR j := 0 to UpperBound
        n := j*size
        BoolRes[i][j] := (a[m+size-1:m] == b[n+size-1:n])

        // invalidate characters after EOS
        IF a[m+size-1:m] == 0
            aInvalid := 1
        FI
        IF b[n+size-1:n] == 0
            bInvalid := 1
        FI

        // override comparisons for invalid characters
        CASE (imm8[3:2]) OF
        0:  // equal any
            IF (!aInvalid && bInvalid)
                BoolRes[i][j] := 0
            ELSE IF (aInvalid && !bInvalid)
                BoolRes[i][j] := 0
            ELSE IF (aInvalid && bInvalid)
                BoolRes[i][j] := 0
            FI
        1:  // ranges
            IF (!aInvalid && bInvalid)
                BoolRes[i][j] := 0
            ELSE IF (aInvalid && !bInvalid)
                BoolRes[i][j] := 0
            ELSE IF (aInvalid && bInvalid)
                BoolRes[i][j] := 0
            FI
        2:  // equal each
            IF (!aInvalid && bInvalid)
                BoolRes[i][j] := 0
            ELSE IF (aInvalid && !bInvalid)
                BoolRes[i][j] := 0
            ELSE IF (aInvalid && bInvalid)
                BoolRes[i][j] := 1
            FI
        3:  // equal ordered
            IF (!aInvalid && bInvalid)
                BoolRes[i][j] := 0
            ELSE IF (aInvalid && !bInvalid)
                BoolRes[i][j] := 1
            ELSE IF (aInvalid && bInvalid)
                BoolRes[i][j] := 1
            FI
        ESAC
    ENDFOR
ENDFOR
// aggregate results
CASE (imm8[3:2]) OF
0:  // equal any
    IntRes1 := 0
    FOR i := 0 to UpperBound
        FOR j := 0 to UpperBound
            IntRes1[i] := IntRes1[i] OR BoolRes[i][j]
        ENDFOR
    ENDFOR
1:  // ranges
    IntRes1 := 0
    FOR i := 0 to UpperBound
        FOR j := 0 to UpperBound, j += 2
            IntRes1[i] := IntRes1[i] OR (BoolRes[i][j] AND BoolRes[i][j+1])
        ENDFOR
    ENDFOR
2:  // equal each
    IntRes1 := 0
    FOR i := 0 to UpperBound
        IntRes1[i] := BoolRes[i][i]
    ENDFOR
3:  // equal ordered
    IntRes1 := (imm8[0] ? 0xFF : 0xFFFF)
    FOR i := 0 to UpperBound
        k := i
        FOR j := 0 to UpperBound-i
            IntRes1[i] := IntRes1[i] AND BoolRes[k][j]
            k := k+1
        ENDFOR
    ENDFOR
ESAC
// optionally negate results
bInvalid := 0
FOR i := 0 to UpperBound
    IF imm8[4]
        IF imm8[5] // only negate valid
            IF b[n+size-1:n] == 0
                bInvalid := 1
            FI
            IF bInvalid // invalid, don't negate
                IntRes2[i] := IntRes1[i]
            ELSE // valid, negate
                IntRes2[i] := -1 XOR IntRes1[i]
            FI
        ELSE // negate all
            IntRes2[i] := -1 XOR IntRes1[i]
        FI
    ELSE // don't negate
        IntRes2[i] := IntRes1[i]
    FI
ENDFOR
// output
dst := IntRes2[0]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 11 | 2 | 2
Jaguar | 2 | 2 | 3
Sandy Bridge | 3 | 3 | 3
Ivy Bridge | 3 |  | 3
Haswell | 11 | 3 | 3
Broadwell | 3 | 3 | 3
Skylake | 10 | 3 | 3
Knights Landing | 17 | 17 | 6
Ivy Bridge | 11 | 3 |
Haswell | 10 | 3 |
Broadwell | 10 | 3 |
Skylake | 15 | 3 |


_mm_cmpistrs

int _mm_cmpistrs( __m128i a, __m128i b, const int imm8 )

Synopsis

#include "nmmintrin.h"
Instruction: pcmpistri
CPUID Flag: SSE4.2
Category: String Compare

Description

Compare packed strings with implicit lengths in "a" and "b" using the control in "imm8", and returns 1 if any character in "a" was null, and 0 otherwise. [strcmp_note]

Operation

size := (imm8[0] ? 16 : 8) // 8 or 16-bit characters
UpperBound := (128 / size) - 1
aInvalid := 0
FOR i := 0 to UpperBound
    m := i*size
    IF b[m+size-1:m] == 0
        aInvalid := 1
    FI
ENDFOR
dst := aInvalid

Performance

Architecture | Latency | Throughput | μops
Ryzen | 11 | 2 | 2
Jaguar | 2 | 2 | 3
Sandy Bridge | 3 | 3 | 3
Ivy Bridge | 3 |  | 3
Haswell | 11 | 3 | 3
Broadwell | 3 | 3 | 3
Skylake | 10 | 3 | 3
Knights Landing | 17 | 17 | 6
Ivy Bridge | 11 | 3 |
Haswell | 10 | 3 |
Broadwell | 10 | 3 |
Skylake | 15 | 3 |


_mm_cmpistrz

int _mm_cmpistrz( __m128i a, __m128i b, const int imm8 )

Synopsis

#include "nmmintrin.h"
Instruction: pcmpistri
CPUID Flag: SSE4.2
Category: String Compare

Description

Compare packed strings with implicit lengths in "a" and "b" using the control in "imm8", and returns 1 if any character in "b" was null, and 0 otherwise. [strcmp_note]

Operation

size := (imm8[0] ? 16 : 8) // 8 or 16-bit characters
UpperBound := (128 / size) - 1
bInvalid := 0
FOR j := 0 to UpperBound
    n := j*size
    IF b[n+size-1:n] == 0
        bInvalid := 1
    FI
ENDFOR
dst := bInvalid

Performance

Architecture | Latency | Throughput | μops
Ryzen | 11 | 2 | 2
Jaguar | 2 | 2 | 3
Sandy Bridge | 3 | 3 | 3
Ivy Bridge | 3 |  | 3
Haswell | 11 | 3 | 3
Broadwell | 3 | 3 | 3
Skylake | 10 | 3 | 3
Knights Landing | 17 | 17 | 6
Ivy Bridge | 11 | 3 |
Haswell | 10 | 3 |
Broadwell | 10 | 3 |
Skylake | 15 | 3 |


_mm_cmple_pd

__m128d _mm_cmple_pd( __m128d a, __m128d b )

Synopsis

#include "emmintrin.h"
Instruction: cmppd
CPUID Flag: SSE2
Category: Compare

Description

Compare packed double-precision (64-bit) floating-point elements in "a" and "b" for less-than-or-equal, and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*64
    dst[i+63:i] := (a[i+63:i] <= b[i+63:i]) ? 0xFFFFFFFFFFFFFFFF : 0
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 1 | 1
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 4 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 4 | 0.5 |


_mm_cmple_ps

__m128 _mm_cmple_ps( __m128 a, __m128 b )

Synopsis

#include "xmmintrin.h"
Instruction: cmpps
CPUID Flag: SSE
Category: Compare

Description

Compare packed single-precision (32-bit) floating-point elements in "a" and "b" for less-than-or-equal, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := ( a[i+31:i] <= b[i+31:i] ) ? 0xffffffff : 0
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 1 | 1
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 4 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 4 | 0.5 |


_mm_cmple_sd

__m128d _mm_cmple_sd( __m128d a, __m128d b )

Synopsis

#include "emmintrin.h"
Instruction: cmpsd
CPUID Flag: SSE2
Category: Compare

Description

Compare the lower double-precision (64-bit) floating-point elements in "a" and "b" for less-than-or-equal, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".

Operation

dst[63:0] := (a[63:0] <= b[63:0]) ? 0xFFFFFFFFFFFFFFFF : 0
dst[127:64] := a[127:64]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 1 | 1
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 4 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 4 | 0.5 |


_mm_cmple_ss

__m128 _mm_cmple_ss( __m128 a, __m128 b )

Synopsis

#include "xmmintrin.h"
Instruction: cmpss
CPUID Flag: SSE
Category: Compare

Description

Compare the lower single-precision (32-bit) floating-point elements in "a" and "b" for less-than-or-equal, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".

Operation

dst[31:0] := ( a[31:0] <= b[31:0] ) ? 0xffffffff : 0
dst[127:32] := a[127:32]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 1 | 1
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 4 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 4 | 0.5 |


_mm_cmplt_epi16

__m128i _mm_cmplt_epi16( __m128i a, __m128i b )

Synopsis

#include "emmintrin.h"
Instruction: pcmpgtw
CPUID Flag: SSE2
Category: Compare

Description

Compare packed 16-bit integers in "a" and "b" for less-than, and store the results in "dst". Note: This intrinsic emits the pcmpgtw instruction with the order of the operands switched.

Operation

FOR j := 0 to 7
    i := j*16
    dst[i+15:i] := ( a[i+15:i] < b[i+15:i] ) ? 0xFFFF : 0
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.5 |


_mm_cmplt_epi32

__m128i _mm_cmplt_epi32( __m128i a, __m128i b )

Synopsis

#include "emmintrin.h"
Instruction: pcmpgtd
CPUID Flag: SSE2
Category: Compare

Description

Compare packed 32-bit integers in "a" and "b" for less-than, and store the results in "dst". Note: This intrinsic emits the pcmpgtd instruction with the order of the operands switched.

Operation

FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := ( a[i+31:i] < b[i+31:i] ) ? 0xFFFFFFFF : 0
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.5 |


_mm_cmplt_epi8

__m128i _mm_cmplt_epi8( __m128i a, __m128i b )

Synopsis

#include "emmintrin.h"
Instruction: pcmpgtb
CPUID Flag: SSE2
Category: Compare

Description

Compare packed 8-bit integers in "a" and "b" for less-than, and store the results in "dst". Note: This intrinsic emits the pcmpgtb instruction with the order of the operands switched.

Operation

FOR j := 0 to 15
    i := j*8
    dst[i+7:i] := ( a[i+7:i] < b[i+7:i] ) ? 0xFF : 0
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.5 |


_mm_cmplt_pd

__m128d _mm_cmplt_pd( __m128d a, __m128d b )

Synopsis

#include "emmintrin.h"
Instruction: cmppd
CPUID Flag: SSE2
Category: Compare

Description

Compare packed double-precision (64-bit) floating-point elements in "a" and "b" for less-than, and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*64
    dst[i+63:i] := (a[i+63:i] < b[i+63:i]) ? 0xFFFFFFFFFFFFFFFF : 0
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 1 | 1
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 4 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 4 | 0.5 |


_mm_cmplt_ps

__m128 _mm_cmplt_ps( __m128 a, __m128 b )

Synopsis

#include "xmmintrin.h"
Instruction: cmpps
CPUID Flag: SSE
Category: Compare

Description

Compare packed single-precision (32-bit) floating-point elements in "a" and "b" for less-than, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := ( a[i+31:i] < b[i+31:i] ) ? 0xffffffff : 0
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 1 | 1
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 4 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 4 | 0.5 |


_mm_cmplt_sd

__m128d _mm_cmplt_sd( __m128d a, __m128d b )

Synopsis

#include "emmintrin.h"
Instruction: cmpsd
CPUID Flag: SSE2
Category: Compare

Description

Compare the lower double-precision (64-bit) floating-point elements in "a" and "b" for less-than, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".

Operation

dst[63:0] := (a[63:0] < b[63:0]) ? 0xFFFFFFFFFFFFFFFF : 0
dst[127:64] := a[127:64]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 1 | 1
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 4 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 4 | 0.5 |


_mm_cmplt_ss

__m128 _mm_cmplt_ss( __m128 a, __m128 b )

Synopsis

#include "xmmintrin.h"
Instruction: cmpss
CPUID Flag: SSE
Category: Compare

Description

Compare the lower single-precision (32-bit) floating-point elements in "a" and "b" for less-than, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".

Operation

dst[31:0] := ( a[31:0] < b[31:0] ) ? 0xffffffff : 0
dst[127:32] := a[127:32]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 1 | 1
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 4 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 4 | 0.5 |


_mm_cmpneq_pd

__m128d _mm_cmpneq_pd( __m128d a, __m128d b )

Synopsis

#include "emmintrin.h"
Instruction: cmppd
CPUID Flag: SSE2
Category: Compare

Description

Compare packed double-precision (64-bit) floating-point elements in "a" and "b" for not-equal, and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*64
    dst[i+63:i] := (a[i+63:i] != b[i+63:i]) ? 0xFFFFFFFFFFFFFFFF : 0
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 1 | 1
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 4 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 4 | 0.5 |


_mm_cmpneq_ps

__m128 _mm_cmpneq_ps( __m128 a, __m128 b )

Synopsis

#include "xmmintrin.h"
Instruction: cmpps
CPUID Flag: SSE
Category: Compare

Description

Compare packed single-precision (32-bit) floating-point elements in "a" and "b" for not-equal, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := ( a[i+31:i] != b[i+31:i] ) ? 0xffffffff : 0
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 1 | 1
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 4 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 4 | 0.5 |


_mm_cmpneq_sd

__m128d _mm_cmpneq_sd( __m128d a, __m128d b )

Synopsis

#include "emmintrin.h"
Instruction: cmpsd
CPUID Flag: SSE2
Category: Compare

Description

Compare the lower double-precision (64-bit) floating-point elements in "a" and "b" for not-equal, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".

Operation

dst[63:0] := (a[63:0] != b[63:0]) ? 0xFFFFFFFFFFFFFFFF : 0
dst[127:64] := a[127:64]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 1 | 1
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 4 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 4 | 0.5 |


_mm_cmpneq_ss

__m128 _mm_cmpneq_ss( __m128 a, __m128 b )

Synopsis

#include "xmmintrin.h"
Instruction: cmpss
CPUID Flag: SSE
Category: Compare

Description

Compare the lower single-precision (32-bit) floating-point elements in "a" and "b" for not-equal, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".

Operation

dst[31:0] := ( a[31:0] != b[31:0] ) ? 0xffffffff : 0
dst[127:32] := a[127:32]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 1 | 1
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 4 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 4 | 0.5 |


_mm_cmpnge_pd

__m128d _mm_cmpnge_pd( __m128d a, __m128d b )

Synopsis

#include "emmintrin.h"
Instruction: cmppd
CPUID Flag: SSE2
Category: Compare

Description

Compare packed double-precision (64-bit) floating-point elements in "a" and "b" for not-greater-than-or-equal, and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*64
    dst[i+63:i] := (!(a[i+63:i] >= b[i+63:i])) ? 0xFFFFFFFFFFFFFFFF : 0
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 1 | 1
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 4 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 4 | 0.5 |


_mm_cmpnge_ps

__m128 _mm_cmpnge_ps( __m128 a, __m128 b )

Synopsis

#include "xmmintrin.h"
Instruction: cmpps
CPUID Flag: SSE
Category: Compare

Description

Compare packed single-precision (32-bit) floating-point elements in "a" and "b" for not-greater-than-or-equal, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := (!( a[i+31:i] >= b[i+31:i] )) ? 0xffffffff : 0
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 1 | 1
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 4 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 4 | 0.5 |


_mm_cmpnge_sd

__m128d _mm_cmpnge_sd( __m128d a, __m128d b )

Synopsis

#include "emmintrin.h"
Instruction: cmpsd
CPUID Flag: SSE2
Category: Compare

Description

Compare the lower double-precision (64-bit) floating-point elements in "a" and "b" for not-greater-than-or-equal, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".

Operation

dst[63:0] := (!(a[63:0] >= b[63:0])) ? 0xFFFFFFFFFFFFFFFF : 0
dst[127:64] := a[127:64]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 1 | 1
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 4 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 4 | 0.5 |


_mm_cmpnge_ss

__m128 _mm_cmpnge_ss( __m128 a, __m128 b )

Synopsis

#include "xmmintrin.h"
Instruction: cmpss
CPUID Flag: SSE
Category: Compare

Description

Compare the lower single-precision (32-bit) floating-point elements in "a" and "b" for not-greater-than-or-equal, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".

Operation

dst[31:0] := (!( a[31:0] >= b[31:0] )) ? 0xffffffff : 0
dst[127:32] := a[127:32]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 1 | 1
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 4 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 4 | 0.5 |


_mm_cmpngt_pd

__m128d _mm_cmpngt_pd( __m128d a, __m128d b )

Synopsis

#include "emmintrin.h"
Instruction: cmppd
CPUID Flag: SSE2
Category: Compare

Description

Compare packed double-precision (64-bit) floating-point elements in "a" and "b" for not-greater-than, and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*64
    dst[i+63:i] := (!(a[i+63:i] > b[i+63:i])) ? 0xFFFFFFFFFFFFFFFF : 0
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 1 | 1
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 4 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 4 | 0.5 |


_mm_cmpngt_ps

__m128 _mm_cmpngt_ps( __m128 a, __m128 b )

Synopsis

#include "xmmintrin.h"
Instruction: cmpps
CPUID Flag: SSE
Category: Compare

Description

Compare packed single-precision (32-bit) floating-point elements in "a" and "b" for not-greater-than, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := (!( a[i+31:i] > b[i+31:i] )) ? 0xffffffff : 0
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 1 | 1
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 4 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 4 | 0.5 |


_mm_cmpngt_sd

__m128d _mm_cmpngt_sd( __m128d a, __m128d b )

Synopsis

#include "emmintrin.h"
Instruction: cmpsd
CPUID Flag: SSE2
Category: Compare

Description

Compare the lower double-precision (64-bit) floating-point elements in "a" and "b" for not-greater-than, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".

Operation

dst[63:0] := (!(a[63:0] > b[63:0])) ? 0xFFFFFFFFFFFFFFFF : 0
dst[127:64] := a[127:64]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 1 | 1
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 4 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 4 | 0.5 |


_mm_cmpngt_ss

__m128 _mm_cmpngt_ss( __m128 a, __m128 b )

Synopsis

#include "xmmintrin.h"
Instruction: cmpss
CPUID Flag: SSE
Category: Compare

Description

Compare the lower single-precision (32-bit) floating-point elements in "a" and "b" for not-greater-than, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".

Operation

dst[31:0] := (!( a[31:0] > b[31:0] )) ? 0xffffffff : 0
dst[127:32] := a[127:32]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 1 | 1
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 4 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 4 | 0.5 |


_mm_cmpnle_pd

__m128d _mm_cmpnle_pd( __m128d a, __m128d b )

Synopsis

#include "emmintrin.h"
Instruction: cmppd
CPUID Flag: SSE2
Category: Compare

Description

Compare packed double-precision (64-bit) floating-point elements in "a" and "b" for not-less-than-or-equal, and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*64
    dst[i+63:i] := (!(a[i+63:i] <= b[i+63:i])) ? 0xFFFFFFFFFFFFFFFF : 0
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 1 | 1
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 4 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 4 | 0.5 |


_mm_cmpnle_ps

__m128 _mm_cmpnle_ps( __m128 a, __m128 b )

Synopsis

#include "xmmintrin.h"
Instruction: cmpps
CPUID Flag: SSE
Category: Compare

Description

Compare packed single-precision (32-bit) floating-point elements in "a" and "b" for not-less-than-or-equal, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := (!( a[i+31:i] <= b[i+31:i] )) ? 0xffffffff : 0
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 1 | 1
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 4 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 4 | 0.5 |


_mm_cmpnle_sd

__m128d _mm_cmpnle_sd( __m128d a, __m128d b )

Synopsis

#include "emmintrin.h"
Instruction: cmpsd
CPUID Flag: SSE2
Category: Compare

Description

Compare the lower double-precision (64-bit) floating-point elements in "a" and "b" for not-less-than-or-equal, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".

Operation

dst[63:0] := (!(a[63:0] <= b[63:0])) ? 0xFFFFFFFFFFFFFFFF : 0
dst[127:64] := a[127:64]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 1 | 1
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 4 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 4 | 0.5 |


_mm_cmpnle_ss

__m128 _mm_cmpnle_ss( __m128 a, __m128 b )

Synopsis

#include "xmmintrin.h"
Instruction: cmpss
CPUID Flag: SSE
Category: Compare

Description

Compare the lower single-precision (32-bit) floating-point elements in "a" and "b" for not-less-than-or-equal, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".

Operation

dst[31:0] := (!( a[31:0] <= b[31:0] )) ? 0xffffffff : 0
dst[127:32] := a[127:32]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 1 | 1
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 4 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 4 | 0.5 |


_mm_cmpnlt_pd

__m128d _mm_cmpnlt_pd( __m128d a, __m128d b )

Synopsis

#include "emmintrin.h"
Instruction: cmppd
CPUID Flag: SSE2
Category: Compare

Description

Compare packed double-precision (64-bit) floating-point elements in "a" and "b" for not-less-than, and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*64
    dst[i+63:i] := (!(a[i+63:i] < b[i+63:i])) ? 0xFFFFFFFFFFFFFFFF : 0
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 1 | 1
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 4 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 4 | 0.5 |


_mm_cmpnlt_ps

__m128 _mm_cmpnlt_ps( __m128 a, __m128 b )

Synopsis

#include "xmmintrin.h"
Instruction: cmpps
CPUID Flag: SSE
Category: Compare

Description

Compare packed single-precision (32-bit) floating-point elements in "a" and "b" for not-less-than, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := !( a[i+31:i] < b[i+31:i] ) ? 0xffffffff : 0
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 1 | 1
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 4 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 4 | 0.5 |


_mm_cmpnlt_sd

__m128d _mm_cmpnlt_sd( __m128d a, __m128d b )

Synopsis

#include "emmintrin.h"
Instruction: cmpsd
CPUID Flag: SSE2
Category: Compare

Description

Compare the lower double-precision (64-bit) floating-point elements in "a" and "b" for not-less-than, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".

Operation

dst[63:0] := (!(a[63:0] < b[63:0])) ? 0xFFFFFFFFFFFFFFFF : 0
dst[127:64] := a[127:64]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 1 | 1
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 4 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 4 | 0.5 |


_mm_cmpnlt_ss

__m128 _mm_cmpnlt_ss( __m128 a, __m128 b )

Synopsis

#include "xmmintrin.h"
Instruction: cmpss
CPUID Flag: SSE
Category: Compare

Description

Compare the lower single-precision (32-bit) floating-point elements in "a" and "b" for not-less-than, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".

Operation

dst[31:0] := (!( a[31:0] < b[31:0] )) ? 0xffffffff : 0
dst[127:32] := a[127:32]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 1 | 1
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 4 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 4 | 0.5 |


_mm_cmpord_pd

__m128d _mm_cmpord_pd( __m128d a, __m128d b )

Synopsis

#include "emmintrin.h"
Instruction: cmppd
CPUID Flag: SSE2
Category: Compare

Description

Compare packed double-precision (64-bit) floating-point elements in "a" and "b" to see if neither is NaN, and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*64
    dst[i+63:i] := (a[i+63:i] != NaN AND b[i+63:i] != NaN) ? 0xFFFFFFFFFFFFFFFF : 0
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 1 | 1
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 4 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 4 | 0.5 |


_mm_cmpord_ps

__m128 _mm_cmpord_ps( __m128 a, __m128 b )

Synopsis

#include "xmmintrin.h"
Instruction: cmpps
CPUID Flag: SSE
Category: Compare

Description

Compare packed single-precision (32-bit) floating-point elements in "a" and "b" to see if neither is NaN, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := ( a[i+31:i] != NaN AND b[i+31:i] != NaN ) ? 0xffffffff : 0
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 1 | 1
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 4 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 4 | 0.5 |


_mm_cmpord_sd

__m128d _mm_cmpord_sd( __m128d a, __m128d b )

Synopsis

#include "emmintrin.h"
Instruction: cmpsd
CPUID Flag: SSE2
Category: Compare

Description

Compare the lower double-precision (64-bit) floating-point elements in "a" and "b" to see if neither is NaN, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".

Operation

dst[63:0] := (a[63:0] != NaN AND b[63:0] != NaN) ? 0xFFFFFFFFFFFFFFFF : 0
dst[127:64] := a[127:64]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 1 | 1
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 4 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 4 | 0.5 |


_mm_cmpord_ss

__m128 _mm_cmpord_ss( __m128 a, __m128 b )

Synopsis

#include "xmmintrin.h"
Instruction: cmpss
CPUID Flag: SSE
Category: Compare

Description

Compare the lower single-precision (32-bit) floating-point elements in "a" and "b" to see if neither is NaN, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".

Operation

dst[31:0] := ( a[31:0] != NaN AND b[31:0] != NaN ) ? 0xffffffff : 0
dst[127:32] := a[127:32]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 1 | 1
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 4 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 4 | 0.5 |


_mm_cmpunord_pd

__m128d _mm_cmpunord_pd( __m128d a, __m128d b )

Synopsis

#include "emmintrin.h"
Instruction: cmppd
CPUID Flag: SSE2
Category: Compare

Description

Compare packed double-precision (64-bit) floating-point elements in "a" and "b" to see if either is NaN, and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*64
    dst[i+63:i] := (a[i+63:i] == NaN OR b[i+63:i] == NaN) ? 0xFFFFFFFFFFFFFFFF : 0
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 1 | 1
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 4 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 4 | 0.5 |


_mm_cmpunord_ps

__m128 _mm_cmpunord_ps( __m128 a, __m128 b )

Synopsis

#include "xmmintrin.h"
Instruction: cmpps
CPUID Flag: SSE
Category: Compare

Description

Compare packed single-precision (32-bit) floating-point elements in "a" and "b" to see if either is NaN, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := ( a[i+31:i] == NaN OR b[i+31:i] == NaN ) ? 0xffffffff : 0
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 1 | 1
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 4 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 4 | 0.5 |


_mm_cmpunord_sd

__m128d _mm_cmpunord_sd( __m128d a, __m128d b )

Synopsis

#include "emmintrin.h"
Instruction: cmpsd
CPUID Flag: SSE2
Category: Compare

Description

Compare the lower double-precision (64-bit) floating-point elements in "a" and "b" to see if either is NaN, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".

Operation

dst[63:0] := (a[63:0] == NaN OR b[63:0] == NaN) ? 0xFFFFFFFFFFFFFFFF : 0
dst[127:64] := a[127:64]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 1 | 1
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 4 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 4 | 0.5 |


_mm_cmpunord_ss

__m128 _mm_cmpunord_ss( __m128 a, __m128 b )

Synopsis

#include "xmmintrin.h"
Instruction: cmpss
CPUID Flag: SSE
Category: Compare

Description

Compare the lower single-precision (32-bit) floating-point elements in "a" and "b" to see if either is NaN, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".

Operation

dst[31:0] := ( a[31:0] == NaN OR b[31:0] == NaN ) ? 0xffffffff : 0
dst[127:32] := a[127:32]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 1 | 1
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 4 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 4 | 0.5 |


_mm_comieq_sd

int _mm_comieq_sd( __m128d a, __m128d b )

Synopsis

#include "emmintrin.h"
Instruction: comisd
CPUID Flag: SSE2
Category: Compare

Description

Compare the lower double-precision (64-bit) floating-point element in "a" and "b" for equality, and return the boolean result (0 or 1).

Operation

RETURN ( a[63:0] == b[63:0] ) ? 1 : 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 4 | 1 | 2
Jaguar |  | 1 | 1
Sandy Bridge | 2 | 1 | 2
Ivy Bridge |  | 1 | 2
Haswell |  | 1 | 1
Broadwell |  | 1 | 1
Skylake |  | 1 | 1
Knights Landing | 7 | 7 | 2
Ivy Bridge | 2 | 1 |
Haswell | 2 | 1 |
Broadwell | 2 | 1 |
Skylake | 2 | 1 |


_mm_comieq_ss

int _mm_comieq_ss( __m128 a, __m128 b )

Synopsis

#include "xmmintrin.h"
Instruction: comiss
CPUID Flag: SSE
Category: Compare

Description

Compare the lower single-precision (32-bit) floating-point element in "a" and "b" for equality, and return the boolean result (0 or 1).

Operation

RETURN ( a[31:0] == b[31:0] ) ? 1 : 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 4 | 1 | 2
Jaguar |  | 1 | 1
Sandy Bridge | 2 | 1 | 2
Ivy Bridge |  | 1 | 2
Haswell |  | 1 | 1
Broadwell |  | 1 | 1
Skylake |  | 1 | 1
Knights Landing | 7 | 7 | 2
Ivy Bridge | 2 | 1 |
Haswell | 2 | 1 |
Broadwell | 2 | 1 |
Skylake | 2 | 1 |


_mm_comige_sd

int _mm_comige_sd( __m128d a, __m128d b )

Synopsis

#include "emmintrin.h"
Instruction: comisd
CPUID Flag: SSE2
Category: Compare

Description

Compare the lower double-precision (64-bit) floating-point element in "a" and "b" for greater-than-or-equal, and return the boolean result (0 or 1).

Operation

RETURN ( a[63:0] >= b[63:0] ) ? 1 : 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 4 | 1 | 2
Jaguar |  | 1 | 1
Sandy Bridge | 2 | 1 | 2
Ivy Bridge |  | 1 | 2
Haswell |  | 1 | 1
Broadwell |  | 1 | 1
Skylake |  | 1 | 1
Knights Landing | 7 | 7 | 2
Ivy Bridge | 2 | 1 |
Haswell | 2 | 1 |
Broadwell | 2 | 1 |
Skylake | 2 | 1 |


_mm_comige_ss

int _mm_comige_ss( __m128 a, __m128 b )

Synopsis

#include "xmmintrin.h"
Instruction: comiss
CPUID Flag: SSE
Category: Compare

Description

Compare the lower single-precision (32-bit) floating-point element in "a" and "b" for greater-than-or-equal, and return the boolean result (0 or 1).

Operation

RETURN ( a[31:0] >= b[31:0] ) ? 1 : 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 4 | 1 | 2
Jaguar |  | 1 | 1
Sandy Bridge | 2 | 1 | 2
Ivy Bridge |  | 1 | 2
Haswell |  | 1 | 1
Broadwell |  | 1 | 1
Skylake |  | 1 | 1
Knights Landing | 7 | 7 | 2
Ivy Bridge | 2 | 1 |
Haswell | 2 | 1 |
Broadwell | 2 | 1 |
Skylake | 2 | 1 |


_mm_comigt_sd

int _mm_comigt_sd( __m128d a, __m128d b )

Synopsis

#include "emmintrin.h"
Instruction: comisd
CPUID Flag: SSE2
Category: Compare

Description

Compare the lower double-precision (64-bit) floating-point element in "a" and "b" for greater-than, and return the boolean result (0 or 1).

Operation

RETURN ( a[63:0] > b[63:0] ) ? 1 : 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 4 | 1 | 2
Jaguar |  | 1 | 1
Sandy Bridge | 2 | 1 | 2
Ivy Bridge |  | 1 | 2
Haswell |  | 1 | 1
Broadwell |  | 1 | 1
Skylake |  | 1 | 1
Knights Landing | 7 | 7 | 2
Ivy Bridge | 2 | 1 |
Haswell | 2 | 1 |
Broadwell | 2 | 1 |
Skylake | 2 | 1 |


_mm_comigt_ss

int _mm_comigt_ss( __m128 a, __m128 b )

Synopsis

#include "xmmintrin.h"
Instruction: comiss
CPUID Flag: SSE
Category: Compare

Description

Compare the lower single-precision (32-bit) floating-point element in "a" and "b" for greater-than, and return the boolean result (0 or 1).

Operation

RETURN ( a[31:0] > b[31:0] ) ? 1 : 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 4 | 1 | 2
Jaguar |  | 1 | 1
Sandy Bridge | 2 | 1 | 2
Ivy Bridge |  | 1 | 2
Haswell |  | 1 | 1
Broadwell |  | 1 | 1
Skylake |  | 1 | 1
Knights Landing | 7 | 7 | 2
Ivy Bridge | 2 | 1 |
Haswell | 2 | 1 |
Broadwell | 2 | 1 |
Skylake | 2 | 1 |


_mm_comile_sd

int _mm_comile_sd( __m128d a, __m128d b )

Synopsis

#include "emmintrin.h"
Instruction: comisd
CPUID Flag: SSE2
Category: Compare

Description

Compare the lower double-precision (64-bit) floating-point element in "a" and "b" for less-than-or-equal, and return the boolean result (0 or 1).

Operation

RETURN ( a[63:0] <= b[63:0] ) ? 1 : 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 4 | 1 | 2
Jaguar |  | 1 | 1
Sandy Bridge | 2 | 1 | 2
Ivy Bridge |  | 1 | 2
Haswell |  | 1 | 1
Broadwell |  | 1 | 1
Skylake |  | 1 | 1
Knights Landing | 7 | 7 | 2
Ivy Bridge | 2 | 1 |
Haswell | 2 | 1 |
Broadwell | 2 | 1 |
Skylake | 2 | 1 |


_mm_comile_ss

int _mm_comile_ss( __m128 a, __m128 b )

Synopsis

#include "xmmintrin.h"
Instruction: comiss
CPUID Flag: SSE
Category: Compare

Description

Compare the lower single-precision (32-bit) floating-point element in "a" and "b" for less-than-or-equal, and return the boolean result (0 or 1).

Operation

RETURN ( a[31:0] <= b[31:0] ) ? 1 : 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 4 | 1 | 2
Jaguar |  | 1 | 1
Sandy Bridge | 2 | 1 | 2
Ivy Bridge |  | 1 | 2
Haswell |  | 1 | 1
Broadwell |  | 1 | 1
Skylake |  | 1 | 1
Knights Landing | 7 | 7 | 2
Ivy Bridge | 2 | 1 |
Haswell | 2 | 1 |
Broadwell | 2 | 1 |
Skylake | 2 | 1 |


_mm_comilt_sd

int _mm_comilt_sd( __m128d a, __m128d b )

Synopsis

#include "emmintrin.h"
Instruction: comisd
CPUID Flag: SSE2
Category: Compare

Description

Compare the lower double-precision (64-bit) floating-point element in "a" and "b" for less-than, and return the boolean result (0 or 1).

Operation

RETURN ( a[63:0] < b[63:0] ) ? 1 : 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 4 | 1 | 2
Jaguar |  | 1 | 1
Sandy Bridge | 2 | 1 | 2
Ivy Bridge |  | 1 | 2
Haswell |  | 1 | 1
Broadwell |  | 1 | 1
Skylake |  | 1 | 1
Knights Landing | 7 | 7 | 2
Ivy Bridge | 2 | 1 |
Haswell | 2 | 1 |
Broadwell | 2 | 1 |
Skylake | 2 | 1 |


_mm_comilt_ss

int _mm_comilt_ss( __m128 a, __m128 b )

Synopsis

#include "xmmintrin.h"
Instruction: comiss
CPUID Flag: SSE
Category: Compare

Description

Compare the lower single-precision (32-bit) floating-point element in "a" and "b" for less-than, and return the boolean result (0 or 1).

Operation

RETURN ( a[31:0] < b[31:0] ) ? 1 : 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 4 | 1 | 2
Jaguar |  | 1 | 1
Sandy Bridge | 2 | 1 | 2
Ivy Bridge |  | 1 | 2
Haswell |  | 1 | 1
Broadwell |  | 1 | 1
Skylake |  | 1 | 1
Knights Landing | 7 | 7 | 2
Ivy Bridge | 2 | 1 |
Haswell | 2 | 1 |
Broadwell | 2 | 1 |
Skylake | 2 | 1 |


_mm_comineq_sd

int _mm_comineq_sd( __m128d a, __m128d b )

Synopsis

#include "emmintrin.h"
Instruction: comisd
CPUID Flag: SSE2
Category: Compare

Description

Compare the lower double-precision (64-bit) floating-point element in "a" and "b" for not-equal, and return the boolean result (0 or 1).

Operation

RETURN ( a[63:0] != b[63:0] ) ? 1 : 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 4 | 1 | 2
Jaguar |  | 1 | 1
Sandy Bridge | 2 | 1 | 2
Ivy Bridge |  | 1 | 2
Haswell |  | 1 | 1
Broadwell |  | 1 | 1
Skylake |  | 1 | 1
Knights Landing | 7 | 7 | 2
Ivy Bridge | 2 | 1 |
Haswell | 2 | 1 |
Broadwell | 2 | 1 |
Skylake | 2 | 1 |


_mm_comineq_ss

int _mm_comineq_ss( __m128 a, __m128 b )

Synopsis

#include "xmmintrin.h"
Instruction: comiss
CPUID Flag: SSE
Category: Compare

Description

Compare the lower single-precision (32-bit) floating-point element in "a" and "b" for not-equal, and return the boolean result (0 or 1).

Operation

RETURN ( a[31:0] != b[31:0] ) ? 1 : 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 4 | 1 | 2
Jaguar |  | 1 | 1
Sandy Bridge | 2 | 1 | 2
Ivy Bridge |  | 1 | 2
Haswell |  | 1 | 1
Broadwell |  | 1 | 1
Skylake |  | 1 | 1
Knights Landing | 7 | 7 | 2
Ivy Bridge | 2 | 1 |
Haswell | 2 | 1 |
Broadwell | 2 | 1 |
Skylake | 2 | 1 |


_mm_cos_pd

__m128d _mm_cos_pd( __m128d a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Trigonometry

Description

Compute the cosine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*64
    dst[i+63:i] := COS(a[i+63:i])
ENDFOR
dst[MAX:128] := 0


_mm_cos_ps

__m128 _mm_cos_ps( __m128 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Trigonometry

Description

Compute the cosine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := COS(a[i+31:i])
ENDFOR
dst[MAX:128] := 0


_mm_cosd_pd

__m128d _mm_cosd_pd( __m128d a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Trigonometry

Description

Compute the cosine of packed double-precision (64-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*64
    dst[i+63:i] := COSD(a[i+63:i])
ENDFOR
dst[MAX:128] := 0


_mm_cosd_ps

__m128 _mm_cosd_ps( __m128 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Trigonometry

Description

Compute the cosine of packed single-precision (32-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := COSD(a[i+31:i])
ENDFOR
dst[MAX:128] := 0


_mm_cosh_pd

__m128d _mm_cosh_pd( __m128d a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Trigonometry

Description

Compute the hyperbolic cosine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*64
    dst[i+63:i] := COSH(a[i+63:i])
ENDFOR
dst[MAX:128] := 0


_mm_cosh_ps

__m128 _mm_cosh_ps( __m128 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Trigonometry

Description

Compute the hyperbolic cosine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := COSH(a[i+31:i])
ENDFOR
dst[MAX:128] := 0


_mm_crc32_u16

unsigned int _mm_crc32_u16( unsigned int crc, unsigned short v )

Synopsis

#include "nmmintrin.h"
Instruction: crc32
CPUID Flag: SSE4.2
Category: Cryptography

Description

Starting with the initial value in "crc", accumulates a CRC32 value for unsigned 16-bit integer "v", and stores the result in "dst".

Operation

tmp1[15:0] := v[0:15] // bit reflection
tmp2[31:0] := crc[0:31] // bit reflection
tmp3[47:0] := tmp1[15:0] << 32
tmp4[47:0] := tmp2[31:0] << 16
tmp5[47:0] := tmp3[47:0] XOR tmp4[47:0]
tmp6[31:0] := MOD2(tmp5[47:0], 0x11EDC6F41) // remainder from polynomial division modulus 2
dst[31:0] := tmp6[0:31] // bit reflection

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 3 | 3
Jaguar | 3 | 2 | 3
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 3 | 1 | 1
Knights Landing | 7 | 2 | 2
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 3 | 1 |


_mm_crc32_u32

unsigned int _mm_crc32_u32( unsigned int crc, unsigned int v )

Synopsis

#include "nmmintrin.h"
Instruction: crc32
CPUID Flag: SSE4.2
Category: Cryptography

Description

Starting with the initial value in "crc", accumulates a CRC32 value for unsigned 32-bit integer "v", and stores the result in "dst".

Operation

tmp1[31:0] := v[0:31] // bit reflection
tmp2[31:0] := crc[0:31] // bit reflection
tmp3[63:0] := tmp1[31:0] << 32
tmp4[63:0] := tmp2[31:0] << 32
tmp5[63:0] := tmp3[63:0] XOR tmp4[63:0]
tmp6[31:0] := MOD2(tmp5[63:0], 0x11EDC6F41) // remainder from polynomial division modulus 2
dst[31:0] := tmp6[0:31] // bit reflection

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 3 | 3
Jaguar | 3 | 2 | 3
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 3 | 1 | 1
Knights Landing | 7 | 2 | 2
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 3 | 1 |


_mm_crc32_u64

unsigned __int64 _mm_crc32_u64( unsigned __int64 crc, unsigned __int64 v )

Synopsis

#include "nmmintrin.h"
Instruction: crc32
CPUID Flag: SSE4.2
Category: Cryptography

Description

Starting with the initial value in "crc", accumulates a CRC32 value for unsigned 64-bit integer "v", and stores the result in "dst".

Operation

tmp1[63:0] := v[0:63] // bit reflection
tmp2[31:0] := crc[0:31] // bit reflection
tmp3[95:0] := tmp1[31:0] << 32
tmp4[95:0] := tmp2[63:0] << 64
tmp5[95:0] := tmp3[95:0] XOR tmp4[95:0]
tmp6[31:0] := MOD2(tmp5[95:0], 0x11EDC6F41) // remainder from polynomial division modulus 2
dst[31:0] := tmp6[0:31] // bit reflection

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 3 | 3
Jaguar | 3 | 2 | 3
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 3 | 1 | 1
Knights Landing | 7 | 2 | 2
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 3 | 1 |


_mm_crc32_u8

unsigned int _mm_crc32_u8( unsigned int crc, unsigned char v )

Synopsis

#include "nmmintrin.h"
Instruction: crc32
CPUID Flag: SSE4.2
Category: Cryptography

Description

Starting with the initial value in "crc", accumulates a CRC32 value for unsigned 8-bit integer "v", and stores the result in "dst".

Operation

tmp1[7:0] := v[0:7] // bit reflection
tmp2[31:0] := crc[0:31] // bit reflection
tmp3[39:0] := tmp1[7:0] << 32
tmp4[39:0] := tmp2[31:0] << 8
tmp5[39:0] := tmp3[39:0] XOR tmp4[39:0]
tmp6[31:0] := MOD2(tmp5[39:0], 0x11EDC6F41) // remainder from polynomial division modulus 2
dst[31:0] := tmp6[0:31] // bit reflection

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 3 | 3
Jaguar | 3 | 2 | 3
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 3 | 1 | 1
Knights Landing | 7 | 2 | 2
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 3 | 1 |


_mm_csqrt_ps

__m128 _mm_csqrt_ps( __m128 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Elementary Math Functions

Description

Compute the square root of packed complex single-precision (32-bit) floating-point elements in "a", and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := SQRT(a[i+31:i])
ENDFOR
dst[MAX:128] := 0


_mm_cvt_pi2ps

__m128 _mm_cvt_pi2ps( __m128 a, __m64 b )

Synopsis

#include "xmmintrin.h"
Instruction: cvtpi2ps
CPUID Flag: SSE
Category: Convert

Description

Convert packed 32-bit integers in "b" to packed single-precision (32-bit) floating-point elements, store the results in the lower 2 elements of "dst", and copy the upper 2 packed elements from "a" to the upper elements of "dst".

Operation

dst[31:0] := Convert_Int32_To_FP32(b[31:0])
dst[63:32] := Convert_Int32_To_FP32(b[63:32])
dst[95:64] := a[95:64]
dst[127:96] := a[127:96]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 6 | 1 | 2
Jaguar | 4 | 1 | 1
Sandy Bridge | 4 | 2 | 1
Ivy Bridge | 4 |  | 1
Haswell | 4 | 4 | 1
Broadwell | 4 | 4 | 1
Skylake | 6 | 2 | 2
Knights Landing | 7 | 7 | 2


_mm_cvt_ps2pi

__m64 _mm_cvt_ps2pi( __m128 a )

Synopsis

#include "xmmintrin.h"
Instruction: cvtps2pi
CPUID Flag: SSE
Category: Convert

Description

Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst".

Operation

FOR j := 0 to 1
    i := 32*j
    dst[i+31:i] := Convert_FP32_To_Int32(a[i+31:i])
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 6 | 1 | 2
Jaguar | 4 | 1 | 1
Sandy Bridge | 4 | 1 | 2
Ivy Bridge | 4 | 1 | 2
Haswell | 4 | 1 | 2
Broadwell | 4 | 1 | 2
Skylake | 7 | 1 | 2
Knights Landing | 3 | 1 | 1


_mm_cvt_si2ss

__m128 _mm_cvt_si2ss( __m128 a, int b )

Synopsis

#include "xmmintrin.h"
Instruction: cvtsi2ss
CPUID Flag: SSE
Category: Convert

Description

Convert the 32-bit integer "b" to a single-precision (32-bit) floating-point element, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".

Operation

dst[31:0] := Convert_Int32_To_FP32(b[31:0])
dst[127:32] := a[127:32]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 8 | 1 | 2
Jaguar | 9 | 1 | 2
Sandy Bridge | 4 | 1.5 | 2
Ivy Bridge | 4 | 3 | 2
Haswell | 4 | 3 | 2
Broadwell | 5 | 4 | 3
Skylake | 7 | 2 | 3
Knights Landing | 5 | 1 | 1
Ivy Bridge | 5 | 1 |
Haswell | 4 | 1 |
Broadwell | 4 | 1 |
Skylake | 6 | 1 |


_mm_cvt_ss2si

int _mm_cvt_ss2si( __m128 a )

Synopsis

#include "xmmintrin.h"
Instruction: cvtss2si
CPUID Flag: SSE
Category: Convert

Description

Convert the lower single-precision (32-bit) floating-point element in "a" to a 32-bit integer, and store the result in "dst".

Operation

dst[31:0] := Convert_FP32_To_Int32(a[31:0])

Performance

Architecture | Latency | Throughput | μops
Ryzen | 7 | 1 | 2
Jaguar | 8 | 1 | 2
Sandy Bridge | 4 | 1 | 2
Ivy Bridge | 4 | 1 | 2
Haswell | 4 | 1 | 2
Broadwell | 4 | 1 | 2
Skylake | 7 | 1 | 3
Knights Landing | 6 | 7 | 2
Ivy Bridge | 5 | 1 |
Haswell | 4 | 1 |
Broadwell | 4 | 1 |
Skylake | 6 | 1 |


_mm_cvtepi16_epi32

__m128i _mm_cvtepi16_epi32( __m128i a )

Synopsis

#include "smmintrin.h"
Instruction: pmovsxwd
CPUID Flag: SSE4.1
Category: Convert

Description

Sign extend packed 16-bit integers in "a" to packed 32-bit integers, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := 32*j
    k := 16*j
    dst[i+31:i] := SignExtend(a[k+15:k])
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm_cvtepi16_epi64

__m128i _mm_cvtepi16_epi64( __m128i a )

Synopsis

#include "smmintrin.h"
Instruction: pmovsxwq
CPUID Flag: SSE4.1
Category: Convert

Description

Sign extend packed 16-bit integers in "a" to packed 64-bit integers, and store the results in "dst".

Operation

FOR j := 0 to 1
    i := 64*j
    k := 16*j
    dst[i+63:i] := SignExtend(a[k+15:k])
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm_cvtepi32_epi64

__m128i _mm_cvtepi32_epi64( __m128i a )

Synopsis

#include "smmintrin.h"
Instruction: pmovsxdq
CPUID Flag: SSE4.1
Category: Convert

Description

Sign extend packed 32-bit integers in "a" to packed 64-bit integers, and store the results in "dst".

Operation

FOR j := 0 to 1
    i := 64*j
    k := 32*j
    dst[i+63:i] := SignExtend(a[k+31:k])
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 8 | 7-8 | 2
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm_cvtepi32_pd

__m128d _mm_cvtepi32_pd( __m128i a )

Synopsis

#include "emmintrin.h"
Instruction: cvtdq2pd
CPUID Flag: SSE2
Category: Convert

Description

Convert packed 32-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*32
    m := j*64
    dst[m+63:m] := Convert_Int32_To_FP64(a[i+31:i])
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 6 | 1 | 2
Jaguar | 4 | 1 | 1
Sandy Bridge | 4 | 1 | 2
Ivy Bridge | 4 | 1 | 2
Haswell | 4 | 1 | 2
Broadwell | 4 | 1 | 2
Skylake | 5 | 1 | 2
Knights Landing | 7 | 7 | 2
Ivy Bridge | 4 | 1 |
Haswell | 4 | 1 |
Broadwell | 4 | 1 |
Skylake | 5 | 1 |


_mm_cvtepi32_ps

__m128 _mm_cvtepi32_ps( __m128i a )

Synopsis

#include "emmintrin.h"
Instruction: cvtdq2ps
CPUID Flag: SSE2
Category: Convert

Description

Convert packed 32-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := 32*j
    dst[i+31:i] := Convert_Int32_To_FP32(a[i+31:i])
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 4 | 1 | 1
Jaguar | 4 | 1 | 1
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 4 | 0.5 | 1
Knights Landing | 2 | 1 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 4 | 1 |


_mm_cvtepi8_epi16

__m128i _mm_cvtepi8_epi16( __m128i a )

Synopsis

#include "smmintrin.h"
Instruction: pmovsxbw
CPUID Flag: SSE4.1
Category: Convert

Description

Sign extend packed 8-bit integers in "a" to packed 16-bit integers, and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*8
    l := j*16
    dst[l+15:l] := SignExtend(a[i+7:i])
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 8 | 7-8 | 2
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm_cvtepi8_epi32

__m128i _mm_cvtepi8_epi32( __m128i a )

Synopsis

#include "smmintrin.h"
Instruction: pmovsxbd
CPUID Flag: SSE4.1
Category: Convert

Description

Sign extend packed 8-bit integers in "a" to packed 32-bit integers, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := 32*j
    k := 8*j
    dst[i+31:i] := SignExtend(a[k+7:k])
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 8 | 7-8 | 2
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm_cvtepi8_epi64

__m128i _mm_cvtepi8_epi64( __m128i a )

Synopsis

#include "smmintrin.h"
Instruction: pmovsxbq
CPUID Flag: SSE4.1
Category: Convert

Description

Sign extend packed 8-bit integers in the low 8 bytes of "a" to packed 64-bit integers, and store the results in "dst".

Operation

FOR j := 0 to 1
    i := 64*j
    k := 8*j
    dst[i+63:i] := SignExtend(a[k+7:k])
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 8 | 7-8 | 2
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm_cvtepu16_epi32

__m128i _mm_cvtepu16_epi32( __m128i a )

Synopsis

#include "smmintrin.h"
Instruction: pmovzxwd
CPUID Flag: SSE4.1
Category: Convert

Description

Zero extend packed unsigned 16-bit integers in "a" to packed 32-bit integers, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := 32*j
    k := 16*j
    dst[i+31:i] := ZeroExtend(a[k+15:k])
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm_cvtepu16_epi64

__m128i _mm_cvtepu16_epi64( __m128i a )

Synopsis

#include "smmintrin.h"
Instruction: pmovzxwq
CPUID Flag: SSE4.1
Category: Convert

Description

Zero extend packed unsigned 16-bit integers in "a" to packed 64-bit integers, and store the results in "dst".

Operation

FOR j := 0 to 1
    i := 64*j
    k := 16*j
    dst[i+63:i] := ZeroExtend(a[k+15:k])
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm_cvtepu32_epi64

__m128i _mm_cvtepu32_epi64( __m128i a )

Synopsis

#include "smmintrin.h"
Instruction: pmovzxdq
CPUID Flag: SSE4.1
Category: Convert

Description

Zero extend packed unsigned 32-bit integers in "a" to packed 64-bit integers, and store the results in "dst".

Operation

FOR j := 0 to 1
    i := 64*j
    k := 32*j
    dst[i+63:i] := ZeroExtend(a[k+31:k])
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 3 | 2 | 1
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm_cvtepu8_epi16

__m128i _mm_cvtepu8_epi16( __m128i a )

Synopsis

#include "smmintrin.h"
Instruction: pmovzxbw
CPUID Flag: SSE4.1
Category: Convert

Description

Zero extend packed unsigned 8-bit integers in "a" to packed 16-bit integers, and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*8
    l := j*16
    dst[l+15:l] := ZeroExtend(a[i+7:i])
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 3 | 2 | 1
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm_cvtepu8_epi32

__m128i _mm_cvtepu8_epi32( __m128i a )

Synopsis

#include "smmintrin.h"
Instruction: pmovzxbd
CPUID Flag: SSE4.1
Category: Convert

Description

Zero extend packed unsigned 8-bit integers in "a" to packed 32-bit integers, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := 32*j
    k := 8*j
    dst[i+31:i] := ZeroExtend(a[k+7:k])
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 3 | 2 | 1
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm_cvtepu8_epi64

__m128i _mm_cvtepu8_epi64( __m128i a )

Synopsis

#include "smmintrin.h"
Instruction: pmovzxbq
CPUID Flag: SSE4.1
Category: Convert

Description

Zero extend packed unsigned 8-bit integers in the low 8 byte sof "a" to packed 64-bit integers, and store the results in "dst".

Operation

FOR j := 0 to 1
    i := 64*j
    k := 8*j
    dst[i+63:i] := ZeroExtend(a[k+7:k])
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 3 | 2 | 1
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm_cvtm64_si64

__int64 _mm_cvtm64_si64( __m64 a )

Synopsis

#include "mmintrin.h"
Instruction: movq
CPUID Flag: MMX
Category: Convert

Description

Copy 64-bit integer "a" to "dst".

Operation

dst[63:0] := a[63:0]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.25 | 1
Jaguar | 4 | 1 | 1
Sandy Bridge | 1 |  | 1
Ivy Bridge | 1 | 0.33 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 2 | 1 | 1
Knights Landing | 4 | 1 | 1


_mm_cvtpd_epi32

__m128i _mm_cvtpd_epi32( __m128d a )

Synopsis

#include "emmintrin.h"
Instruction: cvtpd2dq
CPUID Flag: SSE2
Category: Convert

Description

Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst".

Operation

FOR j := 0 to 1
    i := 32*j
    k := 64*j
    dst[i+31:i] := Convert_FP64_To_Int32(a[k+63:k])
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 6 | 1 | 2
Jaguar | 4 | 1 | 1
Sandy Bridge | 4 | 1 | 2
Ivy Bridge | 4 | 1 | 2
Haswell | 4 | 1 | 2
Broadwell | 4 | 1 | 2
Skylake | 5 | 1 | 2
Knights Landing | 7 | 7 | 2
Ivy Bridge | 4 | 1 |
Haswell | 4 | 1 |
Broadwell | 4 | 1 |
Skylake | 5 | 1 |


_mm_cvtpd_pi32

__m64 _mm_cvtpd_pi32( __m128d a )

Synopsis

#include "emmintrin.h"
Instruction: cvtpd2pi
CPUID Flag: SSE2
Category: Convert

Description

Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst".

Operation

FOR j := 0 to 1
    i := 32*j
    k := 64*j
    dst[i+31:i] := Convert_FP64_To_Int32(a[k+63:k])
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Jaguar | 4 | 1 | 1


_mm_cvtpd_ps

__m128 _mm_cvtpd_ps( __m128d a )

Synopsis

#include "emmintrin.h"
Instruction: cvtpd2ps
CPUID Flag: SSE2
Category: Convert

Description

Convert packed double-precision (64-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".

Operation

FOR j := 0 to 1
    i := 32*j
    k := 64*j
    dst[i+31:i] := Convert_FP64_To_FP32(a[k+63:k])
ENDFOR
dst[127:64] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 1 | 1
Jaguar | 4 | 1 | 1
Sandy Bridge | 4 | 1 | 2
Ivy Bridge | 4 | 1 | 2
Haswell | 4 | 1 | 2
Broadwell | 4 | 1 | 2
Skylake | 5 | 1 | 2
Knights Landing | 7 | 7 | 2
Ivy Bridge | 4 | 1 |
Haswell | 4 | 1 |
Broadwell | 4 | 1 |
Skylake | 5 | 1 |


_mm_cvtph_ps

__m128 _mm_cvtph_ps( __m128i a )

Synopsis

#include "emmintrin.h"
Instruction: vcvtph2ps
CPUID Flag: FP16C
Category: Convert

Description

Convert packed half-precision (16-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    m := j*16
    dst[i+31:i] := Convert_FP16_To_FP32(a[m+15:m])
ENDFOR
dst[MAX:128] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 6 | 2 | 2
Jaguar | 5 | 2 | 2
Ivy Bridge | 6 | 1 | 2
Haswell | 4 | 1 | 2
Broadwell | 4-6 | 1 | 2
Skylake | 5-7 | 1 | 2
Knights Landing | 7 | 7 | 2
Ivy Bridge | 6 | 1 |
Haswell | 4 | 1 |
Broadwell | 4 | 1 |
Skylake | 5 | 1 |


_mm_cvtpi16_ps

__m128 _mm_cvtpi16_ps( __m64 a )

Synopsis

#include "xmmintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Convert

Description

Convert packed 16-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*16
    m := j*32
    dst[m+31:m] := Convert_Int16_To_FP32(a[i+15:i])
ENDFOR


_mm_cvtpi32_pd

__m128d _mm_cvtpi32_pd( __m64 a )

Synopsis

#include "emmintrin.h"
Instruction: cvtpi2pd
CPUID Flag: SSE2
Category: Convert

Description

Convert packed 32-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*32
    m := j*64
    dst[m+63:m] := Convert_Int32_To_FP64(a[i+31:i])
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 6 | 1 | 2
Jaguar | 4 | 1 | 1
Sandy Bridge | 4 | 1 | 2
Ivy Bridge | 4 | 1 | 2
Haswell | 4 | 1 | 2
Broadwell | 4 | 1 | 2
Skylake | 5 | 1 | 2
Knights Landing | 7 | 7 | 2


_mm_cvtpi32_ps

__m128 _mm_cvtpi32_ps( __m128 a, __m64 b )

Synopsis

#include "xmmintrin.h"
Instruction: cvtpi2ps
CPUID Flag: SSE
Category: Convert

Description

Convert packed 32-bit integers in "b" to packed single-precision (32-bit) floating-point elements, store the results in the lower 2 elements of "dst", and copy the upper 2 packed elements from "a" to the upper elements of "dst".

Operation

dst[31:0] := Convert_Int32_To_FP32(b[31:0])
dst[63:32] := Convert_Int32_To_FP32(b[63:32])
dst[95:64] := a[95:64]
dst[127:96] := a[127:96]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 6 | 1 | 2
Jaguar | 4 | 1 | 1
Sandy Bridge | 4 | 2 | 1
Ivy Bridge | 4 |  | 1
Haswell | 4 | 4 | 1
Broadwell | 4 | 4 | 1
Skylake | 6 | 2 | 2
Knights Landing | 7 | 7 | 2


_mm_cvtpi32x2_ps

__m128 _mm_cvtpi32x2_ps( __m64 a, __m64 b )

Synopsis

#include "xmmintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Convert

Description

Convert packed 32-bit integers in "a" to packed single-precision (32-bit) floating-point elements, store the results in the lower 2 elements of "dst", then covert the packed 32-bit integers in "a" to single-precision (32-bit) floating-point element, and store the results in the upper 2 elements of "dst".

Operation

dst[31:0] := Convert_Int32_To_FP32(a[31:0])
dst[63:32] := Convert_Int32_To_FP32(a[63:32])
dst[95:64] := Convert_Int32_To_FP32(b[31:0])
dst[127:96] := Convert_Int32_To_FP32(b[63:32])


_mm_cvtpi8_ps

__m128 _mm_cvtpi8_ps( __m64 a )

Synopsis

#include "xmmintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Convert

Description

Convert the lower packed 8-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*8
    m := j*32
    dst[m+31:m] := Convert_Int8_To_FP32(a[i+7:i])
ENDFOR


_mm_cvtps_epi32

__m128i _mm_cvtps_epi32( __m128 a )

Synopsis

#include "emmintrin.h"
Instruction: cvtps2dq
CPUID Flag: SSE2
Category: Convert

Description

Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := 32*j
    dst[i+31:i] := Convert_FP32_To_Int32(a[i+31:i])
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Jaguar | 4 | 1 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 4 | 1 |


_mm_cvtps_pd

__m128d _mm_cvtps_pd( __m128 a )

Synopsis

#include "emmintrin.h"
Instruction: cvtps2pd
CPUID Flag: SSE2
Category: Convert

Description

Convert packed single-precision (32-bit) floating-point elements in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst".

Operation

FOR j := 0 to 1
    i := 64*j
    k := 32*j
    dst[i+63:i] := Convert_FP32_To_FP64(a[k+31:k])
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 1 | 1
Jaguar | 3 | 1 | 1
Sandy Bridge | 3 | 1 | 2
Ivy Bridge | 1 | 1 | 2
Haswell | 2 | 1 | 2
Broadwell | 2 | 1 | 2
Skylake | 5 | 1 | 2
Knights Landing | 7 | 7 | 2
Ivy Bridge | 2 | 1 |
Haswell | 2 | 1 |
Broadwell | 2 | 1 |
Skylake | 5 | 1 |


_mm_cvtps_ph

__m128i _mm_cvtps_ph( __m128 a, int rounding )

Synopsis

#include "emmintrin.h"
Instruction: vcvtps2ph
CPUID Flag: FP16C
Category: Convert

Description

Convert packed single-precision (32-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst". [round_note]

Operation

FOR j := 0 to 3
    i := 16*j
    l := 32*j
    dst[i+15:i] := Convert_FP32_To_FP16(a[l+31:l])
ENDFOR
dst[MAX:128] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 6 | 2 | 2
Jaguar | 6 | 2 | 3
Ivy Bridge | 10 | 1 | 3
Haswell | 4 | 1 | 2
Broadwell | 4-6 | 1 | 2
Skylake | 5-7 | 1 | 2
Knights Landing | 7 | 7 | 2


_mm_cvtps_pi16

__m64 _mm_cvtps_pi16( __m128 a )

Synopsis

#include "xmmintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Convert

Description

Convert packed single-precision (32-bit) floating-point elements in "a" to packed 16-bit integers, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := 16*j
    k := 32*j
    dst[i+15:i] := Convert_FP32_To_Int16(a[k+31:k])
ENDFOR


_mm_cvtps_pi32

__m64 _mm_cvtps_pi32( __m128 a )

Synopsis

#include "xmmintrin.h"
Instruction: cvtps2pi
CPUID Flag: SSE
Category: Convert

Description

Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst".

Operation

FOR j := 0 to 1
    i := 32*j
    dst[i+31:i] := Convert_FP32_To_Int32(a[i+31:i])
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 6 | 1 | 2
Jaguar | 4 | 1 | 1
Sandy Bridge | 4 | 1 | 2
Ivy Bridge | 4 | 1 | 2
Haswell | 4 | 1 | 2
Broadwell | 4 | 1 | 2
Skylake | 7 | 1 | 2
Knights Landing | 3 | 1 | 1


_mm_cvtps_pi8

__m64 _mm_cvtps_pi8( __m128 a )

Synopsis

#include "xmmintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Convert

Description

Convert packed single-precision (32-bit) floating-point elements in "a" to packed 8-bit integers, and store the results in lower 4 elements of "dst".

Operation

FOR j := 0 to 3
    i := 8*j
    k := 32*j
    dst[i+7:i] := Convert_FP32_To_Int8(a[k+31:k])
ENDFOR


_mm_cvtpu16_ps

__m128 _mm_cvtpu16_ps( __m64 a )

Synopsis

#include "xmmintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Convert

Description

Convert packed unsigned 16-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*16
    m := j*32
    dst[m+31:m] := Convert_UnsignedInt16_To_FP32(a[i+15:i])
ENDFOR


_mm_cvtpu8_ps

__m128 _mm_cvtpu8_ps( __m64 a )

Synopsis

#include "xmmintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Convert

Description

Convert the lower packed unsigned 8-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*8
    m := j*32
    dst[m+31:m] := Convert_UnsignedInt8_To_FP32(a[i+7:i])
ENDFOR


_mm_cvtsd_f64

double _mm_cvtsd_f64( __m128d a )

Synopsis

#include "emmintrin.h"
Instruction: movsd
CPUID Flag: SSE2
Category: Convert

Description

Copy the lower double-precision (64-bit) floating-point element of "a" to "dst".

Operation

dst[63:0] := a[63:0]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.25 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 1 | 1
Ivy Bridge | 1 | 1 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 1 | 1 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm_cvtsd_si32

int _mm_cvtsd_si32( __m128d a )

Synopsis

#include "emmintrin.h"
Instruction: cvtsd2si
CPUID Flag: SSE2
Category: Convert

Description

Convert the lower double-precision (64-bit) floating-point element in "a" to a 32-bit integer, and store the result in "dst".

Operation

dst[31:0] := Convert_FP64_To_Int32(a[63:0])

Performance

Architecture | Latency | Throughput | μops
Ryzen | 7 | 1 | 2
Jaguar | 8 | 1 | 2
Sandy Bridge | 4 | 1 | 2
Ivy Bridge | 4 | 1 | 2
Haswell | 4 | 1 | 2
Broadwell | 4 | 1 | 2
Skylake | 6 | 1 | 2
Knights Landing | 6 | 7 | 2
Ivy Bridge | 5 | 1 |
Haswell | 4 | 1 |
Broadwell | 4 | 1 |
Skylake | 6 | 1 |


_mm_cvtsd_si64

__int64 _mm_cvtsd_si64( __m128d a )

Synopsis

#include "emmintrin.h"
Instruction: cvtsd2si
CPUID Flag: SSE2
Category: Convert

Description

Convert the lower double-precision (64-bit) floating-point element in "a" to a 64-bit integer, and store the result in "dst".

Operation

dst[63:0] := Convert_FP64_To_Int64(a[63:0])

Performance

Architecture | Latency | Throughput | μops
Ryzen | 7 | 1 | 2
Jaguar | 8 | 1 | 2
Sandy Bridge | 4 | 1 | 2
Ivy Bridge | 4 | 1 | 2
Haswell | 4 | 1 | 2
Broadwell | 4 | 1 | 2
Skylake | 6 | 1 | 2
Knights Landing | 6 | 7 | 2
Ivy Bridge | 5 | 1 |
Haswell | 4 | 1 |
Broadwell | 4 | 1 |
Skylake | 6 | 1 |


_mm_cvtsd_si64x

__int64 _mm_cvtsd_si64x( __m128d a )

Synopsis

#include "emmintrin.h"
Instruction: cvtsd2si
CPUID Flag: SSE2
Category: Convert

Description

Convert the lower double-precision (64-bit) floating-point element in "a" to a 64-bit integer, and store the result in "dst".

Operation

dst[63:0] := Convert_FP64_To_Int64(a[63:0])

Performance

Architecture | Latency | Throughput | μops
Ryzen | 7 | 1 | 2
Jaguar | 8 | 1 | 2
Sandy Bridge | 4 | 1 | 2
Ivy Bridge | 4 | 1 | 2
Haswell | 4 | 1 | 2
Broadwell | 4 | 1 | 2
Skylake | 6 | 1 | 2
Knights Landing | 6 | 7 | 2
Ivy Bridge | 5 | 1 |
Haswell | 4 | 1 |
Broadwell | 4 | 1 |
Skylake | 6 | 1 |


_mm_cvtsd_ss

__m128 _mm_cvtsd_ss( __m128 a, __m128d b )

Synopsis

#include "emmintrin.h"
Instruction: cvtsd2ss
CPUID Flag: SSE2
Category: Convert

Description

Convert the lower double-precision (64-bit) floating-point element in "b" to a single-precision (32-bit) floating-point element, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".

Operation

dst[31:0] := Convert_FP64_To_FP32(b[63:0])
dst[127:32] := a[127:31]
dst[MAX:64] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 1 | 1
Jaguar | 5 | 8 | 2
Sandy Bridge | 3 | 1 | 2
Ivy Bridge | 4 | 1 | 2
Haswell | 4 | 1 | 2
Broadwell | 4 | 1 | 2
Skylake | 5 | 1 | 2
Knights Landing | 2 | 1 | 1
Ivy Bridge | 4 | 1 |
Haswell | 4 | 1 |
Broadwell | 4 | 1 |
Skylake | 5 | 1 |


_mm_cvtsi128_si32

int _mm_cvtsi128_si32( __m128i a )

Synopsis

#include "emmintrin.h"
Instruction: movd
CPUID Flag: SSE2
Category: Convert

Description

Copy the lower 32-bit integer in "a" to "dst".

Operation

dst[31:0] := a[31:0]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 1 | 1
Jaguar | 4 | 1 | 1
Sandy Bridge | 1 |  | 1
Ivy Bridge | 1 | 1 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 2 | 1 | 1
Knights Landing | 4 | 1 | 1
Ivy Bridge | 1 | 1 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 2 | 1 |


_mm_cvtsi128_si64

__int64 _mm_cvtsi128_si64( __m128i a )

Synopsis

#include "emmintrin.h"
Instruction: movq
CPUID Flag: SSE2
Category: Convert

Description

Copy the lower 64-bit integer in "a" to "dst".

Operation

dst[63:0] := a[63:0]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.25 | 1
Jaguar | 4 | 1 | 1
Sandy Bridge | 1 |  | 1
Ivy Bridge | 1 | 0.33 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 2 | 1 | 1
Knights Landing | 4 | 1 | 1
Ivy Bridge | 1 | 0.33 |
Haswell | 1 | 0.33 |
Broadwell | 1 | 0.33 |
Skylake | 1 | 0.33 |


_mm_cvtsi128_si64x

__int64 _mm_cvtsi128_si64x( __m128i a )

Synopsis

#include "emmintrin.h"
Instruction: movq
CPUID Flag: SSE2
Category: Convert

Description

Copy the lower 64-bit integer in "a" to "dst".

Operation

dst[63:0] := a[63:0]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.25 | 1
Jaguar | 4 | 1 | 1
Sandy Bridge | 1 |  | 1
Ivy Bridge | 1 | 0.33 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 2 | 1 | 1
Knights Landing | 4 | 1 | 1
Ivy Bridge | 1 | 0.33 |
Haswell | 1 | 0.33 |
Broadwell | 1 | 0.33 |
Skylake | 1 | 0.33 |


_mm_cvtsi32_sd

__m128d _mm_cvtsi32_sd( __m128d a, int b )

Synopsis

#include "emmintrin.h"
Instruction: cvtsi2sd
CPUID Flag: SSE2
Category: Convert

Description

Convert the 32-bit integer "b" to a double-precision (64-bit) floating-point element, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".

Operation

dst[63:0] := Convert_Int32_To_FP64(b[31:0])
dst[127:64] := a[127:64]
dst[MAX:128] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 8 | 1 | 2
Jaguar | 9 | 1 | 2
Sandy Bridge | 4 | 1.5 | 2
Ivy Bridge | 4 | 3 | 2
Haswell | 4 | 3 | 2
Broadwell | 4 | 3 | 2
Skylake | 6 | 2 | 2
Knights Landing | 5 | 1 | 1
Ivy Bridge | 4 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 5 | 1 |


_mm_cvtsi32_si128

__m128i _mm_cvtsi32_si128( int a )

Synopsis

#include "emmintrin.h"
Instruction: movd
CPUID Flag: SSE2
Category: Convert

Description

Copy 32-bit integer "a" to the lower elements of "dst", and zero the upper elements of "dst".

Operation

dst[31:0] := a[31:0]
dst[127:32] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 1 | 1
Jaguar | 4 | 1 | 1
Sandy Bridge | 1 |  | 1
Ivy Bridge | 1 | 1 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 2 | 1 | 1
Knights Landing | 4 | 1 | 1
Ivy Bridge | 1 | 1 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 2 | 1 |


_mm_cvtsi32_si64

__m64 _mm_cvtsi32_si64( int a )

Synopsis

#include "mmintrin.h"
Instruction: movd
CPUID Flag: MMX
Category: Convert

Description

Copy 32-bit integer "a" to the lower elements of "dst", and zero the upper element of "dst".

Operation

dst[31:0] := a[31:0]
dst[63:32] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 1 | 1
Jaguar | 4 | 1 | 1
Sandy Bridge | 1 |  | 1
Ivy Bridge | 1 | 1 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 2 | 1 | 1
Knights Landing | 4 | 1 | 1


_mm_cvtsi32_ss

__m128 _mm_cvtsi32_ss( __m128 a, int b )

Synopsis

#include "xmmintrin.h"
Instruction: cvtsi2ss
CPUID Flag: SSE
Category: Convert

Description

Convert the 32-bit integer "b" to a single-precision (32-bit) floating-point element, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".

Operation

dst[31:0] := Convert_Int32_To_FP32(b[31:0])
dst[127:32] := a[127:32]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 8 | 1 | 2
Jaguar | 9 | 1 | 2
Sandy Bridge | 4 | 1.5 | 2
Ivy Bridge | 4 | 3 | 2
Haswell | 4 | 3 | 2
Broadwell | 5 | 4 | 3
Skylake | 7 | 2 | 3
Knights Landing | 5 | 1 | 1
Ivy Bridge | 5 | 1 |
Haswell | 4 | 1 |
Broadwell | 4 | 1 |
Skylake | 6 | 1 |


_mm_cvtsi64_m64

__m64 _mm_cvtsi64_m64( __int64 a )

Synopsis

#include "mmintrin.h"
Instruction: movq
CPUID Flag: MMX
Category: Convert

Description

Copy 64-bit integer "a" to "dst".

Operation

dst[63:0] := a[63:0]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.25 | 1
Jaguar | 4 | 1 | 1
Sandy Bridge | 1 |  | 1
Ivy Bridge | 1 | 0.33 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 2 | 1 | 1
Knights Landing | 4 | 1 | 1


_mm_cvtsi64_sd

__m128d _mm_cvtsi64_sd( __m128d a, __int64 b )

Synopsis

#include "emmintrin.h"
Instruction: cvtsi2sd
CPUID Flag: SSE2
Category: Convert

Description

Convert the 64-bit integer "b" to a double-precision (64-bit) floating-point element, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".

Operation

dst[63:0] := Convert_Int64_To_FP64(b[63:0])
dst[127:64] := a[127:64]
dst[MAX:128] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 8 | 1 | 2
Jaguar | 9 | 1 | 2
Sandy Bridge | 4 | 1.5 | 2
Ivy Bridge | 4 | 3 | 2
Haswell | 4 | 3 | 2
Broadwell | 4 | 3 | 2
Skylake | 6 | 2 | 2
Knights Landing | 5 | 1 | 1
Ivy Bridge | 4 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 5 | 1 |


_mm_cvtsi64_si128

__m128i _mm_cvtsi64_si128( __int64 a )

Synopsis

#include "emmintrin.h"
Instruction: movq
CPUID Flag: SSE2
Category: Convert

Description

Copy 64-bit integer "a" to the lower element of "dst", and zero the upper element.

Operation

dst[63:0] := a[63:0]
dst[127:64] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.25 | 1
Jaguar | 4 | 1 | 1
Sandy Bridge | 1 |  | 1
Ivy Bridge | 1 | 0.33 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 2 | 1 | 1
Knights Landing | 4 | 1 | 1
Ivy Bridge | 1 | 0.33 |
Haswell | 1 | 0.33 |
Broadwell | 1 | 0.33 |
Skylake | 1 | 0.33 |


_mm_cvtsi64_si32

int _mm_cvtsi64_si32( __m64 a )

Synopsis

#include "mmintrin.h"
Instruction: movd
CPUID Flag: MMX
Category: Convert

Description

Copy the lower 32-bit integer in "a" to "dst".

Operation

dst[31:0] := a[31:0]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 1 | 1
Jaguar | 4 | 1 | 1
Sandy Bridge | 1 |  | 1
Ivy Bridge | 1 | 1 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 2 | 1 | 1
Knights Landing | 4 | 1 | 1


_mm_cvtsi64_ss

__m128 _mm_cvtsi64_ss( __m128 a, __int64 b )

Synopsis

#include "xmmintrin.h"
Instruction: cvtsi2ss
CPUID Flag: SSE
Category: Convert

Description

Convert the 64-bit integer "b" to a single-precision (32-bit) floating-point element, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".

Operation

dst[31:0] := Convert_Int64_To_FP32(b[63:0])
dst[127:32] := a[127:32]
dst[MAX:128] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 8 | 1 | 2
Jaguar | 9 | 1 | 2
Sandy Bridge | 4 | 1.5 | 2
Ivy Bridge | 4 | 3 | 2
Haswell | 4 | 3 | 2
Broadwell | 5 | 4 | 3
Skylake | 7 | 2 | 3
Knights Landing | 5 | 1 | 1
Ivy Bridge | 5 | 1 |
Haswell | 4 | 1 |
Broadwell | 4 | 1 |
Skylake | 6 | 1 |


_mm_cvtsi64x_sd

__m128d _mm_cvtsi64x_sd( __m128d a, __int64 b )

Synopsis

#include "emmintrin.h"
Instruction: cvtsi2sd
CPUID Flag: SSE2
Category: Convert

Description

Convert the 64-bit integer "b" to a double-precision (64-bit) floating-point element, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".

Operation

dst[63:0] := Convert_Int64_To_FP64(b[63:0])
dst[127:64] := a[127:64]
dst[MAX:128] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 8 | 1 | 2
Jaguar | 9 | 1 | 2
Sandy Bridge | 4 | 1.5 | 2
Ivy Bridge | 4 | 3 | 2
Haswell | 4 | 3 | 2
Broadwell | 4 | 3 | 2
Skylake | 6 | 2 | 2
Knights Landing | 5 | 1 | 1
Ivy Bridge | 4 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 5 | 1 |


_mm_cvtsi64x_si128

__m128i _mm_cvtsi64x_si128( __int64 a )

Synopsis

#include "emmintrin.h"
Instruction: movq
CPUID Flag: SSE2
Category: Convert

Description

Copy 64-bit integer "a" to the lower element of "dst", and zero the upper element.

Operation

dst[63:0] := a[63:0]
dst[127:64] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.25 | 1
Jaguar | 4 | 1 | 1
Sandy Bridge | 1 |  | 1
Ivy Bridge | 1 | 0.33 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 2 | 1 | 1
Knights Landing | 4 | 1 | 1
Ivy Bridge | 1 | 0.33 |
Haswell | 1 | 0.33 |
Broadwell | 1 | 0.33 |
Skylake | 1 | 0.33 |


_mm_cvtss_f32

float _mm_cvtss_f32( __m128 a )

Synopsis

#include "xmmintrin.h"
Instruction: movss
CPUID Flag: SSE
Category: Convert

Description

Copy the lower single-precision (32-bit) floating-point element of "a" to "dst".

Operation

dst[31:0] := a[31:0]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.25 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 1 | 1
Ivy Bridge | 1 | 1 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 1 | 1 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm_cvtss_sd

__m128d _mm_cvtss_sd( __m128d a, __m128 b )

Synopsis

#include "emmintrin.h"
Instruction: cvtss2sd
CPUID Flag: SSE2
Category: Convert

Description

Convert the lower single-precision (32-bit) floating-point element in "b" to a double-precision (64-bit) floating-point element, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".

Operation

dst[63:0] := Convert_FP32_To_FP64(b[31:0])
dst[127:64] := a[127:64]
dst[MAX:64] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 1 | 1
Jaguar | 4 | 7 | 2
Sandy Bridge | 3 | 1 | 2
Ivy Bridge | 2 | 1 | 2
Haswell | 2 | 1 | 2
Broadwell | 2 | 1 | 2
Skylake | 5 | 2 | 2
Knights Landing | 2 | 1 | 1
Ivy Bridge | 2 | 1 |
Haswell | 2 | 1 |
Broadwell | 2 | 1 |
Skylake | 5 | 1 |


_mm_cvtss_si32

int _mm_cvtss_si32( __m128 a )

Synopsis

#include "xmmintrin.h"
Instruction: cvtss2si
CPUID Flag: SSE
Category: Convert

Description

Convert the lower single-precision (32-bit) floating-point element in "a" to a 32-bit integer, and store the result in "dst".

Operation

dst[31:0] := Convert_FP32_To_Int32(a[31:0])

Performance

Architecture | Latency | Throughput | μops
Ryzen | 7 | 1 | 2
Jaguar | 8 | 1 | 2
Sandy Bridge | 4 | 1 | 2
Ivy Bridge | 4 | 1 | 2
Haswell | 4 | 1 | 2
Broadwell | 4 | 1 | 2
Skylake | 7 | 1 | 3
Knights Landing | 6 | 7 | 2
Ivy Bridge | 5 | 1 |
Haswell | 4 | 1 |
Broadwell | 4 | 1 |
Skylake | 6 | 1 |


_mm_cvtss_si64

__int64 _mm_cvtss_si64( __m128 a )

Synopsis

#include "xmmintrin.h"
Instruction: cvtss2si
CPUID Flag: SSE
Category: Convert

Description

Convert the lower single-precision (32-bit) floating-point element in "a" to a 64-bit integer, and store the result in "dst".

Operation

dst[63:0] := Convert_FP32_To_Int64(a[31:0])

Performance

Architecture | Latency | Throughput | μops
Ryzen | 7 | 1 | 2
Jaguar | 8 | 1 | 2
Sandy Bridge | 4 | 1 | 2
Ivy Bridge | 4 | 1 | 2
Haswell | 4 | 1 | 2
Broadwell | 4 | 1 | 2
Skylake | 7 | 1 | 3
Knights Landing | 6 | 7 | 2
Ivy Bridge | 5 | 1 |
Haswell | 4 | 1 |
Broadwell | 4 | 1 |
Skylake | 6 | 1 |


_mm_cvtt_ps2pi

__m64 _mm_cvtt_ps2pi( __m128 a )

Synopsis

#include "xmmintrin.h"
Instruction: cvttps2pi
CPUID Flag: SSE
Category: Convert

Description

Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst".

Operation

FOR j := 0 to 1
    i := 32*j
    dst[i+31:i] := Convert_FP32_To_Int32_Truncate(a[i+31:i])
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 6 | 1 | 2
Jaguar | 4 | 1 | 1
Sandy Bridge | 4 | 1 | 2
Ivy Bridge | 4 | 1 | 2
Haswell | 4 | 1 | 2
Broadwell | 4 | 1 | 2
Skylake | 7 | 1 | 2
Knights Landing | 3 | 1 | 1


_mm_cvtt_ss2si

int _mm_cvtt_ss2si( __m128 a )

Synopsis

#include "xmmintrin.h"
Instruction: cvttss2si
CPUID Flag: SSE
Category: Convert

Description

Convert the lower single-precision (32-bit) floating-point element in "a" to a 32-bit integer with truncation, and store the result in "dst".

Operation

dst[31:0] := Convert_FP32_To_Int32_Truncate(a[31:0])

Performance

Architecture | Latency | Throughput | μops
Ryzen | 7 | 1 | 2
Jaguar | 8 | 1 | 2
Sandy Bridge | 4 | 1 | 2
Ivy Bridge | 4 | 1 | 2
Haswell | 4 | 1 | 2
Broadwell | 4 | 1 | 2
Skylake | 7 | 1 | 3
Knights Landing | 6 | 7 | 2
Ivy Bridge | 5 | 1 |
Haswell | 4 | 1 |
Broadwell | 4 | 1 |
Skylake | 6 | 1 |


_mm_cvttpd_epi32

__m128i _mm_cvttpd_epi32( __m128d a )

Synopsis

#include "emmintrin.h"
Instruction: cvttpd2dq
CPUID Flag: SSE2
Category: Convert

Description

Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst".

Operation

FOR j := 0 to 1
    i := 32*j
    k := 64*j
    dst[i+31:i] := Convert_FP64_To_Int32_Truncate(a[k+63:k])
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 6 | 1 | 2
Jaguar | 4 | 1 | 1
Sandy Bridge | 4 | 1 | 2
Ivy Bridge | 4 | 1 | 2
Haswell | 4 | 1 | 2
Broadwell | 4 | 1 | 2
Skylake | 5 | 1 | 2
Knights Landing | 7 | 7 | 2
Ivy Bridge | 4 | 1 |
Haswell | 4 | 1 |
Broadwell | 4 | 1 |
Skylake | 5 | 1 |


_mm_cvttpd_pi32

__m64 _mm_cvttpd_pi32( __m128d a )

Synopsis

#include "emmintrin.h"
Instruction: cvttpd2pi
CPUID Flag: SSE2
Category: Convert

Description

Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst".

Operation

FOR j := 0 to 1
    i := 32*j
    k := 64*j
    dst[i+31:i] := Convert_FP64_To_Int32_Truncate(a[k+63:k])
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Jaguar | 4 | 1 | 1


_mm_cvttps_epi32

__m128i _mm_cvttps_epi32( __m128 a )

Synopsis

#include "emmintrin.h"
Instruction: cvttps2dq
CPUID Flag: SSE2
Category: Convert

Description

Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := 32*j
    dst[i+31:i] := Convert_FP32_To_Int32_Truncate(a[i+31:i])
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Jaguar | 4 | 1 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 4 | 1 |


_mm_cvttps_pi32

__m64 _mm_cvttps_pi32( __m128 a )

Synopsis

#include "xmmintrin.h"
Instruction: cvttps2pi
CPUID Flag: SSE
Category: Convert

Description

Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst".

Operation

FOR j := 0 to 1
    i := 32*j
    dst[i+31:i] := Convert_FP32_To_Int32_Truncate(a[i+31:i])
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 6 | 1 | 2
Jaguar | 4 | 1 | 1
Sandy Bridge | 4 | 1 | 2
Ivy Bridge | 4 | 1 | 2
Haswell | 4 | 1 | 2
Broadwell | 4 | 1 | 2
Skylake | 7 | 1 | 2
Knights Landing | 3 | 1 | 1


_mm_cvttsd_si32

int _mm_cvttsd_si32( __m128d a )

Synopsis

#include "emmintrin.h"
Instruction: cvttsd2si
CPUID Flag: SSE2
Category: Convert

Description

Convert the lower double-precision (64-bit) floating-point element in "a" to a 32-bit integer with truncation, and store the result in "dst".

Operation

dst[31:0] := Convert_FP64_To_Int32_Truncate(a[63:0])

Performance

Architecture | Latency | Throughput | μops
Ryzen | 7 | 1 | 2
Jaguar | 8 | 1 | 2
Sandy Bridge | 4 | 1 | 2
Ivy Bridge | 4 | 1 | 2
Haswell | 4 | 1 | 2
Broadwell | 4 | 1 | 2
Skylake | 6 | 1 | 2
Knights Landing | 6 | 7 | 2
Ivy Bridge | 5 | 1 |
Haswell | 4 | 1 |
Broadwell | 4 | 1 |
Skylake | 6 | 1 |


_mm_cvttsd_si64

__int64 _mm_cvttsd_si64( __m128d a )

Synopsis

#include "emmintrin.h"
Instruction: cvttsd2si
CPUID Flag: SSE2
Category: Convert

Description

Convert the lower double-precision (64-bit) floating-point element in "a" to a 64-bit integer with truncation, and store the result in "dst".

Operation

dst[63:0] := Convert_FP64_To_Int64_Truncate(a[63:0])

Performance

Architecture | Latency | Throughput | μops
Ryzen | 7 | 1 | 2
Jaguar | 8 | 1 | 2
Sandy Bridge | 4 | 1 | 2
Ivy Bridge | 4 | 1 | 2
Haswell | 4 | 1 | 2
Broadwell | 4 | 1 | 2
Skylake | 6 | 1 | 2
Knights Landing | 6 | 7 | 2
Ivy Bridge | 5 | 1 |
Haswell | 4 | 1 |
Broadwell | 4 | 1 |
Skylake | 6 | 1 |


_mm_cvttsd_si64x

__int64 _mm_cvttsd_si64x( __m128d a )

Synopsis

#include "emmintrin.h"
Instruction: cvttsd2si
CPUID Flag: SSE2
Category: Convert

Description

Convert the lower double-precision (64-bit) floating-point element in "a" to a 64-bit integer with truncation, and store the result in "dst".

Operation

dst[63:0] := Convert_FP64_To_Int64_Truncate(a[63:0])

Performance

Architecture | Latency | Throughput | μops
Ryzen | 7 | 1 | 2
Jaguar | 8 | 1 | 2
Sandy Bridge | 4 | 1 | 2
Ivy Bridge | 4 | 1 | 2
Haswell | 4 | 1 | 2
Broadwell | 4 | 1 | 2
Skylake | 6 | 1 | 2
Knights Landing | 6 | 7 | 2
Ivy Bridge | 5 | 1 |
Haswell | 4 | 1 |
Broadwell | 4 | 1 |
Skylake | 6 | 1 |


_mm_cvttss_si32

int _mm_cvttss_si32( __m128 a )

Synopsis

#include "xmmintrin.h"
Instruction: cvttss2si
CPUID Flag: SSE
Category: Convert

Description

Convert the lower single-precision (32-bit) floating-point element in "a" to a 32-bit integer with truncation, and store the result in "dst".

Operation

dst[31:0] := Convert_FP32_To_Int32_Truncate(a[31:0])

Performance

Architecture | Latency | Throughput | μops
Ryzen | 7 | 1 | 2
Jaguar | 8 | 1 | 2
Sandy Bridge | 4 | 1 | 2
Ivy Bridge | 4 | 1 | 2
Haswell | 4 | 1 | 2
Broadwell | 4 | 1 | 2
Skylake | 7 | 1 | 3
Knights Landing | 6 | 7 | 2
Ivy Bridge | 5 | 1 |
Haswell | 4 | 1 |
Broadwell | 4 | 1 |
Skylake | 6 | 1 |


_mm_cvttss_si64

__int64 _mm_cvttss_si64( __m128 a )

Synopsis

#include "xmmintrin.h"
Instruction: cvttss2si
CPUID Flag: SSE
Category: Convert

Description

Convert the lower single-precision (32-bit) floating-point element in "a" to a 64-bit integer with truncation, and store the result in "dst".

Operation

dst[63:0] := Convert_FP64_To_Int32_Truncate(a[31:0])

Performance

Architecture | Latency | Throughput | μops
Ryzen | 7 | 1 | 2
Jaguar | 8 | 1 | 2
Sandy Bridge | 4 | 1 | 2
Ivy Bridge | 4 | 1 | 2
Haswell | 4 | 1 | 2
Broadwell | 4 | 1 | 2
Skylake | 7 | 1 | 3
Knights Landing | 6 | 7 | 2
Ivy Bridge | 5 | 1 |
Haswell | 4 | 1 |
Broadwell | 4 | 1 |
Skylake | 6 | 1 |


_mm_div_epi16

__m128i _mm_div_epi16( __m128i a, __m128i b )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Arithmetic

Description

Divide packed 16-bit integers in "a" by packed elements in "b", and store the truncated results in "dst".

Operation

FOR j := 0 to 7
    i := 16*j
    dst[i+15:i] := TRUNCATE(a[i+15:i] / b[i+15:i])
ENDFOR
dst[MAX:128] := 0


_mm_div_epi32

__m128i _mm_div_epi32( __m128i a, __m128i b )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Arithmetic

Description

Divide packed 32-bit integers in "a" by packed elements in "b", and store the truncated results in "dst".

Operation

FOR j := 0 to 3
    i := 32*j
    dst[i+31:i] := TRUNCATE(a[i+31:i] / b[i+31:i])
ENDFOR
dst[MAX:128] := 0


_mm_div_epi64

__m128i _mm_div_epi64( __m128i a, __m128i b )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Arithmetic

Description

Divide packed 64-bit integers in "a" by packed elements in "b", and store the truncated results in "dst".

Operation

FOR j := 0 to 1
    i := 64*j
    dst[i+63:i] := TRUNCATE(a[i+63:i] / b[i+63:i])
ENDFOR
dst[MAX:128] := 0


_mm_div_epi8

__m128i _mm_div_epi8( __m128i a, __m128i b )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Arithmetic

Description

Divide packed 8-bit integers in "a" by packed elements in "b", and store the truncated results in "dst".

Operation

FOR j := 0 to 15
    i := 8*j
    dst[i+7:i] := TRUNCATE(a[i+7:i] / b[i+7:i])
ENDFOR
dst[MAX:128] := 0


_mm_div_epu16

__m128i _mm_div_epu16( __m128i a, __m128i b )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Arithmetic

Description

Divide packed unsigned 16-bit integers in "a" by packed elements in "b", and store the truncated results in "dst".

Operation

FOR j := 0 to 7
    i := 16*j
    dst[i+15:i] := TRUNCATE(a[i+15:i] / b[i+15:i])
ENDFOR
dst[MAX:128] := 0


_mm_div_epu32

__m128i _mm_div_epu32( __m128i a, __m128i b )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Arithmetic

Description

Divide packed unsigned 32-bit integers in "a" by packed elements in "b", and store the truncated results in "dst".

Operation

FOR j := 0 to 3
    i := 32*j
    dst[i+31:i] := TRUNCATE(a[i+31:i] / b[i+31:i])
ENDFOR
dst[MAX:128] := 0


_mm_div_epu64

__m128i _mm_div_epu64( __m128i a, __m128i b )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Arithmetic

Description

Divide packed unsigned 64-bit integers in "a" by packed elements in "b", and store the truncated results in "dst".

Operation

FOR j := 0 to 1
    i := 64*j
    dst[i+63:i] := TRUNCATE(a[i+63:i] / b[i+63:i])
ENDFOR
dst[MAX:128] := 0


_mm_div_epu8

__m128i _mm_div_epu8( __m128i a, __m128i b )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Arithmetic

Description

Divide packed unsigned 8-bit integers in "a" by packed elements in "b", and store the truncated results in "dst".

Operation

FOR j := 0 to 15
    i := 8*j
    dst[i+7:i] := TRUNCATE(a[i+7:i] / b[i+7:i])
ENDFOR
dst[MAX:128] := 0


_mm_div_pd

__m128d _mm_div_pd( __m128d a, __m128d b )

Synopsis

#include "emmintrin.h"
Instruction: divpd
CPUID Flag: SSE2
Category: Arithmetic

Description

Divide packed double-precision (64-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst".

Operation

FOR j := 0 to 1
    i := 64*j
    dst[i+63:i] := a[i+63:i] / b[i+63:i]
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 8-13 | 4-5 | 1
Jaguar | 19 | 19 | 1
Sandy Bridge | 10-22 | 10-22 | 1
Ivy Bridge | 10-20 | 8-14 | 1
Haswell | 10-20 | 8-14 | 1
Broadwell | 10-14 | 8 | 1
Skylake | 13-14 | 4 | 1
Knights Landing | 32 | 20 | 18
Ivy Bridge | 15-20 | 14 |
Haswell | 14-20 | 13 |
Broadwell | <14 | 8 |
Skylake | 14 | 4 |
Knights Landing | 38 | ~10 |


_mm_div_ps

__m128 _mm_div_ps( __m128 a, __m128 b )

Synopsis

#include "xmmintrin.h"
Instruction: divps
CPUID Flag: SSE
Category: Arithmetic

Description

Divide packed single-precision (32-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst".

Operation

FOR j := 0 to 3
    i := 32*j
    dst[i+31:i] := a[i+31:i] / b[i+31:i]
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 10 | 3 | 1
Jaguar | 19 | 19 | 1
Sandy Bridge | 10-14 | 10-14 | 1
Ivy Bridge | 10-13 | 7 | 1
Haswell | 10-13 | 7 | 1
Broadwell | 11 | 5 | 1
Skylake | 11 | 3 | 1
Knights Landing | 32 | 20 | 18
Ivy Bridge | 14-Nov | 6 |
Haswell | <13 | 6 |
Broadwell | <11 | 4 |
Skylake | 11 | 3 |
Knights Landing | 38 | ~10 |


_mm_div_sd

__m128d _mm_div_sd( __m128d a, __m128d b )

Synopsis

#include "emmintrin.h"
Instruction: divsd
CPUID Flag: SSE2
Category: Arithmetic

Description

Divide the lower double-precision (64-bit) floating-point element in "a" by the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".

Operation

dst[63:0] := a[63:0] / b[63:0]
dst[127:64] := a[127:64]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 8-13 | 4-5 | 1
Jaguar | 19 | 19 | 1
Sandy Bridge | 10-22 | 10-22 | 1
Ivy Bridge | 10-20 | 8-14 | 1
Haswell | 10-20 | 8-14 | 1
Broadwell | 10-14 | 4-5 | 1
Skylake | 13-14 | 4 | 1
Knights Landing | 42 | 42 | 3
Ivy Bridge | 15-20 | 14 |
Haswell | 14-20 | 13 |
Broadwell | <14 | 5 |
Skylake | 14 | 4 |
Knights Landing | 40 | ~33 |


_mm_div_ss

__m128 _mm_div_ss( __m128 a, __m128 b )

Synopsis

#include "xmmintrin.h"
Instruction: divss
CPUID Flag: SSE
Category: Arithmetic

Description

Divide the lower single-precision (32-bit) floating-point element in "a" by the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".

Operation

dst[31:0] := a[31:0] / b[31:0]
dst[127:32] := a[127:32]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 10 | 3 | 1
Jaguar | 14 | 14 | 1
Sandy Bridge | 10-14 | 10-14 | 1
Ivy Bridge | 10-13 | 7 | 1
Haswell | 10-13 | 7 | 1
Broadwell | 11 | 2.5 | 1
Skylake | 11 | 3 | 1
Knights Landing | 27 | 17 | 3
Ivy Bridge | 14-Nov | 6 |
Haswell | <13 | 6 |
Broadwell | <11 | 2.5 |
Skylake | 11 | 3 |
Knights Landing | 25 | ~20 |


_mm_dp_pd

__m128d _mm_dp_pd( __m128d a, __m128d b, const int imm8 )

Synopsis

#include "smmintrin.h"
Instruction: dppd
CPUID Flag: SSE4.1
Category: Arithmetic

Description

Conditionally multiply the packed double-precision (64-bit) floating-point elements in "a" and "b" using the high 4 bits in "imm8", sum the four products, and conditionally store the sum in "dst" using the low 4 bits of "imm8".

Operation

DEFINE DP(a[127:0], b[127:0], imm8[7:0]) {
    FOR j := 0 to 1
        i := j*64
        IF imm8[(4+j)%8]
            temp[i+63:i] := a[i+63:i] * b[i+63:i]
        ELSE
            temp[i+63:i] := 0
        FI
    ENDFOR

    sum[63:0] := temp[127:64] + temp[63:0]

    FOR j := 0 to 1
        i := j*64
        IF imm8[j%8]
            tmpdst[i+63:i] := sum[63:0]
        ELSE
            tmpdst[i+63:i] := 0
        FI
    ENDFOR
    RETURN tmpdst[127:0]
}
dst[127:0] := DP(a[127:0], b[127:0], imm8[7:0])

Performance

Architecture | Latency | Throughput | μops
Ryzen | 10 | 3 | 3
Jaguar | 9 | 3 | 3
Sandy Bridge | 9 | 2 | 3
Ivy Bridge | 9 | 1 | 3
Haswell | 9 | 1 | 3
Broadwell | 7 | 1 | 3
Skylake | 9 | 1 | 3
Knights Landing | 24 | 13 | 12
Ivy Bridge | 9 | 1 |
Haswell | 9 | 1 |
Broadwell | 7 | 1 |
Skylake | 9 | 1 |


_mm_dp_ps

__m128 _mm_dp_ps( __m128 a, __m128 b, const int imm8 )

Synopsis

#include "smmintrin.h"
Instruction: dpps
CPUID Flag: SSE4.1
Category: Arithmetic

Description

Conditionally multiply the packed single-precision (32-bit) floating-point elements in "a" and "b" using the high 4 bits in "imm8", sum the four products, and conditionally store the sum in "dst" using the low 4 bits of "imm8".

Operation

DEFINE DP(a[127:0], b[127:0], imm8[7:0]) {
    FOR j := 0 to 3
        i := j*32
        IF imm8[(4+j)%8]
            temp[i+31:i] := a[i+31:i] * b[i+31:i]
        ELSE
            temp[i+31:i] := 0
        FI
    ENDFOR

    sum[31:0] := (temp[127:96] + temp[95:64]) + (temp[63:32] + temp[31:0])

    FOR j := 0 to 3
        i := j*32
        IF imm8[j%8]
            tmpdst[i+31:i] := sum[31:0]
        ELSE
            tmpdst[i+31:i] := 0
        FI
    ENDFOR
    RETURN tmpdst[127:0]
}
dst[127:0] := DP(a[127:0], b[127:0], imm8[7:0])

Performance

Architecture | Latency | Throughput | μops
Ryzen | 15 | 4 | 8
Jaguar | 11 | 4 | 5
Sandy Bridge | 12 | 2 | 4
Ivy Bridge | 12 | 2 | 4
Haswell | 14 | 2 | 4
Broadwell | 12 | 2 | 4
Skylake | 13 | 1.5 | 4
Knights Landing | 36 | 14 | 14
Ivy Bridge | 13 | 2 |
Haswell | 14 | 2 |
Broadwell | 12 | 2 |
Skylake | 13 | 2 |


_mm_empty

void _mm_empty( void )

Synopsis

#include "mmintrin.h"
Instruction: emms
CPUID Flag: MMX
Category: General Support

Description

Empty the MMX state, which marks the x87 FPU registers as available for use by x87 instructions. This instruction must be used at the end of all MMX technology procedures.

Performance

Architecture | Latency | Throughput | μops
Ryzen |  | 0.25 | 1
Jaguar |  | 0.5 | 1
Sandy Bridge |  | 18 | 31
Ivy Bridge |  | 18 | 31
Haswell |  | 13 | 31
Broadwell |  | 12 | 31
Skylake |  | 6 | 10
Knights Landing |  | 13 | 10


_mm_erf_pd

__m128d _mm_erf_pd( __m128d a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Arithmetic

Description

Compute the error function of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*64
    dst[i+63:i] := ERF(a[i+63:i])
ENDFOR
dst[MAX:128] := 0


_mm_erf_ps

__m128 _mm_erf_ps( __m128 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Probability/Statistics

Description

Compute the error function of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := ERF(a[i+31:i])
ENDFOR
dst[MAX:128] := 0


_mm_erfc_pd

__m128d _mm_erfc_pd( __m128d a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Probability/Statistics

Description

Compute the complementary error function of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*64
    dst[i+63:i] := 1.0 - ERF(a[i+63:i])
ENDFOR
dst[MAX:128] := 0


_mm_erfc_ps

__m128 _mm_erfc_ps( __m128 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Probability/Statistics

Description

Compute the complementary error function of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := 1.0 - ERF(a[i+31:i])
ENDFOR
dst[MAX:128] := 0


_mm_erfcinv_pd

__m128d _mm_erfcinv_pd( __m128d a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Probability/Statistics

Description

Compute the inverse complementary error function of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*64
    dst[i+63:i] := 1.0 / (1.0 - ERF(a[i+63:i]))
ENDFOR
dst[MAX:128] := 0


_mm_erfcinv_ps

__m128 _mm_erfcinv_ps( __m128 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Probability/Statistics

Description

Compute the inverse complementary error function of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := 1.0 / (1.0 - ERF(a[i+31:i]))
ENDFOR
dst[MAX:128] := 0


_mm_erfinv_pd

__m128d _mm_erfinv_pd( __m128d a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Probability/Statistics

Description

Compute the inverse error function of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*64
    dst[i+63:i] := 1.0 / ERF(a[i+63:i])
ENDFOR
dst[MAX:128] := 0


_mm_erfinv_ps

__m128 _mm_erfinv_ps( __m128 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Probability/Statistics

Description

Compute the inverse error function of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := 1.0 / ERF(a[i+31:i])
ENDFOR
dst[MAX:128] := 0


_mm_exp_pd

__m128d _mm_exp_pd( __m128d a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Elementary Math Functions

Description

Compute the exponential value of "e" raised to the power of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*64
    dst[i+63:i] := e^(a[i+63:i])
ENDFOR
dst[MAX:128] := 0


_mm_exp_ps

__m128 _mm_exp_ps( __m128 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Elementary Math Functions

Description

Compute the exponential value of "e" raised to the power of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := e^(a[i+31:i])
ENDFOR
dst[MAX:128] := 0


_mm_exp10_pd

__m128d _mm_exp10_pd( __m128d a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Elementary Math Functions

Description

Compute the exponential value of 10 raised to the power of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*64
    dst[i+63:i] := 10^(a[i+63:i])
ENDFOR
dst[MAX:128] := 0


_mm_exp10_ps

__m128 _mm_exp10_ps( __m128 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Elementary Math Functions

Description

Compute the exponential value of 10 raised to the power of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := 10^(a[i+31:i])
ENDFOR
dst[MAX:128] := 0


_mm_exp2_pd

__m128d _mm_exp2_pd( __m128d a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Elementary Math Functions

Description

Compute the exponential value of 2 raised to the power of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*64
    dst[i+63:i] := 2^(a[i+63:i])
ENDFOR
dst[MAX:128] := 0


_mm_exp2_ps

__m128 _mm_exp2_ps( __m128 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Elementary Math Functions

Description

Compute the exponential value of 2 raised to the power of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := 2^(a[i+31:i])
ENDFOR
dst[MAX:128] := 0


_mm_expm1_pd

__m128d _mm_expm1_pd( __m128d a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Elementary Math Functions

Description

Compute the exponential value of "e" raised to the power of packed double-precision (64-bit) floating-point elements in "a", subtract one from each element, and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*64
    dst[i+63:i] := e^(a[i+63:i]) - 1.0
ENDFOR
dst[MAX:128] := 0


_mm_expm1_ps

__m128 _mm_expm1_ps( __m128 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Elementary Math Functions

Description

Compute the exponential value of "e" raised to the power of packed single-precision (32-bit) floating-point elements in "a", subtract one from each element, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := e^(a[i+31:i]) - 1.0
ENDFOR
dst[MAX:128] := 0


_mm_extract_epi16

int _mm_extract_epi16( __m128i a, int imm8 )

Synopsis

#include "emmintrin.h"
Instruction: pextrw
CPUID Flag: SSE2
Category: Swizzle

Description

Extract a 16-bit integer from "a", selected with "imm8", and store the result in the lower element of "dst".

Operation

dst[15:0] := (a[127:0] >> (imm8[2:0] * 16))[15:0]
dst[31:16] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 1 | 2
Jaguar | 4 | 1 | 1
Sandy Bridge | 2 | 1 | 2
Ivy Bridge | 2 | 1 | 2
Haswell | 2 | 1 | 2
Broadwell | 2 | 1 | 2
Skylake | 3 | 1 | 2
Knights Landing | 8 | 7 | 2
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 3 | 1 |


_mm_extract_epi32

int _mm_extract_epi32( __m128i a, const int imm8 )

Synopsis

#include "smmintrin.h"
Instruction: pextrd
CPUID Flag: SSE4.1
Category: Swizzle

Description

Extract a 32-bit integer from "a", selected with "imm8", and store the result in "dst".

Operation

dst[31:0] := (a[127:0] >> (imm8[1:0] * 32))[31:0]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 1 | 2
Jaguar | 3 | 1 | 1
Sandy Bridge | 2 | 1 | 2
Ivy Bridge | 2 | 1 | 2
Haswell | 2 | 1 | 2
Broadwell | 2 | 1 | 2
Skylake | 3 | 1 | 2
Knights Landing | 8 | 7 | 2
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 3 | 1 |


_mm_extract_epi64

__int64 _mm_extract_epi64( __m128i a, const int imm8 )

Synopsis

#include "smmintrin.h"
Instruction: pextrq
CPUID Flag: SSE4.1
Category: Swizzle

Description

Extract a 64-bit integer from "a", selected with "imm8", and store the result in "dst".

Operation

dst[63:0] := (a[127:0] >> (imm8[0] * 64))[63:0]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 1 | 2
Jaguar | 3 | 1 | 1
Sandy Bridge | 2 | 1 | 2
Ivy Bridge | 2 | 1 | 2
Haswell | 2 | 1 | 2
Broadwell | 2 | 1 | 2
Skylake | 3 | 1 | 2
Knights Landing | 8 | 10 | 2


_mm_extract_epi8

int _mm_extract_epi8( __m128i a, const int imm8 )

Synopsis

#include "smmintrin.h"
Instruction: pextrb
CPUID Flag: SSE4.1
Category: Swizzle

Description

Extract an 8-bit integer from "a", selected with "imm8", and store the result in the lower element of "dst".

Operation

dst[7:0] := (a[127:0] >> (imm8[3:0] * 8))[7:0]
dst[31:8] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 1 | 2
Jaguar | 3 | 1 | 1
Sandy Bridge | 2 | 1 | 2
Ivy Bridge | 2 | 1 | 2
Haswell | 2 | 1 | 2
Broadwell | 2 | 1 | 2
Skylake | 3 | 1 | 2
Knights Landing | 8 | 7 | 2
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 3 | 1 |


_mm_extract_pi16

int _mm_extract_pi16( __m64 a, int imm8 )

Synopsis

#include "xmmintrin.h"
Instruction: pextrw
CPUID Flag: SSE
Category: Swizzle

Description

Extract a 16-bit integer from "a", selected with "imm8", and store the result in the lower element of "dst".

Operation

dst[15:0] := (a[63:0] >> (imm8[1:0] * 16))[15:0]
dst[31:16] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 1 | 2
Jaguar | 4 | 1 | 1
Sandy Bridge | 2 | 1 | 2
Ivy Bridge | 2 | 1 | 2
Haswell | 2 | 1 | 2
Broadwell | 2 | 1 | 2
Skylake | 3 | 1 | 2
Knights Landing | 8 | 7 | 2


_mm_extract_ps

int _mm_extract_ps( __m128 a, const int imm8 )

Synopsis

#include "smmintrin.h"
Instruction: extractps
CPUID Flag: SSE4.1
Category: Swizzle

Description

Extract a single-precision (32-bit) floating-point element from "a", selected with "imm8", and store the result in "dst".

Operation

dst[31:0] := (a[127:0] >> (imm8[1:0] * 32))[31:0]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 1 | 2
Jaguar | 3 | 1 | 1
Sandy Bridge | 2 | 1 | 2
Ivy Bridge | 2 | 1 | 2
Haswell |  | 1 | 2
Broadwell |  | 1 | 2
Skylake |  | 1 | 2
Knights Landing | 8 | 7 | 2
Ivy Bridge | 2 | 1 |
Haswell | 2 | 1 |
Broadwell | 2 | 1 |
Skylake | 3 | 1 |


_mm_floor_pd

__m128d _mm_floor_pd( __m128d a )

Synopsis

#include "smmintrin.h"
Instruction: roundpd
CPUID Flag: SSE4.1
Category: Special Math Functions

Description

Round the packed double-precision (64-bit) floating-point elements in "a" down to an integer value, and store the results as packed double-precision floating-point elements in "dst".

Operation

FOR j := 0 to 1
    i := j*64
    dst[i+63:i] := FLOOR(a[i+63:i])
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 4 | 1 | 1
Jaguar | 4 | 1 | 1
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 6 | 2 | 2
Broadwell | 6 | 2 | 2
Skylake | 8 | 1 | 2
Knights Landing | 6 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 6 | 2 |
Broadwell | 6 | 2 |
Skylake | 6 | 2 |


_mm_floor_ps

__m128 _mm_floor_ps( __m128 a )

Synopsis

#include "smmintrin.h"
Instruction: roundps
CPUID Flag: SSE4.1
Category: Special Math Functions

Description

Round the packed single-precision (32-bit) floating-point elements in "a" down to an integer value, and store the results as packed single-precision floating-point elements in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := FLOOR(a[i+31:i])
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 4 | 1 | 1
Jaguar | 4 | 1 | 1
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 6 | 2 | 2
Broadwell | 6 | 2 | 2
Skylake | 8 | 1 | 2
Knights Landing | 6 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 6 | 2 |
Broadwell | 6 | 2 |
Skylake | 6 | 2 |


_mm_floor_sd

__m128d _mm_floor_sd( __m128d a, __m128d b )

Synopsis

#include "smmintrin.h"
Instruction: roundsd
CPUID Flag: SSE4.1
Category: Special Math Functions

Description

Round the lower double-precision (64-bit) floating-point element in "b" down to an integer value, store the result as a double-precision floating-point element in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".

Operation

dst[63:0] := FLOOR(b[63:0])
dst[127:64] := a[127:64]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 4 | 1 | 1
Jaguar | 4 | 1 | 1
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 6 | 2 | 2
Broadwell | 6 | 2 | 2
Skylake | 8 | 1 | 2
Knights Landing | 6 | 2 | 1
Ivy Bridge | 3 | 1 |
Haswell | 6 | 2 |
Broadwell | 6 | 2 |
Skylake | 6 | 2 |


_mm_floor_ss

__m128 _mm_floor_ss( __m128 a, __m128 b )

Synopsis

#include "smmintrin.h"
Instruction: roundss
CPUID Flag: SSE4.1
Category: Special Math Functions

Description

Round the lower single-precision (32-bit) floating-point element in "b" down to an integer value, store the result as a single-precision floating-point element in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".

Operation

dst[31:0] := FLOOR(b[31:0])
dst[127:32] := a[127:32]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 4 | 1 | 1
Jaguar | 4 | 1 | 1
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 6 | 2 | 2
Broadwell | 6 | 2 | 2
Skylake | 8 | 1 | 2
Knights Landing | 6 | 2 | 1
Ivy Bridge | 3 | 1 |
Haswell | 6 | 2 |
Broadwell | 6 | 2 |
Skylake | 6 | 2 |


_mm_fmadd_pd

__m128d _mm_fmadd_pd( __m128d a, __m128d b, __m128d c )

Synopsis

#include "immintrin.h"
Instruction: vfmadd132pd
CPUID Flag: FMA
Category: Arithmetic

Description

Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*64
    dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
ENDFOR
dst[MAX:128] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 5 | 0.5 | 1
Haswell | 5 | 0.5 |
Broadwell | 5 | 0.5 |
Skylake | 4 | 0.5 |
Knights Landing | 6 | 0.5 |


_mm_fmadd_ps

__m128 _mm_fmadd_ps( __m128 a, __m128 b, __m128 c )

Synopsis

#include "immintrin.h"
Instruction: vfmadd132ps
CPUID Flag: FMA
Category: Arithmetic

Description

Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
ENDFOR
dst[MAX:128] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 5 | 0.5 | 1
Haswell | 5 | 0.5 |
Broadwell | 5 | 0.5 |
Skylake | 4 | 0.5 |
Knights Landing | 6 | 0.5 |


_mm_fmadd_sd

__m128d _mm_fmadd_sd( __m128d a, __m128d b, __m128d c )

Synopsis

#include "immintrin.h"
Instruction: vfmadd132sd
CPUID Flag: FMA
Category: Arithmetic

Description

Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and add the intermediate result to the lower element in "c". Store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".

Operation

dst[63:0] := (a[63:0] * b[63:0]) + c[63:0]
dst[127:64] := a[127:64]
dst[MAX:128] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 5 | 0.5 | 1
Haswell | 5 | 0.5 |
Broadwell | 5 | 0.5 |
Skylake | 4 | 0.5 |
Knights Landing | 6 | 0.5 |


_mm_fmadd_ss

__m128 _mm_fmadd_ss( __m128 a, __m128 b, __m128 c )

Synopsis

#include "immintrin.h"
Instruction: vfmadd132ss
CPUID Flag: FMA
Category: Arithmetic

Description

Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and add the intermediate result to the lower element in "c". Store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".

Operation

dst[31:0] := (a[31:0] * b[31:0]) + c[31:0]
dst[127:32] := a[127:32]
dst[MAX:128] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 5 | 0.5 | 1
Haswell | 5 | 0.5 |
Broadwell | 5 | 0.5 |
Skylake | 4 | 0.5 |
Knights Landing | 6 | 0.5 |


_mm_fmaddsub_pd

__m128d _mm_fmaddsub_pd( __m128d a, __m128d b, __m128d c )

Synopsis

#include "immintrin.h"
Instruction: vfmaddsub132pd
CPUID Flag: FMA
Category: Arithmetic

Description

Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*64
    IF (j % 1 == 0)
        dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
    ELSE
        dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
    FI
ENDFOR
dst[MAX:128] := 0

Performance

Architecture | Latency | Throughput | μops
Haswell | 5 | 0.5 |
Broadwell | 5 | 0.5 |
Skylake | 4 | 0.5 |
Knights Landing | 6 | 0.5 |


_mm_fmaddsub_ps

__m128 _mm_fmaddsub_ps( __m128 a, __m128 b, __m128 c )

Synopsis

#include "immintrin.h"
Instruction: vfmaddsub132ps
CPUID Flag: FMA
Category: Arithmetic

Description

Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    IF (j % 1 == 0)
        dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
    ELSE
        dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
    FI
ENDFOR
dst[MAX:128] := 0

Performance

Architecture | Latency | Throughput | μops
Haswell | 5 | 0.5 |
Broadwell | 5 | 0.5 |
Skylake | 4 | 0.5 |
Knights Landing | 6 | 0.5 |


_mm_fmsub_pd

__m128d _mm_fmsub_pd( __m128d a, __m128d b, __m128d c )

Synopsis

#include "immintrin.h"
Instruction: vfmsub132pd
CPUID Flag: FMA
Category: Arithmetic

Description

Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*64
    dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
ENDFOR
dst[MAX:128] := 0

Performance

Architecture | Latency | Throughput | μops
Haswell | 5 | 0.5 |
Broadwell | 5 | 0.5 |
Skylake | 4 | 0.5 |
Knights Landing | 6 | 0.5 |


_mm_fmsub_ps

__m128 _mm_fmsub_ps( __m128 a, __m128 b, __m128 c )

Synopsis

#include "immintrin.h"
Instruction: vfmsub132ps
CPUID Flag: FMA
Category: Arithmetic

Description

Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
ENDFOR
dst[MAX:128] := 0

Performance

Architecture | Latency | Throughput | μops
Haswell | 5 | 0.5 |
Broadwell | 5 | 0.5 |
Skylake | 4 | 0.5 |
Knights Landing | 6 | 0.5 |


_mm_fmsub_sd

__m128d _mm_fmsub_sd( __m128d a, __m128d b, __m128d c )

Synopsis

#include "immintrin.h"
Instruction: vfmsub132sd
CPUID Flag: FMA
Category: Arithmetic

Description

Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the intermediate result. Store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".

Operation

dst[63:0] := (a[63:0] * b[63:0]) - c[63:0]
dst[127:64] := a[127:64]
dst[MAX:128] := 0

Performance

Architecture | Latency | Throughput | μops
Haswell | 5 | 0.5 |
Broadwell | 5 | 0.5 |
Skylake | 4 | 0.5 |
Knights Landing | 6 | 0.5 |


_mm_fmsub_ss

__m128 _mm_fmsub_ss( __m128 a, __m128 b, __m128 c )

Synopsis

#include "immintrin.h"
Instruction: vfmsub132ss
CPUID Flag: FMA
Category: Arithmetic

Description

Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the intermediate result. Store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".

Operation

dst[31:0] := (a[31:0] * b[31:0]) - c[31:0]
dst[127:32] := a[127:32]
dst[MAX:128] := 0

Performance

Architecture | Latency | Throughput | μops
Haswell | 5 | 0.5 |
Broadwell | 5 | 0.5 |
Skylake | 4 | 0.5 |
Knights Landing | 6 | 0.5 |


_mm_fmsubadd_pd

__m128d _mm_fmsubadd_pd( __m128d a, __m128d b, __m128d c )

Synopsis

#include "immintrin.h"
Instruction: vfmsubadd132pd
CPUID Flag: FMA
Category: Arithmetic

Description

Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*64
    IF (j % 1 == 0)
        dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
    ELSE
        dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
    FI
ENDFOR
dst[MAX:128] := 0

Performance

Architecture | Latency | Throughput | μops
Haswell | 5 | 0.5 |
Broadwell | 5 | 0.5 |
Skylake | 4 | 0.5 |
Knights Landing | 6 | 0.5 |


_mm_fmsubadd_ps

__m128 _mm_fmsubadd_ps( __m128 a, __m128 b, __m128 c )

Synopsis

#include "immintrin.h"
Instruction: vfmsubadd132ps
CPUID Flag: FMA
Category: Arithmetic

Description

Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    IF (j % 1 == 0)
        dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
    ELSE
        dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
    FI
ENDFOR
dst[MAX:128] := 0

Performance

Architecture | Latency | Throughput | μops
Haswell | 5 | 0.5 |
Broadwell | 5 | 0.5 |
Skylake | 4 | 0.5 |
Knights Landing | 6 | 0.5 |


_mm_fnmadd_pd

__m128d _mm_fnmadd_pd( __m128d a, __m128d b, __m128d c )

Synopsis

#include "immintrin.h"
Instruction: vfnmadd132pd
CPUID Flag: FMA
Category: Arithmetic

Description

Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*64
    dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) + c[i+63:i]
ENDFOR
dst[MAX:128] := 0

Performance

Architecture | Latency | Throughput | μops
Haswell | 5 | 0.5 |
Broadwell | 5 | 0.5 |
Skylake | 4 | 0.5 |
Knights Landing | 6 | 0.5 |


_mm_fnmadd_ps

__m128 _mm_fnmadd_ps( __m128 a, __m128 b, __m128 c )

Synopsis

#include "immintrin.h"
Instruction: vfnmadd132ps
CPUID Flag: FMA
Category: Arithmetic

Description

Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    a[i+31:i] := -(a[i+31:i] * b[i+31:i]) + c[i+31:i]
ENDFOR
dst[MAX:128] := 0

Performance

Architecture | Latency | Throughput | μops
Haswell | 5 | 0.5 |
Broadwell | 5 | 0.5 |
Skylake | 4 | 0.5 |
Knights Landing | 6 | 0.5 |


_mm_fnmadd_sd

__m128d _mm_fnmadd_sd( __m128d a, __m128d b, __m128d c )

Synopsis

#include "immintrin.h"
Instruction: vfnmadd132sd
CPUID Flag: FMA
Category: Arithmetic

Description

Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and add the negated intermediate result to the lower element in "c". Store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".

Operation

dst[63:0] := -(a[63:0] * b[63:0]) + c[63:0]
dst[127:64] := a[127:64]
dst[MAX:128] := 0

Performance

Architecture | Latency | Throughput | μops
Haswell | 5 | 0.5 |
Broadwell | 5 | 0.5 |
Skylake | 4 | 0.5 |
Knights Landing | 6 | 0.5 |


_mm_fnmadd_ss

__m128 _mm_fnmadd_ss( __m128 a, __m128 b, __m128 c )

Synopsis

#include "immintrin.h"
Instruction: vfnmadd132ss
CPUID Flag: FMA
Category: Arithmetic

Description

Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and add the negated intermediate result to the lower element in "c". Store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".

Operation

dst[31:0] := -(a[31:0] * b[31:0]) + c[31:0]
dst[127:32] := a[127:32]
dst[MAX:128] := 0

Performance

Architecture | Latency | Throughput | μops
Haswell | 5 | 0.5 |
Broadwell | 5 | 0.5 |
Skylake | 4 | 0.5 |
Knights Landing | 6 | 0.5 |


_mm_fnmsub_pd

__m128d _mm_fnmsub_pd( __m128d a, __m128d b, __m128d c )

Synopsis

#include "immintrin.h"
Instruction: vfnmsub132pd
CPUID Flag: FMA
Category: Arithmetic

Description

Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*64
    dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) - c[i+63:i]
ENDFOR
dst[MAX:128] := 0

Performance

Architecture | Latency | Throughput | μops
Haswell | 5 | 0.5 |
Broadwell | 5 | 0.5 |
Skylake | 4 | 0.5 |
Knights Landing | 6 | 0.5 |


_mm_fnmsub_ps

__m128 _mm_fnmsub_ps( __m128 a, __m128 b, __m128 c )

Synopsis

#include "immintrin.h"
Instruction: vfnmsub132ps
CPUID Flag: FMA
Category: Arithmetic

Description

Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) - c[i+31:i]
ENDFOR
dst[MAX:128] := 0

Performance

Architecture | Latency | Throughput | μops
Haswell | 5 | 0.5 |
Broadwell | 5 | 0.5 |
Skylake | 4 | 0.5 |
Knights Landing | 6 | 0.5 |


_mm_fnmsub_sd

__m128d _mm_fnmsub_sd( __m128d a, __m128d b, __m128d c )

Synopsis

#include "immintrin.h"
Instruction: vfnmsub132sd
CPUID Flag: FMA
Category: Arithmetic

Description

Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the negated intermediate result. Store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".

Operation

dst[63:0] := -(a[63:0] * b[63:0]) - c[63:0]
dst[127:64] := a[127:64]
dst[MAX:128] := 0

Performance

Architecture | Latency | Throughput | μops
Haswell | 5 | 0.5 |
Broadwell | 5 | 0.5 |
Skylake | 4 | 0.5 |
Knights Landing | 6 | 0.5 |


_mm_fnmsub_ss

__m128 _mm_fnmsub_ss( __m128 a, __m128 b, __m128 c )

Synopsis

#include "immintrin.h"
Instruction: vfnmsub132ss
CPUID Flag: FMA
Category: Arithmetic

Description

Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the negated intermediate result. Store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".

Operation

dst[31:0] := -(a[31:0] * b[31:0]) - c[31:0]
dst[127:32] := a[127:32]
dst[MAX:128] := 0

Performance

Architecture | Latency | Throughput | μops
Haswell | 5 | 0.5 |
Broadwell | 5 | 0.5 |
Skylake | 4 | 0.5 |
Knights Landing | 6 | 0.5 |


_mm_free

void _mm_free( void * mem_addr )

Synopsis

#include "xmmintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: General Support

Description

Free aligned memory that was allocated with "_mm_malloc".


_MM_GET_EXCEPTION_MASK

unsigned int _MM_GET_EXCEPTION_MASK()

Synopsis

#include "xmmintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: General Support

Description

Macro: Get the exception mask bits from the MXCSR control and status register. The exception mask may contain any of the following flags: _MM_MASK_INVALID, _MM_MASK_DIV_ZERO, _MM_MASK_DENORM, _MM_MASK_OVERFLOW, _MM_MASK_UNDERFLOW, _MM_MASK_INEXACT

Operation

dst[31:0] := MXCSR & _MM_MASK_MASK


_MM_GET_EXCEPTION_STATE

unsigned int _MM_GET_EXCEPTION_STATE()

Synopsis

#include "xmmintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: General Support

Description

Macro: Get the exception state bits from the MXCSR control and status register. The exception state may contain any of the following flags: _MM_EXCEPT_INVALID, _MM_EXCEPT_DIV_ZERO, _MM_EXCEPT_DENORM, _MM_EXCEPT_OVERFLOW, _MM_EXCEPT_UNDERFLOW, _MM_EXCEPT_INEXACT

Operation

dst[31:0] := MXCSR & _MM_EXCEPT_MASK


_MM_GET_FLUSH_ZERO_MODE

unsigned int _MM_GET_FLUSH_ZERO_MODE()

Synopsis

#include "xmmintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: General Support

Description

Macro: Get the flush zero bits from the MXCSR control and status register. The flush zero may contain any of the following flags: _MM_FLUSH_ZERO_ON or _MM_FLUSH_ZERO_OFF

Operation

dst[31:0] := MXCSR & _MM_FLUSH_MASK


_MM_GET_ROUNDING_MODE

unsigned int _MM_GET_ROUNDING_MODE()

Synopsis

#include "xmmintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: General Support

Description

Macro: Get the rounding mode bits from the MXCSR control and status register. The rounding mode may contain any of the following flags: _MM_ROUND_NEAREST, _MM_ROUND_DOWN, _MM_ROUND_UP, _MM_ROUND_TOWARD_ZERO

Operation

dst[31:0] := MXCSR & _MM_ROUND_MASK


_mm_getcsr

unsigned int _mm_getcsr( void )

Synopsis

#include "xmmintrin.h"
Instruction: stmxcsr
CPUID Flag: SSE
Category: General Support

Description

Get the unsigned 32-bit value of the MXCSR control and status register.

Operation

dst[31:0] := MXCSR

Performance

Architecture | Latency | Throughput | μops
Ryzen |  | 14 | 2
Jaguar | 13 | 12 | 3
Sandy Bridge |  | 1 | 3
Ivy Bridge | 7 | 1 | 3
Haswell | 7 | 1 | 3
Broadwell | 7 | 1 | 3
Skylake | 5 | 2 | 3
Knights Landing |  | 15 | 5
Ivy Bridge |  | 1 |
Haswell |  | 1 |
Broadwell |  | 1 |
Skylake |  | 1 |


_mm_hadd_epi16

__m128i _mm_hadd_epi16( __m128i a, __m128i b )

Synopsis

#include "tmmintrin.h"
Instruction: phaddw
CPUID Flag: SSSE3
Category: Arithmetic

Description

Horizontally add adjacent pairs of 16-bit integers in "a" and "b", and pack the signed 16-bit results in "dst".

Operation

dst[15:0] := a[31:16] + a[15:0]
dst[31:16] := a[63:48] + a[47:32]
dst[47:32] := a[95:80] + a[79:64]
dst[63:48] := a[127:112] + a[111:96]
dst[79:64] := b[31:16] + b[15:0]
dst[95:80] := b[63:48] + b[47:32]
dst[111:96] := b[95:80] + b[79:64]
dst[127:112] := b[127:112] + b[111:96]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 2 | 2 | 4
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 2 | 1.5 | 3
Ivy Bridge | 3 | 1.5 | 3
Haswell | 3 | 2 | 3
Broadwell | 3 | 2 | 3
Skylake | 3 | 2 | 3
Knights Landing | 28 | 28 | 6
Ivy Bridge | 3 | 1.5 |
Haswell | 3 | 2 |
Broadwell | 3 | 2 |
Skylake | 3 | 2 |


_mm_hadd_epi32

__m128i _mm_hadd_epi32( __m128i a, __m128i b )

Synopsis

#include "tmmintrin.h"
Instruction: phaddd
CPUID Flag: SSSE3
Category: Arithmetic

Description

Horizontally add adjacent pairs of 32-bit integers in "a" and "b", and pack the signed 32-bit results in "dst".

Operation

dst[31:0] := a[63:32] + a[31:0]
dst[63:32] := a[127:96] + a[95:64]
dst[95:64] := b[63:32] + b[31:0]
dst[127:96] := b[127:96] + b[95:64]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 2 | 2 | 4
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 2 | 1.5 | 3
Ivy Bridge | 3 | 1.5 | 3
Haswell | 3 | 2 | 3
Broadwell | 3 | 2 | 3
Skylake | 3 | 2 | 3
Knights Landing | 11 | 9 | 3
Ivy Bridge | 3 | 1.5 |
Haswell | 3 | 2 |
Broadwell | 3 | 2 |
Skylake | 3 | 2 |


_mm_hadd_pd

__m128d _mm_hadd_pd( __m128d a, __m128d b )

Synopsis

#include "pmmintrin.h"
Instruction: haddpd
CPUID Flag: SSE3
Category: Arithmetic

Description

Horizontally add adjacent pairs of double-precision (64-bit) floating-point elements in "a" and "b", and pack the results in "dst".

Operation

dst[63:0] := a[127:64] + a[63:0]
dst[127:64] := b[127:64] + b[63:0]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 7 | 2 | 4
Jaguar | 4 | 1 | 1
Sandy Bridge | 5 | 2 | 3
Ivy Bridge | 5 | 2 | 3
Haswell | 5 | 2 | 3
Broadwell | 5 | 2 | 3
Skylake | 6 | 2 | 3
Knights Landing | 15 | 8 | 3
Ivy Bridge | 5 | 2 |
Haswell | 5 | 2 |
Broadwell | 5 | 2 |
Skylake | 6 | 2 |


_mm_hadd_pi16

__m64 _mm_hadd_pi16( __m64 a, __m64 b )

Synopsis

#include "tmmintrin.h"
Instruction: phaddw
CPUID Flag: SSSE3
Category: Arithmetic

Description

Horizontally add adjacent pairs of 16-bit integers in "a" and "b", and pack the signed 16-bit results in "dst".

Operation

dst[15:0] := a[31:16] + a[15:0]
dst[31:16] := a[63:48] + a[47:32]
dst[47:32] := b[31:16] + b[15:0]
dst[63:48] := b[63:48] + b[47:32]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 2 | 2 | 4
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 2 | 1.5 | 3
Ivy Bridge | 3 | 1.5 | 3
Haswell | 3 | 2 | 3
Broadwell | 3 | 2 | 3
Skylake | 3 | 2 | 3
Knights Landing | 28 | 28 | 6
Ivy Bridge | 3 | 1.5 |
Haswell | 3 | 2 |
Broadwell | 3 | 2 |
Skylake | 3 | 2 |


_mm_hadd_pi32

__m64 _mm_hadd_pi32( __m64 a, __m64 b )

Synopsis

#include "tmmintrin.h"
Instruction: phaddw
CPUID Flag: SSSE3
Category: Arithmetic

Description

Horizontally add adjacent pairs of 32-bit integers in "a" and "b", and pack the signed 32-bit results in "dst".

Operation

dst[31:0] := a[63:32] + a[31:0]
dst[63:32] := b[63:32] + b[31:0]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 2 | 2 | 4
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 2 | 1.5 | 3
Ivy Bridge | 3 | 1.5 | 3
Haswell | 3 | 2 | 3
Broadwell | 3 | 2 | 3
Skylake | 3 | 2 | 3
Knights Landing | 28 | 28 | 6
Ivy Bridge | 3 | 1.5 |
Haswell | 3 | 2 |
Broadwell | 3 | 2 |
Skylake | 3 | 2 |


_mm_hadd_ps

__m128 _mm_hadd_ps( __m128 a, __m128 b )

Synopsis

#include "pmmintrin.h"
Instruction: haddps
CPUID Flag: SSE3
Category: Arithmetic

Description

Horizontally add adjacent pairs of single-precision (32-bit) floating-point elements in "a" and "b", and pack the results in "dst".

Operation

dst[31:0] := a[63:32] + a[31:0]
dst[63:32] := a[127:96] + a[95:64]
dst[95:64] := b[63:32] + b[31:0]
dst[127:96] := b[127:96] + b[95:64]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 7 | 2 | 4
Jaguar | 4 | 1 | 1
Sandy Bridge | 5 | 2 | 3
Ivy Bridge | 5 | 2 | 3
Haswell | 5 | 2 | 3
Broadwell | 5 | 2 | 3
Skylake | 6 | 2 | 3
Knights Landing | 15 | 8 | 3
Ivy Bridge | 5 | 2 |
Haswell | 5 | 2 |
Broadwell | 5 | 2 |
Skylake | 6 | 2 |


_mm_hadds_epi16

__m128i _mm_hadds_epi16( __m128i a, __m128i b )

Synopsis

#include "tmmintrin.h"
Instruction: phaddsw
CPUID Flag: SSSE3
Category: Arithmetic

Description

Horizontally add adjacent pairs of 16-bit integers in "a" and "b" using saturation, and pack the signed 16-bit results in "dst".

Operation

dst[15:0] := Saturate_To_Int16(a[31:16] + a[15:0])
dst[31:16] := Saturate_To_Int16(a[63:48] + a[47:32])
dst[47:32] := Saturate_To_Int16(a[95:80] + a[79:64])
dst[63:48] := Saturate_To_Int16(a[127:112] + a[111:96])
dst[79:64] := Saturate_To_Int16(b[31:16] + b[15:0])
dst[95:80] := Saturate_To_Int16(b[63:48] + b[47:32])
dst[111:96] := Saturate_To_Int16(b[95:80] + b[79:64])
dst[127:112] := Saturate_To_Int16(b[127:112] + b[111:96])

Performance

Architecture | Latency | Throughput | μops
Ryzen | 2 | 2 | 4
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 2 | 1.5 | 3
Ivy Bridge | 3 | 1.5 | 3
Haswell | 3 | 2 | 3
Broadwell | 3 | 2 | 3
Skylake | 3 | 2 | 3
Knights Landing | 28 | 28 | 6
Ivy Bridge | 3 | 1.5 |
Haswell | 3 | 2 |
Broadwell | 3 | 2 |
Skylake | 3 | 2 |


_mm_hadds_pi16

__m64 _mm_hadds_pi16( __m64 a, __m64 b )

Synopsis

#include "tmmintrin.h"
Instruction: phaddsw
CPUID Flag: SSSE3
Category: Arithmetic

Description

Horizontally add adjacent pairs of 16-bit integers in "a" and "b" using saturation, and pack the signed 16-bit results in "dst".

Operation

dst[15:0] := Saturate_To_Int16(a[31:16] + a[15:0])
dst[31:16] := Saturate_To_Int16(a[63:48] + a[47:32])
dst[47:32] := Saturate_To_Int16(b[31:16] + b[15:0])
dst[63:48] := Saturate_To_Int16(b[63:48] + b[47:32])

Performance

Architecture | Latency | Throughput | μops
Ryzen | 2 | 2 | 4
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 2 | 1.5 | 3
Ivy Bridge | 3 | 1.5 | 3
Haswell | 3 | 2 | 3
Broadwell | 3 | 2 | 3
Skylake | 3 | 2 | 3
Knights Landing | 28 | 28 | 6
Ivy Bridge | 3 | 1.5 |
Haswell | 3 | 2 |
Broadwell | 3 | 2 |
Skylake | 3 | 2 |


_mm_hsub_epi16

__m128i _mm_hsub_epi16( __m128i a, __m128i b )

Synopsis

#include "tmmintrin.h"
Instruction: phsubw
CPUID Flag: SSSE3
Category: Arithmetic

Description

Horizontally subtract adjacent pairs of 16-bit integers in "a" and "b", and pack the signed 16-bit results in "dst".

Operation

dst[15:0] := a[15:0] - a[31:16]
dst[31:16] := a[47:32] - a[63:48]
dst[47:32] := a[79:64] - a[95:80]
dst[63:48] := a[111:96] - a[127:112]
dst[79:64] := b[15:0] - b[31:16]
dst[95:80] := b[47:32] - b[63:48]
dst[111:96] := b[79:64] - b[95:80]
dst[127:112] := b[111:96] - b[127:112]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 2 | 2 | 4
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 2 | 1.5 | 3
Ivy Bridge | 3 | 1.5 | 3
Haswell | 3 | 2 | 3
Broadwell | 3 | 2 | 3
Skylake | 3 | 2 | 3
Knights Landing | 28 | 28 | 6
Ivy Bridge | 3 | 1.5 |
Haswell | 3 | 2 |
Broadwell | 3 | 2 |
Skylake | 3 | 2 |


_mm_hsub_epi32

__m128i _mm_hsub_epi32( __m128i a, __m128i b )

Synopsis

#include "tmmintrin.h"
Instruction: phsubd
CPUID Flag: SSSE3
Category: Arithmetic

Description

Horizontally subtract adjacent pairs of 32-bit integers in "a" and "b", and pack the signed 32-bit results in "dst".

Operation

dst[31:0] := a[31:0] - a[63:32]
dst[63:32] := a[95:64] - a[127:96]
dst[95:64] := b[31:0] - b[63:32]
dst[127:96] := b[95:64] - b[127:96]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 2 | 2 | 4
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 2 | 1.5 | 3
Ivy Bridge | 3 | 1.5 | 3
Haswell | 3 | 2 | 3
Broadwell | 3 | 2 | 3
Skylake | 3 | 2 | 3
Knights Landing | 11 | 9 | 3
Ivy Bridge | 3 | 1.5 |
Haswell | 3 | 2 |
Broadwell | 3 | 2 |
Skylake | 3 | 2 |


_mm_hsub_pd

__m128d _mm_hsub_pd( __m128d a, __m128d b )

Synopsis

#include "pmmintrin.h"
Instruction: hsubpd
CPUID Flag: SSE3
Category: Arithmetic

Description

Horizontally subtract adjacent pairs of double-precision (64-bit) floating-point elements in "a" and "b", and pack the results in "dst".

Operation

dst[63:0] := a[63:0] - a[127:64]
dst[127:64] := b[63:0] - b[127:64]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 7 | 2 | 4
Jaguar | 4 | 1 | 1
Sandy Bridge | 5 | 2 | 3
Ivy Bridge | 5 | 2 | 3
Haswell | 5 | 2 | 3
Broadwell | 5 | 2 | 3
Skylake | 6 | 2 | 3
Knights Landing | 15 | 8 | 3
Ivy Bridge | 5 | 2 |
Haswell | 5 | 2 |
Broadwell | 5 | 2 |
Skylake | 6 | 2 |


_mm_hsub_pi16

__m64 _mm_hsub_pi16( __m64 a, __m64 b )

Synopsis

#include "tmmintrin.h"
Instruction: phsubw
CPUID Flag: SSSE3
Category: Arithmetic

Description

Horizontally subtract adjacent pairs of 16-bit integers in "a" and "b", and pack the signed 16-bit results in "dst".

Operation

dst[15:0] := a[15:0] - a[31:16]
dst[31:16] := a[47:32] - a[63:48]
dst[47:32] := b[15:0] - b[31:16]
dst[63:48] := b[47:32] - b[63:48]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 2 | 2 | 4
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 2 | 1.5 | 3
Ivy Bridge | 3 | 1.5 | 3
Haswell | 3 | 2 | 3
Broadwell | 3 | 2 | 3
Skylake | 3 | 2 | 3
Knights Landing | 28 | 28 | 6
Ivy Bridge | 3 | 1.5 |
Haswell | 3 | 2 |
Broadwell | 3 | 2 |
Skylake | 3 | 2 |


_mm_hsub_pi32

__m64 _mm_hsub_pi32( __m64 a, __m64 b )

Synopsis

#include "tmmintrin.h"
Instruction: phsubd
CPUID Flag: SSSE3
Category: Arithmetic

Description

Horizontally subtract adjacent pairs of 32-bit integers in "a" and "b", and pack the signed 32-bit results in "dst".

Operation

dst[31:0] := a[31:0] - a[63:32]
dst[63:32] := b[31:0] - b[63:32]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 2 | 2 | 4
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 2 | 1.5 | 3
Ivy Bridge | 3 | 1.5 | 3
Haswell | 3 | 2 | 3
Broadwell | 3 | 2 | 3
Skylake | 3 | 2 | 3
Knights Landing | 11 | 9 | 3
Ivy Bridge | 3 | 1.5 |
Haswell | 3 | 2 |
Broadwell | 3 | 2 |
Skylake | 3 | 2 |


_mm_hsub_ps

__m128 _mm_hsub_ps( __m128 a, __m128 b )

Synopsis

#include "pmmintrin.h"
Instruction: hsubps
CPUID Flag: SSE3
Category: Arithmetic

Description

Horizontally add adjacent pairs of single-precision (32-bit) floating-point elements in "a" and "b", and pack the results in "dst".

Operation

dst[31:0] := a[31:0] - a[63:32]
dst[63:32] := a[95:64] - a[127:96]
dst[95:64] := b[31:0] - b[63:32]
dst[127:96] := b[95:64] - b[127:96]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 7 | 2 | 4
Jaguar | 4 | 1 | 1
Sandy Bridge | 5 | 2 | 3
Ivy Bridge | 5 | 2 | 3
Haswell | 5 | 2 | 3
Broadwell | 5 | 2 | 3
Skylake | 6 | 2 | 3
Knights Landing | 15 | 8 | 3
Ivy Bridge | 5 | 2 |
Haswell | 5 | 2 |
Broadwell | 5 | 2 |
Skylake | 6 | 2 |


_mm_hsubs_epi16

__m128i _mm_hsubs_epi16( __m128i a, __m128i b )

Synopsis

#include "tmmintrin.h"
Instruction: phsubsw
CPUID Flag: SSSE3
Category: Arithmetic

Description

Horizontally subtract adjacent pairs of 16-bit integers in "a" and "b" using saturation, and pack the signed 16-bit results in "dst".

Operation

dst[15:0] := Saturate_To_Int16(a[15:0] - a[31:16])
dst[31:16] := Saturate_To_Int16(a[47:32] - a[63:48])
dst[47:32] := Saturate_To_Int16(a[79:64] - a[95:80])
dst[63:48] := Saturate_To_Int16(a[111:96] - a[127:112])
dst[79:64] := Saturate_To_Int16(b[15:0] - b[31:16])
dst[95:80] := Saturate_To_Int16(b[47:32] - b[63:48])
dst[111:96] := Saturate_To_Int16(b[79:64] - b[95:80])
dst[127:112] := Saturate_To_Int16(b[111:96] - b[127:112])

Performance

Architecture | Latency | Throughput | μops
Ryzen | 2 | 2 | 4
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 2 | 1.5 | 3
Ivy Bridge | 3 | 1.5 | 3
Haswell | 3 | 2 | 3
Broadwell | 3 | 2 | 3
Skylake | 3 | 2 | 3
Knights Landing | 28 | 28 | 6
Ivy Bridge | 3 | 1.5 |
Haswell | 3 | 2 |
Broadwell | 3 | 2 |
Skylake | 3 | 2 |


_mm_hsubs_pi16

__m64 _mm_hsubs_pi16( __m64 a, __m64 b )

Synopsis

#include "tmmintrin.h"
Instruction: phsubsw
CPUID Flag: SSSE3
Category: Arithmetic

Description

Horizontally subtract adjacent pairs of 16-bit integers in "a" and "b" using saturation, and pack the signed 16-bit results in "dst".

Operation

dst[15:0] := Saturate_To_Int16(a[15:0] - a[31:16])
dst[31:16] := Saturate_To_Int16(a[47:32] - a[63:48])
dst[47:32] := Saturate_To_Int16(b[15:0] - b[31:16])
dst[63:48] := Saturate_To_Int16(b[47:32] - b[63:48])

Performance

Architecture | Latency | Throughput | μops
Ryzen | 2 | 2 | 4
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 2 | 1.5 | 3
Ivy Bridge | 3 | 1.5 | 3
Haswell | 3 | 2 | 3
Broadwell | 3 | 2 | 3
Skylake | 3 | 2 | 3
Knights Landing | 28 | 28 | 6
Ivy Bridge | 3 | 1.5 |
Haswell | 3 | 2 |
Broadwell | 3 | 2 |
Skylake | 3 | 2 |


_mm_hypot_pd

__m128d _mm_hypot_pd( __m128d a, __m128d b )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Trigonometry

Description

Compute the length of the hypotenous of a right triangle, with the lengths of the other two sides of the triangle stored as packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*64
    dst[i+63:i] := SQRT(a[i+63:i]^2 + b[i+63:i]^2)
ENDFOR
dst[MAX:128] := 0


_mm_hypot_ps

__m128 _mm_hypot_ps( __m128 a, __m128 b )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Trigonometry

Description

Compute the length of the hypotenous of a right triangle, with the lengths of the other two sides of the triangle stored as packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := SQRT(a[i+31:i]^2 + b[i+31:i]^2)
ENDFOR
dst[MAX:128] := 0


_mm_i32gather_epi32

__m128i _mm_i32gather_epi32( int const* base_addr, __m128i vindex, const int scale )

Synopsis

#include "immintrin.h"
Instruction: vpgatherdd
CPUID Flag: AVX2
Category: Load

Description

Gather 32-bit integers from memory using 32-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.

Operation

FOR j := 0 to 3
    i := j*32
    m := j*32
    dst[i+31:i] := MEM[base_addr + SignExtend(vindex[i+31:i])*scale]
ENDFOR
dst[MAX:128] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen |  | 13 | 38
Haswell |  | 9 | 20
Broadwell |  | 6 | 10
Skylake |  | 4 | 4
Knights Landing |  | 12 | 6
Haswell | ~14 | ~7 |
Broadwell | ~17 | ~5 |
Skylake | ~20 | ~4 |


_mm_i32gather_epi64

__m128i _mm_i32gather_epi64( __int64 const* base_addr, __m128i vindex, const int scale )

Synopsis

#include "immintrin.h"
Instruction: vpgatherdq
CPUID Flag: AVX2
Category: Load

Description

Gather 64-bit integers from memory using 32-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.

Operation

FOR j := 0 to 1
    i := j*64
    m := j*32
    dst[i+63:i] := MEM[base_addr + SignExtend(vindex[m+31:m])*scale]
ENDFOR
dst[MAX:128] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen |  | 9 | 23
Haswell |  | 7 | 12
Broadwell |  | 5 | 7
Skylake |  | 2 | 5
Knights Landing |  | 12 | 6


_mm_i32gather_pd

__m128d _mm_i32gather_pd( double const* base_addr, __m128i vindex, const int scale )

Synopsis

#include "immintrin.h"
Instruction: vgatherdpd
CPUID Flag: AVX2
Category: Load

Description

Gather double-precision (64-bit) floating-point elements from memory using 32-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.

Operation

FOR j := 0 to 1
    i := j*64
    m := j*32
    dst[i+63:i] := MEM[base_addr + SignExtend(vindex[m+31:m])*scale]
ENDFOR
dst[MAX:128] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen |  | 9 | 23
Haswell |  | 7 | 12
Broadwell |  | 5 | 7
Skylake |  | 2 | 5


_mm_i32gather_ps

__m128 _mm_i32gather_ps( float const* base_addr, __m128i vindex, const int scale )

Synopsis

#include "immintrin.h"
Instruction: vgatherdps
CPUID Flag: AVX2
Category: Load

Description

Gather single-precision (32-bit) floating-point elements from memory using 32-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.

Operation

FOR j := 0 to 3
    i := j*32
    m := j*32
    dst[i+31:i] := MEM[base_addr + SignExtend(vindex[i+31:i])*scale]
ENDFOR
dst[MAX:128] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen |  | 13 | 38
Haswell |  | 9 | 20
Broadwell |  | 6 | 10
Skylake | 13 | 5 | 4


_mm_i64gather_epi32

__m128i _mm_i64gather_epi32( int const* base_addr, __m128i vindex, const int scale )

Synopsis

#include "immintrin.h"
Instruction: vpgatherqd
CPUID Flag: AVX2
Category: Load

Description

Gather 32-bit integers from memory using 64-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.

Operation

FOR j := 0 to 1
    i := j*32
    m := j*64
    dst[i+31:i] := MEM[base_addr + SignExtend(vindex[m+63:m])*scale]
ENDFOR
dst[MAX:64] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen |  | 9 | 24
Haswell |  | 8 | 15
Broadwell |  | 6 | 9
Skylake |  | 2 | 5
Knights Landing |  | 12 | 6


_mm_i64gather_epi64

__m128i _mm_i64gather_epi64( __int64 const* base_addr, __m128i vindex, const int scale )

Synopsis

#include "immintrin.h"
Instruction: vpgatherqq
CPUID Flag: AVX2
Category: Load

Description

Gather 64-bit integers from memory using 64-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.

Operation

FOR j := 0 to 1
    i := j*64
    m := j*64
    dst[i+63:i] := MEM[base_addr + SignExtend(vindex[m+63:m])*scale]
ENDFOR
dst[MAX:128] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen |  | 9 | 23
Haswell |  | 7 | 14
Broadwell |  | 5 | 7
Skylake |  | 2 | 5
Knights Landing |  | 12 | 6
Haswell | ~12 | ~5 |
Broadwell | ~15 | ~4 |
Skylake | ~18 | ~3 |


_mm_i64gather_pd

__m128d _mm_i64gather_pd( double const* base_addr, __m128i vindex, const int scale )

Synopsis

#include "immintrin.h"
Instruction: vgatherqpd
CPUID Flag: AVX2
Category: Load

Description

Gather double-precision (64-bit) floating-point elements from memory using 64-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.

Operation

FOR j := 0 to 1
    i := j*64
    m := j*64
    dst[i+63:i] := MEM[base_addr + SignExtend(vindex[m+63:m])*scale]
ENDFOR
dst[MAX:128] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen |  | 9 | 23
Haswell |  | 7 | 14
Broadwell |  | 5 | 7
Skylake |  | 2 | 5


_mm_i64gather_ps

__m128 _mm_i64gather_ps( float const* base_addr, __m128i vindex, const int scale )

Synopsis

#include "immintrin.h"
Instruction: vgatherqps
CPUID Flag: AVX2
Category: Load

Description

Gather single-precision (32-bit) floating-point elements from memory using 64-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.

Operation

FOR j := 0 to 1
    i := j*32
    m := j*64
    dst[i+31:i] := MEM[base_addr + SignExtend(vindex[m+63:m])*scale]
ENDFOR
dst[MAX:64] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen |  | 9 | 24
Haswell |  | 8 | 15
Broadwell |  | 6 | 9
Skylake |  | 2 | 5


_mm_idiv_epi32

__m128i _mm_idiv_epi32( __m128i a, __m128i b )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Arithmetic

Description

Divide packed 32-bit integers in "a" by packed elements in "b", and store the truncated results in "dst".

Operation

FOR j := 0 to 3
    i := 32*j
    dst[i+31:i] := TRUNCATE(a[i+31:i] / b[i+31:i])
ENDFOR
dst[MAX:128] := 0


_mm_idivrem_epi32

__m128i _mm_idivrem_epi32( __m128i * mem_addr, __m128i a, __m128i b )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Arithmetic

Description

Divide packed 32-bit integers in "a" by packed elements in "b", store the truncated results in "dst", and store the remainders as packed 32-bit integers into memory at "mem_addr".

Operation

FOR j := 0 to 3
    i := 32*j
    dst[i+31:i] := TRUNCATE(a[i+31:i] / b[i+31:i])
    MEM[mem_addr+i+31:mem_addr+i] := REMAINDER(a[i+31:i] / b[i+31:i])
ENDFOR
dst[MAX:128] := 0


_mm_insert_epi16

__m128i _mm_insert_epi16( __m128i a, int i, int imm8 )

Synopsis

#include "emmintrin.h"
Instruction: pinsrw
CPUID Flag: SSE2
Category: Swizzle

Description

Copy "a" to "dst", and insert the 16-bit integer "i" into "dst" at the location specified by "imm8".

Operation

dst[127:0] := a[127:0]
sel := imm8[2:0]*16
dst[sel+15:sel] := i[15:0]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 1 | 2
Jaguar | 7 | 1 | 2
Sandy Bridge | 2 | 1 | 2
Ivy Bridge | 2 | 1 | 2
Haswell | 2 | 2 | 2
Broadwell | 2 | 2 | 2
Skylake | 3 | 2 | 2
Knights Landing | 5 | 1 | 1
Ivy Bridge | 2 | 1 |
Haswell | 2 | 2 |
Broadwell | 2 | 2 |
Skylake | 2 | 2 |


_mm_insert_epi32

__m128i _mm_insert_epi32( __m128i a, int i, const int imm8 )

Synopsis

#include "smmintrin.h"
Instruction: pinsrd
CPUID Flag: SSE4.1
Category: Swizzle

Description

Copy "a" to "dst", and insert the 32-bit integer "i" into "dst" at the location specified by "imm8".

Operation

dst[127:0] := a[127:0]
sel := imm8[1:0]*32
dst[sel+31:sel] := i[31:0]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 1 | 2
Jaguar | 7 | 1 | 2
Sandy Bridge | 2 | 1 | 2
Ivy Bridge | 2 | 1 | 2
Haswell | 2 | 2 | 2
Broadwell | 2 | 2 | 2
Skylake | 3 | 2 | 2
Knights Landing | 4 | 1.5 | 1
Ivy Bridge | 2 | 1 |
Haswell | 2 | 1 |
Broadwell | 2 | 1 |
Skylake | 2 | 1 |


_mm_insert_epi64

__m128i _mm_insert_epi64( __m128i a, __int64 i, const int imm8 )

Synopsis

#include "smmintrin.h"
Instruction: pinsrq
CPUID Flag: SSE4.1
Category: Swizzle

Description

Copy "a" to "dst", and insert the 64-bit integer "i" into "dst" at the location specified by "imm8".

Operation

dst[127:0] := a[127:0]
sel := imm8[0]*64
dst[sel+63:sel] := i[63:0]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 1 | 2
Jaguar | 7 | 1 | 2
Sandy Bridge | 2 | 1 | 2
Ivy Bridge | 2 | 1 | 2
Haswell | 2 | 2 | 2
Broadwell | 2 | 2 | 2
Skylake | 3 | 2 | 2
Knights Landing | 4 | 6 | 1


_mm_insert_epi8

__m128i _mm_insert_epi8( __m128i a, int i, const int imm8 )

Synopsis

#include "smmintrin.h"
Instruction: pinsrb
CPUID Flag: SSE4.1
Category: Swizzle

Description

Copy "a" to "dst", and insert the lower 8-bit integer from "i" into "dst" at the location specified by "imm8".

Operation

dst[127:0] := a[127:0]
sel := imm8[3:0]*8
dst[sel+7:sel] := i[7:0]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 1 | 2
Jaguar | 7 | 1 | 2
Sandy Bridge | 2 | 1 | 2
Ivy Bridge | 2 | 1 | 2
Haswell | 2 | 2 | 2
Broadwell | 2 | 2 | 2
Skylake | 3 | 2 | 2
Knights Landing | 5 | 1 | 1
Ivy Bridge | 2 | 1 |
Haswell | 2 | 1 |
Broadwell | 2 | 1 |
Skylake | 2 | 1 |


_mm_insert_pi16

__m64 _mm_insert_pi16( __m64 a, int i, int imm8 )

Synopsis

#include "xmmintrin.h"
Instruction: pinsrw
CPUID Flag: SSE
Category: Swizzle

Description

Copy "a" to "dst", and insert the 16-bit integer "i" into "dst" at the location specified by "imm8".

Operation

dst[63:0] := a[63:0]
sel := imm8[1:0]*16
dst[sel+15:sel] := i[15:0]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 1 | 2
Jaguar | 7 | 1 | 2
Sandy Bridge | 2 | 1 | 2
Ivy Bridge | 2 | 1 | 2
Haswell | 2 | 2 | 2
Broadwell | 2 | 2 | 2
Skylake | 3 | 2 | 2
Knights Landing | 5 | 1 | 1


_mm_insert_ps

__m128 _mm_insert_ps( __m128 a, __m128 b, const int imm8 )

Synopsis

#include "smmintrin.h"
Instruction: insertps
CPUID Flag: SSE4.1
Category: Swizzle

Description

Copy "a" to "tmp", then insert a single-precision (32-bit) floating-point element from "b" into "tmp" using the control in "imm8". Store "tmp" to "dst" using the mask in "imm8" (elements are zeroed out when the corresponding bit is set).

Operation

tmp2[127:0] := a[127:0]
CASE (imm8[7:6]) OF
0: tmp1[31:0] := b[31:0]
1: tmp1[31:0] := b[63:32]
2: tmp1[31:0] := b[95:64]
3: tmp1[31:0] := b[127:96]
ESAC
CASE (imm8[5:4]) OF
0: tmp2[31:0] := tmp1[31:0]
1: tmp2[63:32] := tmp1[31:0]
2: tmp2[95:64] := tmp1[31:0]
3: tmp2[127:96] := tmp1[31:0]
ESAC
FOR j := 0 to 3
    i := j*32
    IF imm8[j%8]
        dst[i+31:i] := 0
    ELSE
        dst[i+31:i] := tmp2[i+31:i]
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar |  | 1 | 1
Sandy Bridge | 1 | 1 | 1
Ivy Bridge | 1 | 1 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 8 | 7 | 2
Ivy Bridge | 1 | 1 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm_invcbrt_pd

__m128d _mm_invcbrt_pd( __m128d a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Elementary Math Functions

Description

Compute the inverse cube root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*64
    dst[i+63:i] := InvCubeRoot(a[i+63:i])
ENDFOR
dst[MAX:128] := 0


_mm_invcbrt_ps

__m128 _mm_invcbrt_ps( __m128 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Elementary Math Functions

Description

Compute the inverse cube root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := InvCubeRoot(a[i+31:i])
ENDFOR
dst[MAX:128] := 0


_mm_invsqrt_pd

__m128d _mm_invsqrt_pd( __m128d a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Elementary Math Functions

Description

Compute the inverse square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*64
    dst[i+63:i] := InvSQRT(a[i+63:i])
ENDFOR
dst[MAX:128] := 0


_mm_invsqrt_ps

__m128 _mm_invsqrt_ps( __m128 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Elementary Math Functions

Description

Compute the inverse square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := InvSQRT(a[i+31:i])
ENDFOR
dst[MAX:128] := 0


_mm_irem_epi32

__m128i _mm_irem_epi32( __m128i a, __m128i b )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Arithmetic

Description

Divide packed 32-bit integers in "a" by packed elements in "b", and store the remainders as packed 32-bit integers in "dst".

Operation

FOR j := 0 to 3
    i := 32*j
    dst[i+31:i] := REMAINDER(a[i+31:i] / b[i+31:i])
ENDFOR
dst[MAX:128] := 0


_mm_lddqu_si128

__m128i _mm_lddqu_si128( __m128i const* mem_addr )

Synopsis

#include "pmmintrin.h"
Instruction: lddqu
CPUID Flag: SSE3
Category: Load

Description

Load 128-bits of integer data from unaligned memory into "dst". This intrinsic may perform better than "_mm_loadu_si128" when the data crosses a cache line boundary.

Operation

dst[127:0] := MEM[mem_addr+127:mem_addr]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 0.5 | 1
Jaguar | 4 | 1 | 1
Sandy Bridge | 3 | 0.5 | 1
Ivy Bridge | 3 | 0.5 | 1
Haswell | 3 | 0.5 | 1
Broadwell | 3 | 0.5 | 1
Skylake | 3 | 0.5 | 1
Knights Landing | 5 | 0.5 | 1


_mm_lfence

void _mm_lfence( void )

Synopsis

#include "emmintrin.h"
Instruction: lfence
CPUID Flag: SSE2
Category: General Support

Description

Perform a serializing operation on all load-from-memory instructions that were issued prior to this instruction. Guarantees that every load instruction that precedes, in program order, is globally visible before any load instruction which follows the fence in program order.

Performance

Architecture | Latency | Throughput | μops
Ivy Bridge |  | 4 |
Haswell |  | 5 |
Broadwell |  | 5 |
Skylake |  | 6 |


_mm_load_pd

__m128d _mm_load_pd( double const* mem_addr )

Synopsis

#include "emmintrin.h"
Instruction: movapd
CPUID Flag: SSE2
Category: Load

Description

Load 128-bits (composed of 2 packed double-precision (64-bit) floating-point elements) from memory into "dst". "mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.

Operation

dst[127:0] := MEM[mem_addr+127:mem_addr]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 0 | 0.25 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 1 | 1
Ivy Bridge | 0-1 | ≤1 | 1
Haswell | 0-1 | 1 | 1
Broadwell | 0-1 | 1 | 1
Skylake | 0-1 | 0.25 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 1 | 1 |
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.33 |


_mm_load_pd1

__m128d _mm_load_pd1( double const* mem_addr )

Synopsis

#include "emmintrin.h"
Instruction: movapd
CPUID Flag: SSE2
Category: Load

Description

Load a double-precision (64-bit) floating-point element from memory into both elements of "dst".

Operation

dst[63:0] := MEM[mem_addr+63:mem_addr]
dst[127:64] := MEM[mem_addr+63:mem_addr]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 0 | 0.25 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 1 | 1
Ivy Bridge | 0-1 | ≤1 | 1
Haswell | 0-1 | 1 | 1
Broadwell | 0-1 | 1 | 1
Skylake | 0-1 | 0.25 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 1 | 1 |
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.33 |


_mm_load_ps

__m128 _mm_load_ps( float const* mem_addr )

Synopsis

#include "xmmintrin.h"
Instruction: movaps
CPUID Flag: SSE
Category: Load

Description

Load 128-bits (composed of 4 packed single-precision (32-bit) floating-point elements) from memory into "dst". "mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.

Operation

dst[127:0] := MEM[mem_addr+127:mem_addr]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 0 | 0.25 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 1 | 1
Ivy Bridge | 0-1 | ≤1 | 1
Haswell | 0-1 | 1 | 1
Broadwell | 0-1 | 1 | 1
Skylake | 0-1 | 0.25 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 1 | 1 |
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.25 |


_mm_load_ps1

__m128 _mm_load_ps1( float const* mem_addr )

Synopsis

#include "xmmintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Load

Description

Load a single-precision (32-bit) floating-point element from memory into all elements of "dst".

Operation

dst[31:0] := MEM[mem_addr+31:mem_addr]
dst[63:32] := MEM[mem_addr+31:mem_addr]
dst[95:64] := MEM[mem_addr+31:mem_addr]
dst[127:96] := MEM[mem_addr+31:mem_addr]


_mm_load_sd

__m128d _mm_load_sd( double const* mem_addr )

Synopsis

#include "emmintrin.h"
Instruction: movsd
CPUID Flag: SSE2
Category: Load

Description

Load a double-precision (64-bit) floating-point element from memory into the lower of "dst", and zero the upper element. "mem_addr" does not need to be aligned on any particular boundary.

Operation

dst[63:0] := MEM[mem_addr+63:mem_addr]
dst[127:64] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.25 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 1 | 1
Ivy Bridge | 1 | 1 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 1 | 1 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm_load_si128

__m128i _mm_load_si128( __m128i const* mem_addr )

Synopsis

#include "emmintrin.h"
Instruction: movdqa
CPUID Flag: SSE2
Category: Load

Description

Load 128-bits of integer data from memory into "dst". "mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.

Operation

dst[127:0] := MEM[mem_addr+127:mem_addr]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 0 | 0.25 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 |  | 1
Ivy Bridge | 0-1 | 0.25 | 1
Haswell | 0-1 | 0.33 | 1
Broadwell | 0-1 | 0.25 | 1
Skylake | 0-1 | 0.25 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 0.33 |
Broadwell | 1 | 0.33 |
Skylake | 1 | 0.25 |


_mm_load_ss

__m128 _mm_load_ss( float const* mem_addr )

Synopsis

#include "xmmintrin.h"
Instruction: movss
CPUID Flag: SSE
Category: Load

Description

Load a single-precision (32-bit) floating-point element from memory into the lower of "dst", and zero the upper 3 elements. "mem_addr" does not need to be aligned on any particular boundary.

Operation

dst[31:0] := MEM[mem_addr+31:mem_addr]
dst[127:32] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.25 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 1 | 1
Ivy Bridge | 1 | 1 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 1 | 1 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm_load1_pd

__m128d _mm_load1_pd( double const* mem_addr )

Synopsis

#include "emmintrin.h"
Instruction: movapd
CPUID Flag: SSE2
Category: Load

Description

Load a double-precision (64-bit) floating-point element from memory into both elements of "dst".

Operation

dst[63:0] := MEM[mem_addr+63:mem_addr]
dst[127:64] := MEM[mem_addr+63:mem_addr]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 0 | 0.25 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 1 | 1
Ivy Bridge | 0-1 | ≤1 | 1
Haswell | 0-1 | 1 | 1
Broadwell | 0-1 | 1 | 1
Skylake | 0-1 | 0.25 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 1 | 1 |
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.33 |


_mm_load1_ps

__m128 _mm_load1_ps( float const* mem_addr )

Synopsis

#include "xmmintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Load

Description

Load a single-precision (32-bit) floating-point element from memory into all elements of "dst".

Operation

dst[31:0] := MEM[mem_addr+31:mem_addr]
dst[63:32] := MEM[mem_addr+31:mem_addr]
dst[95:64] := MEM[mem_addr+31:mem_addr]
dst[127:96] := MEM[mem_addr+31:mem_addr]


_mm_loaddup_pd

__m128d _mm_loaddup_pd( double const* mem_addr )

Synopsis

#include "pmmintrin.h"
Instruction: movddup
CPUID Flag: SSE3
Category: Load

Description

Load a double-precision (64-bit) floating-point element from memory into both elements of "dst".

Operation

tmp[63:0] := MEM[mem_addr+63:mem_addr]
tmp[127:64] := MEM[mem_addr+63:mem_addr]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 1 | 1 | 1
Ivy Bridge | 1 | 1 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 3-6 | 1 | 1
Ivy Bridge | 1 | 1 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm_loadh_pd

__m128d _mm_loadh_pd( __m128d a, double const* mem_addr )

Synopsis

#include "emmintrin.h"
Instruction: movhpd
CPUID Flag: SSE2
Category: Load

Description

Load a double-precision (64-bit) floating-point element from memory into the upper element of "dst", and copy the lower element from "a" to "dst". "mem_addr" does not need to be aligned on any particular boundary.

Operation

dst[63:0] := a[63:0]
dst[127:64] := MEM[mem_addr+63:mem_addr]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 4 | 0.5 | 1
Jaguar | 5 | 1 | 1
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 4 | 1 | 2
Haswell | 4 | 1 | 1
Broadwell | 4 | 1 | 1
Skylake | 4 | 1 | 1
Knights Landing | 6 | 1.5 | 1


_mm_loadh_pi

__m128 _mm_loadh_pi( __m128 a, __m64 const* mem_addr )

Synopsis

#include "xmmintrin.h"
Instruction: movhps
CPUID Flag: SSE
Category: Load

Description

Load 2 single-precision (32-bit) floating-point elements from memory into the upper 2 elements of "dst", and copy the lower 2 elements from "a" to "dst". "mem_addr" does not need to be aligned on any particular boundary.

Operation

dst[31:0] := a[31:0]
dst[63:32] := a[63:32]
dst[95:64] := MEM[mem_addr+31:mem_addr]
dst[127:96] := MEM[mem_addr+63:mem_addr+32]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 4 | 0.5 | 1
Jaguar | 5 | 1 | 1
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 4 | 1 | 2
Haswell | 4 | 1 | 1
Broadwell | 4 | 1 | 1
Skylake | 4 | 1 | 1
Knights Landing | 6 | 1.5 | 1


_mm_loadl_epi64

__m128i _mm_loadl_epi64( __m128i const* mem_addr )

Synopsis

#include "emmintrin.h"
Instruction: movq
CPUID Flag: SSE2
Category: Load

Description

Load 64-bit integer from memory into the first element of "dst".

Operation

dst[63:0] := MEM[mem_addr+63:mem_addr]
dst[MAX:64] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.25 | 1
Jaguar | 4 | 1 | 1
Sandy Bridge | 1 |  | 1
Ivy Bridge | 1 | 0.33 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 2 | 1 | 1
Knights Landing | 4 | 1 | 1
Ivy Bridge | 1 | 0.33 |
Haswell | 1 | 0.33 |
Broadwell | 1 | 0.33 |
Skylake | 1 | 0.33 |


_mm_loadl_pd

__m128d _mm_loadl_pd( __m128d a, double const* mem_addr )

Synopsis

#include "emmintrin.h"
Instruction: movlpd
CPUID Flag: SSE2
Category: Load

Description

Load a double-precision (64-bit) floating-point element from memory into the lower element of "dst", and copy the upper element from "a" to "dst". "mem_addr" does not need to be aligned on any particular boundary.

Operation

dst[63:0] := MEM[mem_addr+63:mem_addr]
dst[127:64] := a[127:64]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 4 | 0.5 | 1
Jaguar | 5 | 1 | 1
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 4 | 1 | 2
Haswell | 4 | 1 | 1
Broadwell | 4 | 1 | 1
Skylake | 4 | 1 | 1
Knights Landing | 6 | 1.5 | 1


_mm_loadl_pi

__m128 _mm_loadl_pi( __m128 a, __m64 const* mem_addr )

Synopsis

#include "xmmintrin.h"
Instruction: movlps
CPUID Flag: SSE
Category: Load

Description

Load 2 single-precision (32-bit) floating-point elements from memory into the lower 2 elements of "dst", and copy the upper 2 elements from "a" to "dst". "mem_addr" does not need to be aligned on any particular boundary.

Operation

dst[31:0] := MEM[mem_addr+31:mem_addr]
dst[63:32] := MEM[mem_addr+63:mem_addr+32]
dst[95:64] := a[95:64]
dst[127:96] := a[127:96]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 4 | 0.5 | 1
Jaguar | 5 | 1 | 1
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 4 | 1 | 2
Haswell | 4 | 1 | 1
Broadwell | 4 | 1 | 1
Skylake | 4 | 1 | 1
Knights Landing | 6 | 1.5 | 1


_mm_loadr_pd

__m128d _mm_loadr_pd( double const* mem_addr )

Synopsis

#include "emmintrin.h"
Instruction: movapd
CPUID Flag: SSE2
Category: Load

Description

Load 2 double-precision (64-bit) floating-point elements from memory into "dst" in reverse order. mem_addr must be aligned on a 16-byte boundary or a general-protection exception may be generated.

Operation

dst[63:0] := MEM[mem_addr+127:mem_addr+64]
dst[127:64] := MEM[mem_addr+63:mem_addr]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 0 | 0.25 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 1 | 1
Ivy Bridge | 0-1 | ≤1 | 1
Haswell | 0-1 | 1 | 1
Broadwell | 0-1 | 1 | 1
Skylake | 0-1 | 0.25 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 1 | 1 |
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.33 |


_mm_loadr_ps

__m128 _mm_loadr_ps( float const* mem_addr )

Synopsis

#include "xmmintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Load

Description

Load 4 single-precision (32-bit) floating-point elements from memory into "dst" in reverse order. mem_addr must be aligned on a 16-byte boundary or a general-protection exception may be generated.

Operation

dst[31:0] := MEM[mem_addr+127:mem_addr+96]
dst[63:32] := MEM[mem_addr+95:mem_addr+64]
dst[95:64] := MEM[mem_addr+63:mem_addr+32]
dst[127:96] := MEM[mem_addr+31:mem_addr]


_mm_loadu_pd

__m128d _mm_loadu_pd( double const* mem_addr )

Synopsis

#include "emmintrin.h"
Instruction: movupd
CPUID Flag: SSE2
Category: Load

Description

Load 128-bits (composed of 2 packed double-precision (64-bit) floating-point elements) from memory into "dst". "mem_addr" does not need to be aligned on any particular boundary.

Operation

dst[127:0] := MEM[mem_addr+127:mem_addr]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 0 | 0.25 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 3 | 0.5 | 1
Ivy Bridge | 3 | 0.5 | 1
Haswell | 3 | 0.5 | 1
Broadwell | 3 | 0.5 | 1
Skylake | 2 | 0.5 | 1
Knights Landing | 5 | 0.5 | 1
Ivy Bridge | 1 | 1 |
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.33 |


_mm_loadu_ps

__m128 _mm_loadu_ps( float const* mem_addr )

Synopsis

#include "xmmintrin.h"
Instruction: movups
CPUID Flag: SSE
Category: Load

Description

Load 128-bits (composed of 4 packed single-precision (32-bit) floating-point elements) from memory into "dst". "mem_addr" does not need to be aligned on any particular boundary.

Operation

dst[127:0] := MEM[mem_addr+127:mem_addr]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 0 | 0.25 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 3 | 0.5 | 1
Ivy Bridge | 3 | 0.5 | 1
Haswell | 3 | 0.5 | 1
Broadwell | 3 | 0.5 | 1
Skylake | 2 | 0.5 | 1
Knights Landing | 5 | 0.5 | 1
Ivy Bridge | 1 | 1 |
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.25 |


_mm_loadu_si128

__m128i _mm_loadu_si128( __m128i const* mem_addr )

Synopsis

#include "emmintrin.h"
Instruction: movdqu
CPUID Flag: SSE2
Category: Load

Description

Load 128-bits of integer data from memory into "dst". "mem_addr" does not need to be aligned on any particular boundary.

Operation

dst[127:0] := MEM[mem_addr+127:mem_addr]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 0 | 0.25 | 1
Jaguar | 4 | 1 | 1
Sandy Bridge | 3 | 0.5 | 1
Ivy Bridge | 0-1 | 0.25 | 1
Haswell | 0-1 | 0.33 | 1
Broadwell | 0-1 | 0.25 | 1
Skylake | 0-1 | 0.25 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 0.33 |
Broadwell | 1 | 0.33 |
Skylake | 1 | 0.25 |


_mm_loadu_si16

__m128i _mm_loadu_si16( void const* mem_addr )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Load

Description

Load unaligned 16-bit integer from memory into the first element of "dst".

Operation

dst[15:0] := MEM[mem_addr+15:mem_addr]
dst[MAX:16] := 0


_mm_loadu_si32

__m128i _mm_loadu_si32( void const* mem_addr )

Synopsis

#include "immintrin.h"
Instruction: movd
CPUID Flag: SSE2
Category: Load

Description

Load unaligned 32-bit integer from memory into the first element of "dst".

Operation

dst[31:0] := MEM[mem_addr+31:mem_addr]
dst[MAX:32] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 1 | 1
Jaguar | 4 | 1 | 1
Sandy Bridge | 1 |  | 1
Ivy Bridge | 1 | 1 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 2 | 1 | 1
Knights Landing | 4 | 1 | 1


_mm_loadu_si64

__m128i _mm_loadu_si64( void const* mem_addr )

Synopsis

#include "immintrin.h"
Instruction: movq
CPUID Flag: SSE
Category: Load

Description

Load unaligned 64-bit integer from memory into the first element of "dst".

Operation

dst[63:0] := MEM[mem_addr+63:mem_addr]
dst[MAX:64] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.25 | 1
Jaguar | 4 | 1 | 1
Sandy Bridge | 1 |  | 1
Ivy Bridge | 1 | 0.33 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 2 | 1 | 1
Knights Landing | 4 | 1 | 1


_mm_log_pd

__m128d _mm_log_pd( __m128d a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Elementary Math Functions

Description

Compute the natural logarithm of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*64
    dst[i+63:i] := ln(a[i+63:i])
ENDFOR
dst[MAX:128] := 0


_mm_log_ps

__m128 _mm_log_ps( __m128 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Elementary Math Functions

Description

Compute the natural logarithm of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := ln(a[i+31:i])
ENDFOR
dst[MAX:128] := 0


_mm_log10_pd

__m128d _mm_log10_pd( __m128d a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Elementary Math Functions

Description

Compute the base-10 logarithm of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*64
    dst[i+63:i] := log10(a[i+63:i])
ENDFOR
dst[MAX:128] := 0


_mm_log10_ps

__m128 _mm_log10_ps( __m128 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Elementary Math Functions

Description

Compute the base-10 logarithm of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := log10(a[i+31:i])
ENDFOR
dst[MAX:128] := 0


_mm_log1p_pd

__m128d _mm_log1p_pd( __m128d a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Elementary Math Functions

Description

Compute the natural logarithm of one plus packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*64
    dst[i+63:i] := ln(1.0 + a[i+63:i])
ENDFOR
dst[MAX:128] := 0


_mm_log1p_ps

__m128 _mm_log1p_ps( __m128 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Elementary Math Functions

Description

Compute the natural logarithm of one plus packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := ln(1.0 + a[i+31:i])
ENDFOR
dst[MAX:128] := 0


_mm_log2_pd

__m128d _mm_log2_pd( __m128d a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Elementary Math Functions

Description

Compute the base-2 logarithm of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*64
    dst[i+63:i] := log2(a[i+63:i])
ENDFOR
dst[MAX:128] := 0


_mm_log2_ps

__m128 _mm_log2_ps( __m128 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Elementary Math Functions

Description

Compute the base-2 logarithm of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := log2(a[i+31:i])
ENDFOR
dst[MAX:128] := 0


_mm_logb_pd

__m128d _mm_logb_pd( __m128d a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Elementary Math Functions

Description

Convert the exponent of each packed double-precision (64-bit) floating-point element in "a" to a double-precision floating-point number representing the integer exponent, and store the results in "dst". This intrinsic essentially calculates "floor(log2(x))" for each element.

Operation

FOR j := 0 to 1
    i := j*64
    dst[i+63:i] := ConvertExpFP64(a[i+63:i])
ENDFOR
dst[MAX:128] := 0


_mm_logb_ps

__m128 _mm_logb_ps( __m128 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Elementary Math Functions

Description

Convert the exponent of each packed single-precision (32-bit) floating-point element in "a" to a single-precision floating-point number representing the integer exponent, and store the results in "dst". This intrinsic essentially calculates "floor(log2(x))" for each element.

Operation

FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := ConvertExpFP32(a[i+31:i])
ENDFOR
dst[MAX:128] := 0


_mm_madd_epi16

__m128i _mm_madd_epi16( __m128i a, __m128i b )

Synopsis

#include "emmintrin.h"
Instruction: pmaddwd
CPUID Flag: SSE2
Category: Arithmetic

Description

Multiply packed signed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers. Horizontally add adjacent pairs of intermediate 32-bit integers, and pack the results in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := a[i+31:i+16]*b[i+31:i+16] + a[i+15:i]*b[i+15:i]
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 1 | 1
Jaguar | 2 | 1 | 1
Sandy Bridge | 5 | 1 | 1
Ivy Bridge | 5 | 1 | 1
Haswell | 5 | 1 | 1
Broadwell | 5 | 1 | 1
Skylake | 5 | 0.5 | 1
Knights Landing | 7 | 2 | 1
Ivy Bridge | 5 | 1 |
Haswell | 5 | 1 |
Broadwell | 5 | 1 |
Skylake | 5 | 0.5 |


_mm_madd_pi16

__m64 _mm_madd_pi16( __m64 a, __m64 b )

Synopsis

#include "mmintrin.h"
Instruction: pmaddwd
CPUID Flag: MMX
Category: Arithmetic

Description

Multiply packed 16-bit integers in "a" and "b", producing intermediate 32-bit integers. Horizontally add adjacent pairs of intermediate 32-bit integers, and pack the results in "dst".

Operation

FOR j := 0 to 1
    i := j*32
    dst[i+31:i] := a[i+31:i+16]*b[i+31:i+16] + a[i+15:i]*b[i+15:i]
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 1 | 1
Jaguar | 2 | 1 | 1
Sandy Bridge | 5 | 1 | 1
Ivy Bridge | 5 | 1 | 1
Haswell | 5 | 1 | 1
Broadwell | 5 | 1 | 1
Skylake | 5 | 0.5 | 1
Knights Landing | 7 | 2 | 1


_mm_maddubs_epi16

__m128i _mm_maddubs_epi16( __m128i a, __m128i b )

Synopsis

#include "tmmintrin.h"
Instruction: pmaddubsw
CPUID Flag: SSSE3
Category: Arithmetic

Description

Vertically multiply each unsigned 8-bit integer from "a" with the corresponding signed 8-bit integer from "b", producing intermediate signed 16-bit integers. Horizontally add adjacent pairs of intermediate signed 16-bit integers, and pack the saturated results in "dst".

Operation

FOR j := 0 to 7
    i := j*16
    dst[i+15:i] := Saturate_To_Int16( a[i+15:i+8]*b[i+15:i+8] + a[i+7:i]*b[i+7:i] )
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 4 | 1 | 1
Jaguar | 2 | 1 | 1
Sandy Bridge | 5 | 1 | 1
Ivy Bridge | 5 | 1 | 1
Haswell | 5 | 1 | 1
Broadwell | 5 | 1 | 1
Skylake | 5 | 0.5 | 1
Knights Landing | 16 | 9 | 5
Ivy Bridge | 5 | 1 |
Haswell | 5 | 1 |
Broadwell | 5 | 1 |
Skylake | 5 | 0.5 |


_mm_maddubs_pi16

__m64 _mm_maddubs_pi16( __m64 a, __m64 b )

Synopsis

#include "tmmintrin.h"
Instruction: pmaddubsw
CPUID Flag: SSSE3
Category: Arithmetic

Description

Vertically multiply each unsigned 8-bit integer from "a" with the corresponding signed 8-bit integer from "b", producing intermediate signed 16-bit integers. Horizontally add adjacent pairs of intermediate signed 16-bit integers, and pack the saturated results in "dst".

Operation

FOR j := 0 to 3
    i := j*16
    dst[i+15:i] := Saturate_To_Int16( a[i+15:i+8]*b[i+15:i+8] + a[i+7:i]*b[i+7:i] )
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 4 | 1 | 1
Jaguar | 2 | 1 | 1
Sandy Bridge | 5 | 1 | 1
Ivy Bridge | 5 | 1 | 1
Haswell | 5 | 1 | 1
Broadwell | 5 | 1 | 1
Skylake | 5 | 0.5 | 1
Knights Landing | 16 | 9 | 5
Ivy Bridge | 5 | 1 |
Haswell | 5 | 1 |
Broadwell | 5 | 1 |
Skylake | 5 | 0.5 |


_mm_malloc

void* _mm_malloc( size_t size, size_t align )

Synopsis

#include "xmmintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: General Support

Description

Allocate "size" bytes of memory, aligned to the alignment specified in "align", and return a pointer to the allocated memory. "_mm_free" should be used to free memory that is allocated with "_mm_malloc".


_mm_mask_i32gather_epi32

__m128i _mm_mask_i32gather_epi32( __m128i src, int const* base_addr, __m128i vindex, __m128i mask, const int scale )

Synopsis

#include "immintrin.h"
Instruction: vpgatherdd
CPUID Flag: AVX2
Category: Load

Description

Gather 32-bit integers from memory using 32-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8.

Operation

FOR j := 0 to 3
    i := j*32
    IF mask[i+31]
        dst[i+31:i] := MEM[base_addr + SignExtend(vindex[i+31:i])*scale]
        mask[i+31] := 0
    ELSE
        dst[i+31:i] := src[i+31:i]
    FI
ENDFOR
mask[MAX:128] := 0
dst[MAX:128] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen |  | 13 | 38
Haswell |  | 9 | 20
Broadwell |  | 6 | 10
Skylake |  | 4 | 4
Knights Landing |  | 12 | 6
Haswell | ~14 | ~7 |
Broadwell | ~17 | ~5 |
Skylake | ~20 | ~4 |


_mm_mask_i32gather_epi64

__m128i _mm_mask_i32gather_epi64( __m128i src, __int64 const* base_addr, __m128i vindex, __m128i mask, const int scale )

Synopsis

#include "immintrin.h"
Instruction: vpgatherdq
CPUID Flag: AVX2
Category: Load

Description

Gather 64-bit integers from memory using 32-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8.

Operation

FOR j := 0 to 1
    i := j*64
    m := j*32
    IF mask[i+63]
        dst[i+63:i] := MEM[base_addr + SignExtend(vindex[m+31:m])*scale]
        mask[i+63] := 0
    ELSE
        dst[i+63:i] := src[i+63:i]
    FI
ENDFOR
mask[MAX:128] := 0
dst[MAX:128] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen |  | 9 | 23
Haswell |  | 7 | 12
Broadwell |  | 5 | 7
Skylake |  | 2 | 5
Knights Landing |  | 12 | 6


_mm_mask_i32gather_pd

__m128d _mm_mask_i32gather_pd( __m128d src, double const* base_addr, __m128i vindex, __m128d mask, const int scale )

Synopsis

#include "immintrin.h"
Instruction: vgatherdpd
CPUID Flag: AVX2
Category: Load

Description

Gather double-precision (64-bit) floating-point elements from memory using 32-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8.

Operation

FOR j := 0 to 1
    i := j*64
    m := j*32
    IF mask[i+63]
        dst[i+63:i] := MEM[base_addr + SignExtend(vindex[m+31:m])*scale]
        mask[i+63] := 0
    ELSE
        dst[i+63:i] := src[i+63:i]
    FI
ENDFOR
mask[MAX:128] := 0
dst[MAX:128] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen |  | 9 | 23
Haswell |  | 7 | 12
Broadwell |  | 5 | 7
Skylake |  | 2 | 5


_mm_mask_i32gather_ps

__m128 _mm_mask_i32gather_ps( __m128 src, float const* base_addr, __m128i vindex, __m128 mask, const int scale )

Synopsis

#include "immintrin.h"
Instruction: vgatherdps
CPUID Flag: AVX2
Category: Load

Description

Gather single-precision (32-bit) floating-point elements from memory using 32-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8.

Operation

FOR j := 0 to 3
    i := j*32
    IF mask[i+31]
        dst[i+31:i] := MEM[base_addr + SignExtend(vindex[i+31:i])*scale]
        mask[i+31] := 0
    ELSE
        dst[i+31:i] := src[i+31:i]
    FI
ENDFOR
mask[MAX:128] := 0
dst[MAX:128] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen |  | 13 | 38
Haswell |  | 9 | 20
Broadwell |  | 6 | 10
Skylake | 13 | 5 | 4


_mm_mask_i64gather_epi32

__m128i _mm_mask_i64gather_epi32( __m128i src, int const* base_addr, __m128i vindex, __m128i mask, const int scale )

Synopsis

#include "immintrin.h"
Instruction: vpgatherqd
CPUID Flag: AVX2
Category: Load

Description

Gather 32-bit integers from memory using 64-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8.

Operation

FOR j := 0 to 1
    i := j*32
    m := j*64
    IF mask[i+31]
        dst[i+31:i] := MEM[base_addr + SignExtend(vindex[m+63:m])*scale]
        mask[i+31] := 0
    ELSE
        dst[i+31:i] := src[i+31:i]
    FI
ENDFOR
mask[MAX:64] := 0
dst[MAX:64] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen |  | 9 | 24
Haswell |  | 8 | 15
Broadwell |  | 6 | 9
Skylake |  | 2 | 5
Knights Landing |  | 12 | 6


_mm_mask_i64gather_epi64

__m128i _mm_mask_i64gather_epi64( __m128i src, __int64 const* base_addr, __m128i vindex, __m128i mask, const int scale )

Synopsis

#include "immintrin.h"
Instruction: vpgatherqq
CPUID Flag: AVX2
Category: Load

Description

Gather 64-bit integers from memory using 64-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8.

Operation

FOR j := 0 to 1
    i := j*64
    m := j*64
    IF mask[i+63]
        dst[i+63:i] := MEM[base_addr + SignExtend(vindex[m+63:m])*scale]
        mask[i+63] := 0
    ELSE
        dst[i+63:i] := src[i+63:i]
    FI
ENDFOR
mask[MAX:128] := 0
dst[MAX:128] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen |  | 9 | 23
Haswell |  | 7 | 14
Broadwell |  | 5 | 7
Skylake |  | 2 | 5
Knights Landing |  | 12 | 6
Haswell | ~12 | ~5 |
Broadwell | ~15 | ~4 |
Skylake | ~18 | ~3 |


_mm_mask_i64gather_pd

__m128d _mm_mask_i64gather_pd( __m128d src, double const* base_addr, __m128i vindex, __m128d mask, const int scale )

Synopsis

#include "immintrin.h"
Instruction: vgatherqpd
CPUID Flag: AVX2
Category: Load

Description

Gather double-precision (64-bit) floating-point elements from memory using 64-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8.

Operation

FOR j := 0 to 1
    i := j*64
    m := j*64
    IF mask[i+63]
        dst[i+63:i] := MEM[base_addr + SignExtend(vindex[m+63:m])*scale]
        mask[i+63] := 0
    ELSE
        dst[i+63:i] := src[i+63:i]
    FI
ENDFOR
mask[MAX:128] := 0
dst[MAX:128] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen |  | 9 | 23
Haswell |  | 7 | 14
Broadwell |  | 5 | 7
Skylake |  | 2 | 5


_mm_mask_i64gather_ps

__m128 _mm_mask_i64gather_ps( __m128 src, float const* base_addr, __m128i vindex, __m128 mask, const int scale )

Synopsis

#include "immintrin.h"
Instruction: vgatherqps
CPUID Flag: AVX2
Category: Load

Description

Gather single-precision (32-bit) floating-point elements from memory using 64-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8.

Operation

FOR j := 0 to 1
    i := j*32
    m := j*64
    IF mask[i+31]
        dst[i+31:i] := MEM[base_addr + SignExtend(vindex[m+63:m])*scale]
        mask[i+31] := 0
    ELSE
        dst[i+31:i] := src[i+31:i]
    FI
ENDFOR
mask[MAX:64] := 0
dst[MAX:64] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen |  | 9 | 24
Haswell |  | 8 | 15
Broadwell |  | 6 | 9
Skylake |  | 2 | 5


_mm_maskload_epi32

__m128i _mm_maskload_epi32( int const* mem_addr, __m128i mask )

Synopsis

#include "immintrin.h"
Instruction: vpmaskmovd
CPUID Flag: AVX2
Category: Load

Description

Load packed 32-bit integers from memory into "dst" using "mask" (elements are zeroed out when the highest bit is not set in the corresponding element).

Operation

FOR j := 0 to 3
    i := j*32
    IF mask[i+31]
        dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i]
    ELSE
        dst[i+31:i] := 0
    FI
ENDFOR
dst[MAX:128] := 0

Performance

Architecture | Latency | Throughput | μops
Haswell | 13-14 | 1 | 4
Broadwell | 15 | 1 | 4
Skylake | 14 | 1 | 3
Knights Landing | 7 | 9 | 5


_mm_maskload_epi64

__m128i _mm_maskload_epi64( __int64 const* mem_addr, __m128i mask )

Synopsis

#include "immintrin.h"
Instruction: vpmaskmovq
CPUID Flag: AVX2
Category: Load

Description

Load packed 64-bit integers from memory into "dst" using "mask" (elements are zeroed out when the highest bit is not set in the corresponding element).

Operation

FOR j := 0 to 1
    i := j*64
    IF mask[i+63]
        dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i]
    ELSE
        dst[i+63:i] := 0
    FI
ENDFOR
dst[MAX:128] := 0

Performance

Architecture | Latency | Throughput | μops
Haswell | 13-14 | 1 | 4
Broadwell | 15 | 1 | 4
Skylake | 14 | 1 | 3
Knights Landing | 7 | 9 | 5


_mm_maskload_pd

__m128d _mm_maskload_pd( double const * mem_addr, __m128i mask )

Synopsis

#include "immintrin.h"
Instruction: vmaskmovpd
CPUID Flag: AVX
Category: Load

Description

Load packed double-precision (64-bit) floating-point elements from memory into "dst" using "mask" (elements are zeroed out when the high bit of the corresponding element is not set).

Operation

FOR j := 0 to 1
    i := j*64
    IF mask[i+63]
        dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i]
    ELSE
        dst[i+63:i] := 0
    FI
ENDFOR
dst[MAX:128] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | ~50 | 5 | 19
Jaguar | 32 | 22 | 36
Sandy Bridge |  | 1 | 3
Ivy Bridge | 5 | 1 | 3
Haswell | 14 | 2 | 4
Broadwell | 16 | 1 | 4
Skylake | 13 | 1 | 4


_mm_maskload_ps

__m128 _mm_maskload_ps( float const * mem_addr, __m128i mask )

Synopsis

#include "immintrin.h"
Instruction: vmaskmovps
CPUID Flag: AVX
Category: Load

Description

Load packed single-precision (32-bit) floating-point elements from memory into "dst" using "mask" (elements are zeroed out when the high bit of the corresponding element is not set).

Operation

FOR j := 0 to 3
    i := j*32
    IF mask[i+31]
        dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i]
    ELSE
        dst[i+31:i] := 0
    FI
ENDFOR
dst[MAX:128] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | ~50 | 5 | 19
Jaguar | 32 | 22 | 36
Sandy Bridge |  | 1 | 3
Ivy Bridge | 5 | 1 | 3
Haswell | 14 | 2 | 4
Broadwell | 16 | 1 | 4
Skylake | 13 | 1 | 4


_mm_maskmove_si64

void _mm_maskmove_si64( __m64 a, __m64 mask, char* mem_addr )

Synopsis

#include "xmmintrin.h"
Instruction: maskmovq
CPUID Flag: SSE
Category: Store

Description

Conditionally store 8-bit integer elements from "a" into memory using "mask" (elements are not stored when the highest bit is not set in the corresponding element) and a non-temporal memory hint.

Operation

FOR j := 0 to 7
    i := j*8
    IF mask[i+7]
        MEM[mem_addr+i+7:mem_addr+i] := a[i+7:i]
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | ~3000 | ~9 | 30
Jaguar | 432 | 17 | 32
Sandy Bridge |  | 1 | 4
Ivy Bridge |  | 1 | 4
Haswell | 13-413 | 1 | 4
Broadwell | 18-500 | 1 | 4
Skylake | ~450 | 2 | 4
Knights Landing | ~550 | 12 | 6


_mm_maskmoveu_si128

void _mm_maskmoveu_si128( __m128i a, __m128i mask, char* mem_addr )

Synopsis

#include "emmintrin.h"
Instruction: maskmovdqu
CPUID Flag: SSE2
Category: Store

Description

Conditionally store 8-bit integer elements from "a" into memory using "mask" (elements are not stored when the highest bit is not set in the corresponding element) and a non-temporal memory hint. "mem_addr" does not need to be aligned on any particular boundary.

Operation

FOR j := 0 to 15
    i := j*8
    IF mask[i+7]
        MEM[mem_addr+i+7:mem_addr+i] := a[i+7:i]
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | ~3000 | ~18 | 60
Jaguar | 43-2210 | 34 | 64
Sandy Bridge |  | 6 | 10
Ivy Bridge |  | 6 | 10
Haswell | 14-438 | 6 | 10
Broadwell | 18-500 | 6 | 10
Skylake | 18-500 | 6 | 10
Knights Landing | ~550 | 12 | 6
Ivy Bridge |  | 6 |
Haswell |  | 6 |
Broadwell |  | 6 |
Skylake |  | 7 |


_mm_maskstore_epi32

void _mm_maskstore_epi32( int* mem_addr, __m128i mask, __m128i a )

Synopsis

#include "immintrin.h"
Instruction: vpmaskmovd
CPUID Flag: AVX2
Category: Store

Description

Store packed 32-bit integers from "a" into memory using "mask" (elements are not stored when the highest bit is not set in the corresponding element).

Operation

FOR j := 0 to 3
    i := j*32
    IF mask[i+31]
        MEM[mem_addr+i+31:mem_addr+i] := a[i+31:i]
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Haswell | 13-14 | 1 | 4
Broadwell | 15 | 1 | 4
Skylake | 14 | 1 | 3
Knights Landing | 7 | 9 | 5


_mm_maskstore_epi64

void _mm_maskstore_epi64( __int64* mem_addr, __m128i mask, __m128i a )

Synopsis

#include "immintrin.h"
Instruction: vpmaskmovq
CPUID Flag: AVX2
Category: Store

Description

Store packed 64-bit integers from "a" into memory using "mask" (elements are not stored when the highest bit is not set in the corresponding element).

Operation

FOR j := 0 to 1
    i := j*64
    IF mask[i+63]
        MEM[mem_addr+i+63:mem_addr+i] := a[i+63:i]
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Haswell | 13-14 | 1 | 4
Broadwell | 15 | 1 | 4
Skylake | 14 | 1 | 3
Knights Landing | 7 | 9 | 5


_mm_maskstore_pd

void _mm_maskstore_pd( double * mem_addr, __m128i mask, __m128d a )

Synopsis

#include "immintrin.h"
Instruction: vmaskmovpd
CPUID Flag: AVX
Category: Store

Description

Store packed double-precision (64-bit) floating-point elements from "a" into memory using "mask".

Operation

FOR j := 0 to 1
    i := j*64
    IF mask[i+63]
        MEM[mem_addr+i+63:mem_addr+i] := a[i+63:i]
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | ~50 | 5 | 19
Jaguar | 32 | 22 | 36
Sandy Bridge |  | 1 | 3
Ivy Bridge | 5 | 1 | 3
Haswell | 14 | 2 | 4
Broadwell | 16 | 1 | 4
Skylake | 13 | 1 | 4


_mm_maskstore_ps

void _mm_maskstore_ps( float * mem_addr, __m128i mask, __m128 a )

Synopsis

#include "immintrin.h"
Instruction: vmaskmovps
CPUID Flag: AVX
Category: Store

Description

Store packed single-precision (32-bit) floating-point elements from "a" into memory using "mask".

Operation

FOR j := 0 to 3
    i := j*32
    IF mask[i+31]
        MEM[mem_addr+i+31:mem_addr+i] := a[i+31:i]
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | ~50 | 5 | 19
Jaguar | 32 | 22 | 36
Sandy Bridge |  | 1 | 3
Ivy Bridge | 5 | 1 | 3
Haswell | 14 | 2 | 4
Broadwell | 16 | 1 | 4
Skylake | 13 | 1 | 4


_mm_max_epi16

__m128i _mm_max_epi16( __m128i a, __m128i b )

Synopsis

#include "emmintrin.h"
Instruction: pmaxsw
CPUID Flag: SSE2
Category: Special Math Functions

Description

Compare packed 16-bit integers in "a" and "b", and store packed maximum values in "dst".

Operation

FOR j := 0 to 7
    i := j*16
    IF a[i+15:i] > b[i+15:i]
        dst[i+15:i] := a[i+15:i]
    ELSE
        dst[i+15:i] := b[i+15:i]
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.5 | 1
Knights Landing | 2 | 2 | 1


_mm_max_epi32

__m128i _mm_max_epi32( __m128i a, __m128i b )

Synopsis

#include "smmintrin.h"
Instruction: pmaxsd
CPUID Flag: SSE4.1
Category: Special Math Functions

Description

Compare packed 32-bit integers in "a" and "b", and store packed maximum values in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    IF a[i+31:i] > b[i+31:i]
        dst[i+31:i] := a[i+31:i]
    ELSE
        dst[i+31:i] := b[i+31:i]
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.5 |


_mm_max_epi8

__m128i _mm_max_epi8( __m128i a, __m128i b )

Synopsis

#include "smmintrin.h"
Instruction: pmaxsb
CPUID Flag: SSE4.1
Category: Special Math Functions

Description

Compare packed 8-bit integers in "a" and "b", and store packed maximum values in "dst".

Operation

FOR j := 0 to 15
    i := j*8
    IF a[i+7:i] > b[i+7:i]
        dst[i+7:i] := a[i+7:i]
    ELSE
        dst[i+7:i] := b[i+7:i]
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.5 |


_mm_max_epu16

__m128i _mm_max_epu16( __m128i a, __m128i b )

Synopsis

#include "smmintrin.h"
Instruction: pmaxuw
CPUID Flag: SSE4.1
Category: Special Math Functions

Description

Compare packed unsigned 16-bit integers in "a" and "b", and store packed maximum values in "dst".

Operation

FOR j := 0 to 7
    i := j*16
    IF a[i+15:i] > b[i+15:i]
        dst[i+15:i] := a[i+15:i]
    ELSE
        dst[i+15:i] := b[i+15:i]
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.5 |


_mm_max_epu32

__m128i _mm_max_epu32( __m128i a, __m128i b )

Synopsis

#include "smmintrin.h"
Instruction: pmaxud
CPUID Flag: SSE4.1
Category: Special Math Functions

Description

Compare packed unsigned 32-bit integers in "a" and "b", and store packed maximum values in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    IF a[i+31:i] > b[i+31:i]
        dst[i+31:i] := a[i+31:i]
    ELSE
        dst[i+31:i] := b[i+31:i]
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.5 |


_mm_max_epu8

__m128i _mm_max_epu8( __m128i a, __m128i b )

Synopsis

#include "emmintrin.h"
Instruction: pmaxub
CPUID Flag: SSE2
Category: Special Math Functions

Description

Compare packed unsigned 8-bit integers in "a" and "b", and store packed maximum values in "dst".

Operation

FOR j := 0 to 15
    i := j*8
    IF a[i+7:i] > b[i+7:i]
        dst[i+7:i] := a[i+7:i]
    ELSE
        dst[i+7:i] := b[i+7:i]
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.5 | 1
Knights Landing | 2 | 2 | 1


_mm_max_pd

__m128d _mm_max_pd( __m128d a, __m128d b )

Synopsis

#include "emmintrin.h"
Instruction: maxpd
CPUID Flag: SSE2
Category: Special Math Functions

Description

Compare packed double-precision (64-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst".

Operation

FOR j := 0 to 1
    i := j*64
    dst[i+63:i] := MAX(a[i+63:i], b[i+63:i])
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 1 | 1
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 4 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 4 | 0.5 |


_mm_max_pi16

__m64 _mm_max_pi16( __m64 a, __m64 b )

Synopsis

#include "xmmintrin.h"
Instruction: pmaxsw
CPUID Flag: SSE
Category: Special Math Functions

Description

Compare packed 16-bit integers in "a" and "b", and store packed maximum values in "dst".

Operation

FOR j := 0 to 3
    i := j*16
    IF a[i+15:i] > b[i+15:i]
        dst[i+15:i] := a[i+15:i]
    ELSE
        dst[i+15:i] := b[i+15:i]
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.5 | 1
Knights Landing | 2 | 2 | 1


_mm_max_ps

__m128 _mm_max_ps( __m128 a, __m128 b )

Synopsis

#include "xmmintrin.h"
Instruction: maxps
CPUID Flag: SSE
Category: Special Math Functions

Description

Compare packed single-precision (32-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := MAX(a[i+31:i], b[i+31:i])
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 1 | 1
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 4 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 4 | 0.5 |


_mm_max_pu8

__m64 _mm_max_pu8( __m64 a, __m64 b )

Synopsis

#include "xmmintrin.h"
Instruction: pmaxub
CPUID Flag: SSE
Category: Special Math Functions

Description

Compare packed unsigned 8-bit integers in "a" and "b", and store packed maximum values in "dst".

Operation

FOR j := 0 to 7
    i := j*8
    IF a[i+7:i] > b[i+7:i]
        dst[i+7:i] := a[i+7:i]
    ELSE
        dst[i+7:i] := b[i+7:i]
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.5 | 1
Knights Landing | 2 | 2 | 1


_mm_max_sd

__m128d _mm_max_sd( __m128d a, __m128d b )

Synopsis

#include "emmintrin.h"
Instruction: maxsd
CPUID Flag: SSE2
Category: Special Math Functions

Description

Compare the lower double-precision (64-bit) floating-point elements in "a" and "b", store the maximum value in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".

Operation

dst[63:0] := MAX(a[63:0], b[63:0])
dst[127:64] := a[127:64]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 1 | 1
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 4 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 4 | 0.5 |


_mm_max_ss

__m128 _mm_max_ss( __m128 a, __m128 b )

Synopsis

#include "xmmintrin.h"
Instruction: maxss
CPUID Flag: SSE
Category: Special Math Functions

Description

Compare the lower single-precision (32-bit) floating-point elements in "a" and "b", store the maximum value in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".

Operation

dst[31:0] := MAX(a[31:0], b[31:0])
dst[127:32] := a[127:32]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 1 | 1
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 4 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 4 | 0.5 |


_mm_mfence

void _mm_mfence( void )

Synopsis

#include "emmintrin.h"
Instruction: mfence
CPUID Flag: SSE2
Category: General Support

Description

Perform a serializing operation on all load-from-memory and store-to-memory instructions that were issued prior to this instruction. Guarantees that every memory access that precedes, in program order, the memory fence instruction is globally visible before any memory instruction which follows the fence in program order.

Performance

Architecture | Latency | Throughput | μops
Ivy Bridge |  | ~35 |
Haswell |  | ~35 |
Broadwell |  | ~35 |
Skylake |  | ~40 |


_mm_min_epi16

__m128i _mm_min_epi16( __m128i a, __m128i b )

Synopsis

#include "emmintrin.h"
Instruction: pminsw
CPUID Flag: SSE2
Category: Special Math Functions

Description

Compare packed 16-bit integers in "a" and "b", and store packed minimum values in "dst".

Operation

FOR j := 0 to 7
    i := j*16
    IF a[i+15:i] < b[i+15:i]
        dst[i+15:i] := a[i+15:i]
    ELSE
        dst[i+15:i] := b[i+15:i]
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.5 | 1
Knights Landing | 2 | 2 | 1


_mm_min_epi32

__m128i _mm_min_epi32( __m128i a, __m128i b )

Synopsis

#include "smmintrin.h"
Instruction: pminsd
CPUID Flag: SSE4.1
Category: Special Math Functions

Description

Compare packed 32-bit integers in "a" and "b", and store packed minimum values in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    IF a[i+31:i] < b[i+31:i]
        dst[i+31:i] := a[i+31:i]
    ELSE
        dst[i+31:i] := b[i+31:i]
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.5 |


_mm_min_epi8

__m128i _mm_min_epi8( __m128i a, __m128i b )

Synopsis

#include "smmintrin.h"
Instruction: pminsb
CPUID Flag: SSE4.1
Category: Special Math Functions

Description

Compare packed 8-bit integers in "a" and "b", and store packed minimum values in "dst".

Operation

FOR j := 0 to 15
    i := j*8
    IF a[i+7:i] < b[i+7:i]
        dst[i+7:i] := a[i+7:i]
    ELSE
        dst[i+7:i] := b[i+7:i]
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.5 |


_mm_min_epu16

__m128i _mm_min_epu16( __m128i a, __m128i b )

Synopsis

#include "smmintrin.h"
Instruction: pminuw
CPUID Flag: SSE4.1
Category: Special Math Functions

Description

Compare packed unsigned 16-bit integers in "a" and "b", and store packed minimum values in "dst".

Operation

FOR j := 0 to 7
    i := j*16
    IF a[i+15:i] < b[i+15:i]
        dst[i+15:i] := a[i+15:i]
    ELSE
        dst[i+15:i] := b[i+15:i]
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.5 |


_mm_min_epu32

__m128i _mm_min_epu32( __m128i a, __m128i b )

Synopsis

#include "smmintrin.h"
Instruction: pminud
CPUID Flag: SSE4.1
Category: Special Math Functions

Description

Compare packed unsigned 32-bit integers in "a" and "b", and store packed minimum values in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    IF a[i+31:i] < b[i+31:i]
        dst[i+31:i] := a[i+31:i]
    ELSE
        dst[i+31:i] := b[i+31:i]
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.5 |


_mm_min_epu8

__m128i _mm_min_epu8( __m128i a, __m128i b )

Synopsis

#include "emmintrin.h"
Instruction: pminub
CPUID Flag: SSE2
Category: Special Math Functions

Description

Compare packed unsigned 8-bit integers in "a" and "b", and store packed minimum values in "dst".

Operation

FOR j := 0 to 15
    i := j*8
    IF a[i+7:i] < b[i+7:i]
        dst[i+7:i] := a[i+7:i]
    ELSE
        dst[i+7:i] := b[i+7:i]
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.5 | 1
Knights Landing | 2 | 2 | 1


_mm_min_pd

__m128d _mm_min_pd( __m128d a, __m128d b )

Synopsis

#include "emmintrin.h"
Instruction: minpd
CPUID Flag: SSE2
Category: Special Math Functions

Description

Compare packed double-precision (64-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst".

Operation

FOR j := 0 to 1
    i := j*64
    dst[i+63:i] := MIN(a[i+63:i], b[i+63:i])
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 1 | 1
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 4 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 4 | 0.5 |


_mm_min_pi16

__m64 _mm_min_pi16( __m64 a, __m64 b )

Synopsis

#include "xmmintrin.h"
Instruction: pminsw
CPUID Flag: SSE
Category: Special Math Functions

Description

Compare packed 16-bit integers in "a" and "b", and store packed minimum values in "dst".

Operation

FOR j := 0 to 3
    i := j*16
    IF a[i+15:i] < b[i+15:i]
        dst[i+15:i] := a[i+15:i]
    ELSE
        dst[i+15:i] := b[i+15:i]
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.5 | 1
Knights Landing | 2 | 2 | 1


_mm_min_ps

__m128 _mm_min_ps( __m128 a, __m128 b )

Synopsis

#include "xmmintrin.h"
Instruction: minps
CPUID Flag: SSE
Category: Special Math Functions

Description

Compare packed single-precision (32-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := MIN(a[i+31:i], b[i+31:i])
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 1 | 1
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 4 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 4 | 0.5 |


_mm_min_pu8

__m64 _mm_min_pu8( __m64 a, __m64 b )

Synopsis

#include "xmmintrin.h"
Instruction: pminub
CPUID Flag: SSE
Category: Special Math Functions

Description

Compare packed unsigned 8-bit integers in "a" and "b", and store packed minimum values in "dst".

Operation

FOR j := 0 to 7
    i := j*8
    IF a[i+7:i] < b[i+7:i]
        dst[i+7:i] := a[i+7:i]
    ELSE
        dst[i+7:i] := b[i+7:i]
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.5 | 1
Knights Landing | 2 | 2 | 1


_mm_min_sd

__m128d _mm_min_sd( __m128d a, __m128d b )

Synopsis

#include "emmintrin.h"
Instruction: minsd
CPUID Flag: SSE2
Category: Special Math Functions

Description

Compare the lower double-precision (64-bit) floating-point elements in "a" and "b", store the minimum value in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".

Operation

dst[63:0] := MIN(a[63:0], b[63:0])
dst[127:64] := a[127:64]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 1 | 1
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 4 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 4 | 0.5 |


_mm_min_ss

__m128 _mm_min_ss( __m128 a, __m128 b )

Synopsis

#include "xmmintrin.h"
Instruction: minss
CPUID Flag: SSE
Category: Special Math Functions

Description

Compare the lower single-precision (32-bit) floating-point elements in "a" and "b", store the minimum value in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".

Operation

dst[31:0] := MIN(a[31:0], b[31:0])
dst[127:32] := a[127:32]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 1 | 1
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 4 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 4 | 0.5 |


_mm_minpos_epu16

__m128i _mm_minpos_epu16( __m128i a )

Synopsis

#include "smmintrin.h"
Instruction: phminposuw
CPUID Flag: SSE4.1
Category: Miscellaneous

Description

Horizontally compute the minimum amongst the packed unsigned 16-bit integers in "a", store the minimum and index in "dst", and zero the remaining bits in "dst".

Operation

index[2:0] := 0
min[15:0] := a[15:0]
FOR j := 0 to 7
    i := j*16
    IF a[i+15:i] < min[15:0]
        index[2:0] := j
        min[15:0] := a[i+15:i]
    FI
ENDFOR
dst[15:0] := min[15:0]
dst[18:16] := index[2:0]
dst[127:19] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 2 | 1
Sandy Bridge | 5 | 1 | 1
Ivy Bridge | 5 | 1 | 1
Haswell | 5 | 1 | 1
Broadwell | 5 | 1 | 1
Skylake | 4 | 1 | 1
Knights Landing | 3 | 2 | 1
Ivy Bridge | 5 | 1 |
Haswell | 5 | 1 |
Broadwell | 5 | 1 |
Skylake | 4 | 1 |


_mm_monitor

void _mm_monitor( void const* p, unsigned extensions, unsigned hints )

Synopsis

#include "pmmintrin.h"
Instruction: monitor
CPUID Flag: MONITOR
Category: General Support

Description

Arm address monitoring hardware using the address specified in "p". A store to an address within the specified address range triggers the monitoring hardware. Specify optional extensions in "extensions", and optional hints in "hints".


_mm_move_epi64

__m128i _mm_move_epi64( __m128i a )

Synopsis

#include "emmintrin.h"
Instruction: movq
CPUID Flag: SSE2
Category: Move

Description

Copy the lower 64-bit integer in "a" to the lower element of "dst", and zero the upper element.

Operation

dst[63:0] := a[63:0]
dst[127:64] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.25 | 1
Jaguar | 4 | 1 | 1
Sandy Bridge | 1 |  | 1
Ivy Bridge | 1 | 0.33 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 2 | 1 | 1
Knights Landing | 4 | 1 | 1
Ivy Bridge | 1 | 0.33 |
Haswell | 1 | 0.33 |
Broadwell | 1 | 0.33 |
Skylake | 1 | 0.33 |


_mm_move_sd

__m128d _mm_move_sd( __m128d a, __m128d b )

Synopsis

#include "emmintrin.h"
Instruction: movsd
CPUID Flag: SSE2
Category: Move

Description

Move the lower double-precision (64-bit) floating-point element from "b" to the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".

Operation

dst[63:0] := b[63:0]
dst[127:64] := a[127:64]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.25 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 1 | 1
Ivy Bridge | 1 | 1 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 1 | 1 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm_move_ss

__m128 _mm_move_ss( __m128 a, __m128 b )

Synopsis

#include "xmmintrin.h"
Instruction: movss
CPUID Flag: SSE
Category: Move

Description

Move the lower single-precision (32-bit) floating-point element from "b" to the lower element of "dst", and copy the upper 3 elements from "a" to the upper elements of "dst".

Operation

dst[31:0] := b[31:0]
dst[63:32] := a[63:32]
dst[95:64] := a[95:64]
dst[127:96] := a[127:96]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.25 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 1 | 1
Ivy Bridge | 1 | 1 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 1 | 1 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm_movedup_pd

__m128d _mm_movedup_pd( __m128d a )

Synopsis

#include "pmmintrin.h"
Instruction: movddup
CPUID Flag: SSE3
Category: Move

Description

Duplicate the low double-precision (64-bit) floating-point element from "a", and store the results in "dst".

Operation

tmp[63:0] := a[63:0]
tmp[127:64] := a[63:0]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 1 | 1 | 1
Ivy Bridge | 1 | 1 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 3-6 | 1 | 1
Ivy Bridge | 1 | 1 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm_movehdup_ps

__m128 _mm_movehdup_ps( __m128 a )

Synopsis

#include "pmmintrin.h"
Instruction: movshdup
CPUID Flag: SSE3
Category: Move

Description

Duplicate odd-indexed single-precision (32-bit) floating-point elements from "a", and store the results in "dst".

Operation

dst[31:0] := a[63:32]
dst[63:32] := a[63:32]
dst[95:64] := a[127:96]
dst[127:96] := a[127:96]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 1 | 1
Ivy Bridge | 1 | 1 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 3-6 | 1 | 1
Ivy Bridge | 1 | 1 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm_movehl_ps

__m128 _mm_movehl_ps( __m128 a, __m128 b )

Synopsis

#include "xmmintrin.h"
Instruction: movhlps
CPUID Flag: SSE
Category: Move

Description

Move the upper 2 single-precision (32-bit) floating-point elements from "b" to the lower 2 elements of "dst", and copy the upper 2 elements from "a" to the upper 2 elements of "dst".

Operation

dst[31:0] := b[95:64]
dst[63:32] := b[127:96]
dst[95:64] := a[95:64]
dst[127:96] := a[127:96]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 2 | 1
Sandy Bridge | 1 | 1 | 1
Ivy Bridge | 1 | 1 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 3-6 | 1 | 1
Ivy Bridge | 1 | 1 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm_moveldup_ps

__m128 _mm_moveldup_ps( __m128 a )

Synopsis

#include "pmmintrin.h"
Instruction: movsldup
CPUID Flag: SSE3
Category: Move

Description

Duplicate even-indexed single-precision (32-bit) floating-point elements from "a", and store the results in "dst".

Operation

dst[31:0] := a[31:0]
dst[63:32] := a[31:0]
dst[95:64] := a[95:64]
dst[127:96] := a[95:64]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 1 | 1
Ivy Bridge | 1 | 1 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 3-6 | 1 | 1
Ivy Bridge | 1 | 1 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm_movelh_ps

__m128 _mm_movelh_ps( __m128 a, __m128 b )

Synopsis

#include "xmmintrin.h"
Instruction: movlhps
CPUID Flag: SSE
Category: Move

Description

Move the lower 2 single-precision (32-bit) floating-point elements from "b" to the upper 2 elements of "dst", and copy the lower 2 elements from "a" to the lower 2 elements of "dst".

Operation

dst[31:0] := a[31:0]
dst[63:32] := a[63:32]
dst[95:64] := b[31:0]
dst[127:96] := b[63:32]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 2 | 1
Sandy Bridge | 1 | 1 | 1
Ivy Bridge | 1 | 1 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 3-6 | 1 | 1
Ivy Bridge | 1 | 1 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm_movemask_epi8

int _mm_movemask_epi8( __m128i a )

Synopsis

#include "emmintrin.h"
Instruction: pmovmskb
CPUID Flag: SSE2
Category: Miscellaneous

Description

Create mask from the most significant bit of each 8-bit element in "a", and store the result in "dst".

Operation

FOR j := 0 to 15
    i := j*8
    dst[j] := a[i+7]
ENDFOR
dst[MAX:16] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 1 | 1
Jaguar | 3 | 1 | 1
Sandy Bridge | 2 | 1 | 1
Ivy Bridge | 2 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 2-3 | 1 | 1
Knights Landing | 26 | 12 | 12


_mm_movemask_pd

int _mm_movemask_pd( __m128d a )

Synopsis

#include "emmintrin.h"
Instruction: movmskpd
CPUID Flag: SSE2
Category: Miscellaneous

Description

Set each bit of mask "dst" based on the most significant bit of the corresponding packed double-precision (64-bit) floating-point element in "a".

Operation

FOR j := 0 to 1
    i := j*64
    IF a[i+63]
        dst[j] := 1
    ELSE
        dst[j] := 0
    FI
ENDFOR
dst[MAX:2] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 1 | 1
Jaguar | 3 | 1 | 1
Sandy Bridge | 2 | 1 | 1
Ivy Bridge | 2 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 2 | 1 | 1
Knights Landing | 6 | 7 | 2
Ivy Bridge | 2 | 1 |
Haswell | 2 | 1 |
Broadwell | 2 | 1 |
Skylake | 2 | 1 |


_mm_movemask_pi8

int _mm_movemask_pi8( __m64 a )

Synopsis

#include "xmmintrin.h"
Instruction: pmovmskb
CPUID Flag: SSE
Category: Miscellaneous

Description

Create mask from the most significant bit of each 8-bit element in "a", and store the result in "dst".

Operation

FOR j := 0 to 7
    i := j*8
    dst[j] := a[i+7]
ENDFOR
dst[MAX:8] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 1 | 1
Jaguar | 3 | 1 | 1
Sandy Bridge | 2 | 1 | 1
Ivy Bridge | 2 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 2-3 | 1 | 1
Knights Landing | 26 | 12 | 12


_mm_movemask_ps

int _mm_movemask_ps( __m128 a )

Synopsis

#include "xmmintrin.h"
Instruction: movmskps
CPUID Flag: SSE
Category: Miscellaneous

Description

Set each bit of mask "dst" based on the most significant bit of the corresponding packed single-precision (32-bit) floating-point element in "a".

Operation

FOR j := 0 to 3
    i := j*32
    IF a[i+31]
        dst[j] := 1
    ELSE
        dst[j] := 0
    FI
ENDFOR
dst[MAX:4] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 1 | 1
Jaguar | 3 | 1 | 1
Sandy Bridge | 2 | 1 | 1
Ivy Bridge | 2 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 2 | 1 | 1
Knights Landing | 6 | 7 | 2
Ivy Bridge | 2 | 1 |
Haswell | 2 | 1 |
Broadwell | 2 | 1 |
Skylake | 2 | 1 |


_mm_movepi64_pi64

__m64 _mm_movepi64_pi64( __m128i a )

Synopsis

#include "emmintrin.h"
Instruction: movdq2q
CPUID Flag: SSE2
Category: Miscellaneous

Description

Copy the lower 64-bit integer in "a" to "dst".

Operation

dst[63:0] := a[63:0]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.25 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 1 | 2
Ivy Bridge | 1 | 1 | 2
Haswell | 1 | 1 | 2
Broadwell | 1 | 1 | 2
Skylake | 2 | 1 | 2
Knights Landing | 2 | 0.5 | 1


_mm_movpi64_epi64

__m128i _mm_movpi64_epi64( __m64 a )

Synopsis

#include "emmintrin.h"
Instruction: movq2dq
CPUID Flag: SSE2
Category: Move

Description

Copy the 64-bit integer "a" to the lower element of "dst", and zero the upper element.

Operation

dst[63:0] := a[63:0]
dst[127:64] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.25 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 |  | 1
Ivy Bridge | 1 | 0.33 | 1
Haswell | 1 | 0.33 | 1
Broadwell | 1 | 0.33 | 1
Skylake | 2 | 1 | 2
Knights Landing | 2 | 0.5 | 1


_mm_mpsadbw_epu8

__m128i _mm_mpsadbw_epu8( __m128i a, __m128i b, const int imm8 )

Synopsis

#include "smmintrin.h"
Instruction: mpsadbw
CPUID Flag: SSE4.1
Category: Arithmetic

Description

Compute the sum of absolute differences (SADs) of quadruplets of unsigned 8-bit integers in "a" compared to those in "b", and store the 16-bit results in "dst". Eight SADs are performed using one quadruplet from "b" and eight quadruplets from "a". One quadruplet is selected from "b" starting at on the offset specified in "imm8". Eight quadruplets are formed from sequential 8-bit integers selected from "a" starting at the offset specified in "imm8".

Operation

DEFINE MPSADBW(a[127:0], b[127:0], imm8[2:0]) {
    a_offset := imm8[2]*32
    b_offset := imm8[1:0]*32
    FOR j := 0 to 7
        i := j*8
        k := a_offset+i
        l := b_offset
        tmp[i*2+15:i*2] := ABS(a[k+7:k] - b[l+7:l]) + ABS(a[k+15:k+8] - b[l+15:l+8]) + ABS(a[k+23:k+16] - b[l+23:l+16]) + ABS(a[k+31:k+24] - b[l+31:l+24])
    ENDFOR
    RETURN tmp[127:0]
}
dst[127:0] := MPSADBW(a[127:0], b[127:0], imm8[2:0])

Performance

Architecture | Latency | Throughput | μops
Ryzen | 4 | 2 | 4
Jaguar | 4 | 1 | 3
Sandy Bridge | 6 | 1 | 3
Ivy Bridge | 6 | 1 | 3
Haswell | 6 | 2 | 3
Broadwell | 6 | 2 | 3
Skylake | 4 | 2 | 2
Knights Landing | 9 | 9 | 3
Ivy Bridge | 6 | 1 |
Haswell | 6 | 2 |
Broadwell | 6 | 2 |
Skylake | 4 | 2 |


_mm_mul_epi32

__m128i _mm_mul_epi32( __m128i a, __m128i b )

Synopsis

#include "smmintrin.h"
Instruction: pmuldq
CPUID Flag: SSE4.1
Category: Arithmetic

Description

Multiply the low 32-bit integers from each packed 64-bit element in "a" and "b", and store the signed 64-bit results in "dst".

Operation

FOR j := 0 to 1
    i := j*64
    dst[i+63:i] := a[i+31:i] * b[i+31:i]
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 1 | 1
Jaguar | 2 | 1 | 1
Sandy Bridge | 5 | 1 | 1
Ivy Bridge | 5 | 1 | 1
Haswell | 5 | 1 | 1
Broadwell | 5 | 1 | 1
Skylake | 5 | 0.5 | 1
Knights Landing | 6 | 2 | 1
Ivy Bridge | 5 | 1 |
Haswell | 5 | 1 |
Broadwell | 5 | 1 |
Skylake | 5 | 0.5 |


_mm_mul_epu32

__m128i _mm_mul_epu32( __m128i a, __m128i b )

Synopsis

#include "emmintrin.h"
Instruction: pmuludq
CPUID Flag: SSE2
Category: Arithmetic

Description

Multiply the low unsigned 32-bit integers from each packed 64-bit element in "a" and "b", and store the unsigned 64-bit results in "dst".

Operation

FOR j := 0 to 1
    i := j*64
    dst[i+63:i] := a[i+31:i] * b[i+31:i]
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 1 | 1
Jaguar | 2 | 1 | 1
Sandy Bridge | 5 | 1 | 1
Ivy Bridge | 5 | 1 | 1
Haswell | 5 | 1 | 1
Broadwell | 5 | 1 | 1
Skylake | 5 | 0.5 | 1
Knights Landing | 6 | 0.5 | 1
Ivy Bridge | 5 | 1 |
Haswell | 5 | 1 |
Broadwell | 5 | 1 |
Skylake | 5 | 0.5 |


_mm_mul_pd

__m128d _mm_mul_pd( __m128d a, __m128d b )

Synopsis

#include "emmintrin.h"
Instruction: mulpd
CPUID Flag: SSE2
Category: Arithmetic

Description

Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*64
    dst[i+63:i] := a[i+63:i] * b[i+63:i]
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 4 | 0.5 | 1
Jaguar | 4 | 2 | 1
Sandy Bridge | 5 | 1 | 1
Ivy Bridge | 5 | 1 | 1
Haswell | 5 | 0.5 | 1
Broadwell | 3 | 0.5 | 1
Skylake | 4 | 0.5 | 1
Knights Landing | 6 | 0.5 | 1
Ivy Bridge | 5 | 1 |
Haswell | 5 | 0.5 |
Broadwell | 5 | 0.5 |
Skylake | 3 | 0.5 |


_mm_mul_ps

__m128 _mm_mul_ps( __m128 a, __m128 b )

Synopsis

#include "xmmintrin.h"
Instruction: mulps
CPUID Flag: SSE
Category: Arithmetic

Description

Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := a[i+31:i] * b[i+31:i]
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 0.5 | 1
Jaguar | 2 | 1 | 1
Sandy Bridge | 5 | 1 | 1
Ivy Bridge | 5 | 1 | 1
Haswell | 5 | 0.5 | 1
Broadwell | 3 | 0.5 | 1
Skylake | 4 | 0.5 | 1
Knights Landing | 6 | 0.5 | 1
Ivy Bridge | 5 | 1 |
Haswell | 5 | 0.5 |
Broadwell | 3 | 0.5 |
Skylake | 4 | 0.5 |


_mm_mul_sd

__m128d _mm_mul_sd( __m128d a, __m128d b )

Synopsis

#include "emmintrin.h"
Instruction: mulsd
CPUID Flag: SSE2
Category: Arithmetic

Description

Multiply the lower double-precision (64-bit) floating-point element in "a" and "b", store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".

Operation

dst[63:0] := a[63:0] * b[63:0]
dst[127:64] := a[127:64]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 4 | 0.5 | 1
Jaguar | 4 | 2 | 1
Sandy Bridge | 5 | 1 | 1
Ivy Bridge | 5 | 1 | 1
Haswell | 5 | 0.5 | 1
Broadwell | 3 | 0.5 | 1
Skylake | 4 | 0.5 | 1
Knights Landing | 6 | 0.5 | 1
Ivy Bridge | 5 | 1 |
Haswell | 5 | 0.5 |
Broadwell | 5 | 0.5 |
Skylake | 3 | 0.5 |


_mm_mul_ss

__m128 _mm_mul_ss( __m128 a, __m128 b )

Synopsis

#include "xmmintrin.h"
Instruction: mulss
CPUID Flag: SSE
Category: Arithmetic

Description

Multiply the lower single-precision (32-bit) floating-point element in "a" and "b", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".

Operation

dst[31:0] := a[31:0] * b[31:0]
dst[127:32] := a[127:32]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 0.5 | 1
Jaguar | 2 | 1 | 1
Sandy Bridge | 5 | 1 | 1
Ivy Bridge | 5 | 1 | 1
Haswell | 5 | 0.5 | 1
Broadwell | 3 | 0.5 | 1
Skylake | 4 | 0.5 | 1
Knights Landing | 6 | 0.5 | 1
Ivy Bridge | 5 | 1 |
Haswell | 5 | 0.5 |
Broadwell | 3 | 0.5 |
Skylake | 4 | 0.5 |


_mm_mul_su32

__m64 _mm_mul_su32( __m64 a, __m64 b )

Synopsis

#include "emmintrin.h"
Instruction: pmuludq
CPUID Flag: SSE2
Category: Arithmetic

Description

Multiply the low unsigned 32-bit integers from "a" and "b", and store the unsigned 64-bit result in "dst".

Operation

dst[63:0] := a[31:0] * b[31:0]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 1 | 1
Jaguar | 2 | 1 | 1
Sandy Bridge | 5 | 1 | 1
Ivy Bridge | 5 | 1 | 1
Haswell | 5 | 1 | 1
Broadwell | 5 | 1 | 1
Skylake | 5 | 0.5 | 1
Knights Landing | 6 | 0.5 | 1
Ivy Bridge | 5 | 1 |
Haswell | 5 | 1 |
Broadwell | 5 | 1 |
Skylake | 5 | 0.5 |


_mm_mulhi_epi16

__m128i _mm_mulhi_epi16( __m128i a, __m128i b )

Synopsis

#include "emmintrin.h"
Instruction: pmulhw
CPUID Flag: SSE2
Category: Arithmetic

Description

Multiply the packed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst".

Operation

FOR j := 0 to 7
    i := j*16
    tmp[31:0] := a[i+15:i] * b[i+15:i]
    dst[i+15:i] := tmp[31:16]
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 1 | 1
Jaguar | 2 | 1 | 1
Sandy Bridge | 5 | 1 | 1
Ivy Bridge | 5 | 1 | 1
Haswell | 5 | 1 | 1
Broadwell | 5 | 1 | 1
Skylake | 5 | 0.5 | 1
Knights Landing | 7 | 2 | 1
Ivy Bridge | 5 | 1 |
Haswell | 5 | 1 |
Broadwell | 5 | 1 |
Skylake | 5 | 0.5 |


_mm_mulhi_epu16

__m128i _mm_mulhi_epu16( __m128i a, __m128i b )

Synopsis

#include "emmintrin.h"
Instruction: pmulhuw
CPUID Flag: SSE2
Category: Arithmetic

Description

Multiply the packed unsigned 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst".

Operation

FOR j := 0 to 7
    i := j*16
    tmp[31:0] := a[i+15:i] * b[i+15:i]
    dst[i+15:i] := tmp[31:16]
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 1 | 1
Jaguar | 2 | 1 | 1
Sandy Bridge | 5 | 1 | 1
Ivy Bridge | 5 | 1 | 1
Haswell | 5 | 1 | 1
Broadwell | 5 | 1 | 1
Skylake | 5 | 0.5 | 1
Knights Landing | 7 | 2 | 1
Ivy Bridge | 5 | 1 |
Haswell | 5 | 1 |
Broadwell | 5 | 1 |
Skylake | 5 | 0.5 |


_mm_mulhi_pi16

__m64 _mm_mulhi_pi16( __m64 a, __m64 b )

Synopsis

#include "mmintrin.h"
Instruction: pmulhw
CPUID Flag: MMX
Category: Arithmetic

Description

Multiply the packed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst".

Operation

FOR j := 0 to 3
    i := j*16
    tmp[31:0] := a[i+15:i] * b[i+15:i]
    dst[i+15:i] := tmp[31:16]
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 1 | 1
Jaguar | 2 | 1 | 1
Sandy Bridge | 5 | 1 | 1
Ivy Bridge | 5 | 1 | 1
Haswell | 5 | 1 | 1
Broadwell | 5 | 1 | 1
Skylake | 5 | 0.5 | 1
Knights Landing | 7 | 2 | 1


_mm_mulhi_pu16

__m64 _mm_mulhi_pu16( __m64 a, __m64 b )

Synopsis

#include "xmmintrin.h"
Instruction: pmulhuw
CPUID Flag: SSE
Category: Arithmetic

Description

Multiply the packed unsigned 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst".

Operation

FOR j := 0 to 3
    i := j*16
    tmp[31:0] := a[i+15:i] * b[i+15:i]
    dst[i+15:i] := tmp[31:16]
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 1 | 1
Jaguar | 2 | 1 | 1
Sandy Bridge | 5 | 1 | 1
Ivy Bridge | 5 | 1 | 1
Haswell | 5 | 1 | 1
Broadwell | 5 | 1 | 1
Skylake | 5 | 0.5 | 1
Knights Landing | 7 | 2 | 1


_mm_mulhrs_epi16

__m128i _mm_mulhrs_epi16( __m128i a, __m128i b )

Synopsis

#include "tmmintrin.h"
Instruction: pmulhrsw
CPUID Flag: SSSE3
Category: Arithmetic

Description

Multiply packed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers. Truncate each intermediate integer to the 18 most significant bits, round by adding 1, and store bits [16:1] to "dst".

Operation

FOR j := 0 to 7
    i := j*16
    tmp[31:0] := ((a[i+15:i] * b[i+15:i]) >> 14) + 1
    dst[i+15:i] := tmp[16:1]
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 4 | 1 | 1
Jaguar | 2 | 1 | 1
Sandy Bridge | 5 | 1 | 1
Ivy Bridge | 5 | 1 | 1
Haswell | 5 | 1 | 1
Broadwell | 5 | 1 | 1
Skylake | 5 | 0.5 | 1
Knights Landing | 7 | 2 | 1
Ivy Bridge | 5 | 1 |
Haswell | 5 | 1 |
Broadwell | 5 | 1 |
Skylake | 5 | 0.5 |


_mm_mulhrs_pi16

__m64 _mm_mulhrs_pi16( __m64 a, __m64 b )

Synopsis

#include "tmmintrin.h"
Instruction: pmulhrsw
CPUID Flag: SSSE3
Category: Arithmetic

Description

Multiply packed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers. Truncate each intermediate integer to the 18 most significant bits, round by adding 1, and store bits [16:1] to "dst".

Operation

FOR j := 0 to 3
    i := j*16
    tmp[31:0] := ((a[i+15:i] * b[i+15:i]) >> 14) + 1
    dst[i+15:i] := tmp[16:1]
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 4 | 1 | 1
Jaguar | 2 | 1 | 1
Sandy Bridge | 5 | 1 | 1
Ivy Bridge | 5 | 1 | 1
Haswell | 5 | 1 | 1
Broadwell | 5 | 1 | 1
Skylake | 5 | 0.5 | 1
Knights Landing | 7 | 2 | 1
Ivy Bridge | 5 | 1 |
Haswell | 5 | 1 |
Broadwell | 5 | 1 |
Skylake | 5 | 0.5 |


_mm_mullo_epi16

__m128i _mm_mullo_epi16( __m128i a, __m128i b )

Synopsis

#include "emmintrin.h"
Instruction: pmullw
CPUID Flag: SSE2
Category: Arithmetic

Description

Multiply the packed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the low 16 bits of the intermediate integers in "dst".

Operation

FOR j := 0 to 7
    i := j*16
    tmp[31:0] := a[i+15:i] * b[i+15:i]
    dst[i+15:i] := tmp[15:0]
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 1 | 1
Jaguar | 2 | 1 | 1
Sandy Bridge | 5 | 1 | 1
Ivy Bridge | 5 | 1 | 1
Haswell | 5 | 1 | 1
Broadwell | 5 | 1 | 1
Skylake | 5 | 0.5 | 1
Knights Landing | 7 | 2 | 1
Ivy Bridge | 5 | 1 |
Haswell | 5 | 1 |
Broadwell | 5 | 1 |
Skylake | 5 | 0.5 |


_mm_mullo_epi32

__m128i _mm_mullo_epi32( __m128i a, __m128i b )

Synopsis

#include "smmintrin.h"
Instruction: pmulld
CPUID Flag: SSE4.1
Category: Arithmetic

Description

Multiply the packed 32-bit integers in "a" and "b", producing intermediate 64-bit integers, and store the low 32 bits of the intermediate integers in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    tmp[63:0] := a[i+31:i] * b[i+31:i]
    dst[i+31:i] := tmp[31:0]
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 4 | 2 | 1
Jaguar | 4 | 2 | 3
Sandy Bridge | 5 | 1 | 1
Ivy Bridge | 5 | 1 | 1
Haswell | 10 | 2 | 2
Broadwell | 10 | 2 | 2
Skylake | 10 | 1 | 2
Knights Landing | 7 | 2 | 1
Ivy Bridge | 5 | 1 |
Haswell | 10 | 2 |
Broadwell | 10 | 2 |
Skylake | 10 | 2 |


_mm_mullo_pi16

__m64 _mm_mullo_pi16( __m64 a, __m64 b )

Synopsis

#include "mmintrin.h"
Instruction: pmullw
CPUID Flag: MMX
Category: Arithmetic

Description

Multiply the packed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the low 16 bits of the intermediate integers in "dst".

Operation

FOR j := 0 to 3
    i := j*16
    tmp[31:0] := a[i+15:i] * b[i+15:i]
    dst[i+15:i] := tmp[15:0]
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 1 | 1
Jaguar | 2 | 1 | 1
Sandy Bridge | 5 | 1 | 1
Ivy Bridge | 5 | 1 | 1
Haswell | 5 | 1 | 1
Broadwell | 5 | 1 | 1
Skylake | 5 | 0.5 | 1
Knights Landing | 7 | 2 | 1


_mm_mwait

void _mm_mwait( unsigned extensions, unsigned hints )

Synopsis

#include "pmmintrin.h"
Instruction: mwait
CPUID Flag: MONITOR
Category: General Support

Description

Hint to the processor that it can enter an implementation-dependent-optimized state while waiting for an event or store operation to the address range specified by MONITOR.


_mm_or_pd

__m128d _mm_or_pd( __m128d a, __m128d b )

Synopsis

#include "emmintrin.h"
Instruction: orpd
CPUID Flag: SSE2
Category: Logical

Description

Compute the bitwise OR of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*64
    dst[i+63:i] := a[i+63:i] OR b[i+63:i]
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.25 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 1 | 1
Ivy Bridge | 1 | 1 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 0.33 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 1 | 1 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 0.33 |


_mm_or_ps

__m128 _mm_or_ps( __m128 a, __m128 b )

Synopsis

#include "xmmintrin.h"
Instruction: orps
CPUID Flag: SSE
Category: Logical

Description

Compute the bitwise OR of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := a[i+31:i] OR b[i+31:i]
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.25 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 1 | 1
Ivy Bridge | 1 | 1 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 0.33 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 1 | 1 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 0.33 |


_mm_or_si128

__m128i _mm_or_si128( __m128i a, __m128i b )

Synopsis

#include "emmintrin.h"
Instruction: por
CPUID Flag: SSE2
Category: Logical

Description

Compute the bitwise OR of 128 bits (representing integer data) in "a" and "b", and store the result in "dst".

Operation

dst[127:0] := (a[127:0] OR b[127:0])

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.25 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 |  | 1
Ivy Bridge | 1 | 0.33 | 1
Haswell | 1 | 0.33 | 1
Broadwell | 1 | 0.33 | 1
Skylake | 1 | 0.33 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 1 | 0.33 |
Haswell | 1 | 0.33 |
Broadwell | 1 | 0.33 |
Skylake | 1 | 0.33 |


_mm_or_si64

__m64 _mm_or_si64( __m64 a, __m64 b )

Synopsis

#include "mmintrin.h"
Instruction: por
CPUID Flag: MMX
Category: Logical

Description

Compute the bitwise OR of 64 bits (representing integer data) in "a" and "b", and store the result in "dst".

Operation

dst[63:0] := (a[63:0] OR b[63:0])

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.25 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 |  | 1
Ivy Bridge | 1 | 0.33 | 1
Haswell | 1 | 0.33 | 1
Broadwell | 1 | 0.33 | 1
Skylake | 1 | 0.33 | 1
Knights Landing | 2 | 0.5 | 1


_mm_packs_epi16

__m128i _mm_packs_epi16( __m128i a, __m128i b )

Synopsis

#include "emmintrin.h"
Instruction: packsswb
CPUID Flag: SSE2
Category: Miscellaneous

Description

Convert packed 16-bit integers from "a" and "b" to packed 8-bit integers using signed saturation, and store the results in "dst".

Operation

dst[7:0] := Saturate_Int16_To_Int8 (a[15:0])
dst[15:8] := Saturate_Int16_To_Int8 (a[31:16])
dst[23:16] := Saturate_Int16_To_Int8 (a[47:32])
dst[31:24] := Saturate_Int16_To_Int8 (a[63:48])
dst[39:32] := Saturate_Int16_To_Int8 (a[79:64])
dst[47:40] := Saturate_Int16_To_Int8 (a[95:80])
dst[55:48] := Saturate_Int16_To_Int8 (a[111:96])
dst[63:56] := Saturate_Int16_To_Int8 (a[127:112])
dst[71:64] := Saturate_Int16_To_Int8 (b[15:0])
dst[79:72] := Saturate_Int16_To_Int8 (b[31:16])
dst[87:80] := Saturate_Int16_To_Int8 (b[47:32])
dst[95:88] := Saturate_Int16_To_Int8 (b[63:48])
dst[103:96] := Saturate_Int16_To_Int8 (b[79:64])
dst[111:104] := Saturate_Int16_To_Int8 (b[95:80])
dst[119:112] := Saturate_Int16_To_Int8 (b[111:96])
dst[127:120] := Saturate_Int16_To_Int8 (b[127:112])

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm_packs_epi32

__m128i _mm_packs_epi32( __m128i a, __m128i b )

Synopsis

#include "emmintrin.h"
Instruction: packssdw
CPUID Flag: SSE2
Category: Miscellaneous

Description

Convert packed 32-bit integers from "a" and "b" to packed 16-bit integers using signed saturation, and store the results in "dst".

Operation

dst[15:0] := Saturate_Int32_To_Int16 (a[31:0])
dst[31:16] := Saturate_Int32_To_Int16 (a[63:32])
dst[47:32] := Saturate_Int32_To_Int16 (a[95:64])
dst[63:48] := Saturate_Int32_To_Int16 (a[127:96])
dst[79:64] := Saturate_Int32_To_Int16 (b[31:0])
dst[95:80] := Saturate_Int32_To_Int16 (b[63:32])
dst[111:96] := Saturate_Int32_To_Int16 (b[95:64])
dst[127:112] := Saturate_Int32_To_Int16 (b[127:96])

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm_packs_pi16

__m64 _mm_packs_pi16( __m64 a, __m64 b )

Synopsis

#include "mmintrin.h"
Instruction: packsswb
CPUID Flag: MMX
Category: Miscellaneous

Description

Convert packed 16-bit integers from "a" and "b" to packed 8-bit integers using signed saturation, and store the results in "dst".

Operation

dst[7:0] := Saturate_Int16_To_Int8 (a[15:0])
dst[15:8] := Saturate_Int16_To_Int8 (a[31:16])
dst[23:16] := Saturate_Int16_To_Int8 (a[47:32])
dst[31:24] := Saturate_Int16_To_Int8 (a[63:48])
dst[39:32] := Saturate_Int16_To_Int8 (b[15:0])
dst[47:40] := Saturate_Int16_To_Int8 (b[31:16])
dst[55:48] := Saturate_Int16_To_Int8 (b[47:32])
dst[63:56] := Saturate_Int16_To_Int8 (b[63:48])

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1


_mm_packs_pi32

__m64 _mm_packs_pi32( __m64 a, __m64 b )

Synopsis

#include "mmintrin.h"
Instruction: packssdw
CPUID Flag: MMX
Category: Miscellaneous

Description

Convert packed 32-bit integers from "a" and "b" to packed 16-bit integers using signed saturation, and store the results in "dst".

Operation

dst[15:0] := Saturate_Int32_To_Int16 (a[31:0])
dst[31:16] := Saturate_Int32_To_Int16 (a[63:32])
dst[47:32] := Saturate_Int32_To_Int16 (b[31:0])
dst[63:48] := Saturate_Int32_To_Int16 (b[63:32])

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1


_mm_packs_pu16

__m64 _mm_packs_pu16( __m64 a, __m64 b )

Synopsis

#include "mmintrin.h"
Instruction: packuswb
CPUID Flag: MMX
Category: Miscellaneous

Description

Convert packed 16-bit integers from "a" and "b" to packed 8-bit integers using unsigned saturation, and store the results in "dst".

Operation

dst[7:0] := Saturate_Int16_To_UnsignedInt8 (a[15:0])
dst[15:8] := Saturate_Int16_To_UnsignedInt8 (a[31:16])
dst[23:16] := Saturate_Int16_To_UnsignedInt8 (a[47:32])
dst[31:24] := Saturate_Int16_To_UnsignedInt8 (a[63:48])
dst[39:32] := Saturate_Int16_To_UnsignedInt8 (b[15:0])
dst[47:40] := Saturate_Int16_To_UnsignedInt8 (b[31:16])
dst[55:48] := Saturate_Int16_To_UnsignedInt8 (b[47:32])
dst[63:56] := Saturate_Int16_To_UnsignedInt8 (b[63:48])

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1


_mm_packus_epi16

__m128i _mm_packus_epi16( __m128i a, __m128i b )

Synopsis

#include "emmintrin.h"
Instruction: packuswb
CPUID Flag: SSE2
Category: Miscellaneous

Description

Convert packed 16-bit integers from "a" and "b" to packed 8-bit integers using unsigned saturation, and store the results in "dst".

Operation

dst[7:0] := Saturate_Int16_To_UnsignedInt8 (a[15:0])
dst[15:8] := Saturate_Int16_To_UnsignedInt8 (a[31:16])
dst[23:16] := Saturate_Int16_To_UnsignedInt8 (a[47:32])
dst[31:24] := Saturate_Int16_To_UnsignedInt8 (a[63:48])
dst[39:32] := Saturate_Int16_To_UnsignedInt8 (a[79:64])
dst[47:40] := Saturate_Int16_To_UnsignedInt8 (a[95:80])
dst[55:48] := Saturate_Int16_To_UnsignedInt8 (a[111:96])
dst[63:56] := Saturate_Int16_To_UnsignedInt8 (a[127:112])
dst[71:64] := Saturate_Int16_To_UnsignedInt8 (b[15:0])
dst[79:72] := Saturate_Int16_To_UnsignedInt8 (b[31:16])
dst[87:80] := Saturate_Int16_To_UnsignedInt8 (b[47:32])
dst[95:88] := Saturate_Int16_To_UnsignedInt8 (b[63:48])
dst[103:96] := Saturate_Int16_To_UnsignedInt8 (b[79:64])
dst[111:104] := Saturate_Int16_To_UnsignedInt8 (b[95:80])
dst[119:112] := Saturate_Int16_To_UnsignedInt8 (b[111:96])
dst[127:120] := Saturate_Int16_To_UnsignedInt8 (b[127:112])

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm_packus_epi32

__m128i _mm_packus_epi32( __m128i a, __m128i b )

Synopsis

#include "smmintrin.h"
Instruction: packusdw
CPUID Flag: SSE4.1
Category: Convert

Description

Convert packed 32-bit integers from "a" and "b" to packed 16-bit integers using unsigned saturation, and store the results in "dst".

Operation

dst[15:0] := Saturate_Int32_To_UnsignedInt16 (a[31:0])
dst[31:16] := Saturate_Int32_To_UnsignedInt16 (a[63:32])
dst[47:32] := Saturate_Int32_To_UnsignedInt16 (a[95:64])
dst[63:48] := Saturate_Int32_To_UnsignedInt16 (a[127:96])
dst[79:64] := Saturate_Int32_To_UnsignedInt16 (b[31:0])
dst[95:80] := Saturate_Int32_To_UnsignedInt16 (b[63:32])
dst[111:96] := Saturate_Int32_To_UnsignedInt16 (b[95:64])
dst[127:112] := Saturate_Int32_To_UnsignedInt16 (b[127:96])

Performance

Architecture | Latency | Throughput | μops
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm_pause

void _mm_pause( void )

Synopsis

#include "emmintrin.h"
Instruction: pause
CPUID Flag: SSE2
Category: General Support

Description

Provide a hint to the processor that the code sequence is a spin-wait loop. This can help improve the performance and power consumption of spin-wait loops.


_mm_permute_pd

__m128d _mm_permute_pd( __m128d a, int imm8 )

Synopsis

#include "immintrin.h"
Instruction: vpermilpd
CPUID Flag: AVX
Category: Swizzle

Description

Shuffle double-precision (64-bit) floating-point elements in "a" using the control in "imm8", and store the results in "dst".

Operation

IF (imm8[0] == 0) dst[63:0] := a[63:0]; FI
IF (imm8[0] == 1) dst[63:0] := a[127:64]; FI
IF (imm8[1] == 0) dst[127:64] := a[63:0]; FI
IF (imm8[1] == 1) dst[127:64] := a[127:64]; FI
dst[MAX:128] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 4 | 4 | 2
Sandy Bridge | 1 | 1 | 1
Ivy Bridge | 1 | 1 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 3-6 | 1 | 1
Ivy Bridge | 1 | 1 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm_permute_ps

__m128 _mm_permute_ps( __m128 a, int imm8 )

Synopsis

#include "immintrin.h"
Instruction: vpermilps
CPUID Flag: AVX
Category: Swizzle

Description

Shuffle single-precision (32-bit) floating-point elements in "a" using the control in "imm8", and store the results in "dst".

Operation

DEFINE SELECT4(src, control) {
    CASE(control[1:0]) OF
    0:	tmp[31:0] := src[31:0]
    1:	tmp[31:0] := src[63:32]
    2:	tmp[31:0] := src[95:64]
    3:	tmp[31:0] := src[127:96]
    ESAC
    RETURN tmp[31:0]
}
dst[31:0] := SELECT4(a[127:0], imm8[1:0])
dst[63:32] := SELECT4(a[127:0], imm8[3:2])
dst[95:64] := SELECT4(a[127:0], imm8[5:4])
dst[127:96] := SELECT4(a[127:0], imm8[7:6])
dst[MAX:128] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 4 | 4 | 2
Sandy Bridge | 1 | 1 | 1
Ivy Bridge | 1 | 1 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 3-6 | 1 | 1
Ivy Bridge | 1 | 1 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm_permutevar_pd

__m128d _mm_permutevar_pd( __m128d a, __m128i b )

Synopsis

#include "immintrin.h"
Instruction: vpermilpd
CPUID Flag: AVX
Category: Swizzle

Description

Shuffle double-precision (64-bit) floating-point elements in "a" using the control in "b", and store the results in "dst".

Operation

IF (b[1] == 0) dst[63:0] := a[63:0]; FI
IF (b[1] == 1) dst[63:0] := a[127:64]; FI
IF (b[65] == 0) dst[127:64] := a[63:0]; FI
IF (b[65] == 1) dst[127:64] := a[127:64]; FI
dst[MAX:128] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 4 | 4 | 2
Sandy Bridge | 1 | 1 | 1
Ivy Bridge | 1 | 1 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 3-6 | 1 | 1
Ivy Bridge | 1 | 1 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm_permutevar_ps

__m128 _mm_permutevar_ps( __m128 a, __m128i b )

Synopsis

#include "immintrin.h"
Instruction: vpermilps
CPUID Flag: AVX
Category: Swizzle

Description

Shuffle single-precision (32-bit) floating-point elements in "a" using the control in "b", and store the results in "dst".

Operation

DEFINE SELECT4(src, control) {
    CASE(control[1:0]) OF
    0:	tmp[31:0] := src[31:0]
    1:	tmp[31:0] := src[63:32]
    2:	tmp[31:0] := src[95:64]
    3:	tmp[31:0] := src[127:96]
    ESAC
    RETURN tmp[31:0]
}
dst[31:0] := SELECT4(a[127:0], b[1:0])
dst[63:32] := SELECT4(a[127:0], b[33:32])
dst[95:64] := SELECT4(a[127:0], b[65:64])
dst[127:96] := SELECT4(a[127:0], b[97:96])
dst[MAX:128] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 4 | 4 | 2
Sandy Bridge | 1 | 1 | 1
Ivy Bridge | 1 | 1 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 3-6 | 1 | 1
Ivy Bridge | 1 | 1 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm_popcnt_u32

int _mm_popcnt_u32( unsigned int a )

Synopsis

#include "nmmintrin.h"
Instruction: popcnt
CPUID Flag: POPCNT
Category: Bit Manipulation

Description

Count the number of bits set to 1 in unsigned 32-bit integer "a", and return that count in "dst".

Operation

dst := 0
FOR i := 0 to 31
    IF a[i]
        dst := dst + 1
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.25 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 3 | 1 | 1
Knights Landing | 7 | 7 | 2
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 3 | 1 |


_mm_popcnt_u64

__int64 _mm_popcnt_u64( unsigned __int64 a )

Synopsis

#include "nmmintrin.h"
Instruction: popcnt
CPUID Flag: POPCNT
Category: Bit Manipulation

Description

Count the number of bits set to 1 in unsigned 64-bit integer "a", and return that count in "dst".

Operation

dst := 0
FOR i := 0 to 63
    IF a[i]
        dst := dst + 1
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.25 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 3 | 1 | 1
Knights Landing | 7 | 7 | 2
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 3 | 1 |


_mm_pow_pd

__m128d _mm_pow_pd( __m128d a, __m128d b )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Elementary Math Functions

Description

Compute the exponential value of packed double-precision (64-bit) floating-point elements in "a" raised by packed elements in "b", and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*64
    dst[i+63:i] := (a[i+63:i])^(b[i+63:i])
ENDFOR
dst[MAX:128] := 0


_mm_pow_ps

__m128 _mm_pow_ps( __m128 a, __m128 b )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Elementary Math Functions

Description

Compute the exponential value of packed single-precision (32-bit) floating-point elements in "a" raised by packed elements in "b", and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := (a[i+31:i])^(b[i+31:i])
ENDFOR
dst[MAX:128] := 0


_mm_prefetch Other

void _mm_prefetch( char const* p, int i )

Synopsis

#include "xmmintrin.h"
Instruction: prefetchwt1
CPUID Flag: PREFETCHWT1
Category: General Support

Description

Fetch the line of data from memory that contains address "p" to a location in the cache heirarchy specified by the locality hint "i".


_mm_prefetch SSE

void _mm_prefetch( char const* p, int i )

Synopsis

#include "xmmintrin.h"
Instruction: prefetchnta
CPUID Flag: SSE
Category: General Support

Description

Fetch the line of data from memory that contains address "p" to a location in the cache heirarchy specified by the locality hint "i".


_mm_rcp_ps

__m128 _mm_rcp_ps( __m128 a )

Synopsis

#include "xmmintrin.h"
Instruction: rcpps
CPUID Flag: SSE
Category: Elementary Math Functions

Description

Compute the approximate reciprocal of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". The maximum relative error for this approximation is less than 1.5*2^-12.

Operation

FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := APPROXIMATE(1.0/a[i+31:i])
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 5 | 1 | 1
Jaguar | 2 | 1 | 1
Sandy Bridge | 5 | 1 | 1
Ivy Bridge | 5 | 1 | 1
Haswell | 5 | 1 | 1
Broadwell | 5 | 1 | 1
Skylake | 4 | 1 | 1
Knights Landing | 8 | 3 | 1
Ivy Bridge | 5 | 1 |
Haswell | 5 | 1 |
Broadwell | 5 | 1 |
Skylake | 4 | 1 |


_mm_rcp_ss

__m128 _mm_rcp_ss( __m128 a )

Synopsis

#include "xmmintrin.h"
Instruction: rcpss
CPUID Flag: SSE
Category: Elementary Math Functions

Description

Compute the approximate reciprocal of the lower single-precision (32-bit) floating-point element in "a", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". The maximum relative error for this approximation is less than 1.5*2^-12.

Operation

dst[31:0] := APPROXIMATE(1.0/a[31:0])
dst[127:32] := a[127:32]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 5 | 1 | 1
Jaguar | 2 | 1 | 1
Sandy Bridge | 5 | 1 | 1
Ivy Bridge | 5 | 1 | 1
Haswell | 5 | 1 | 1
Broadwell | 5 | 1 | 1
Skylake | 4 | 1 | 1
Knights Landing | 7 | 2 | 1
Ivy Bridge | 5 | 1 |
Haswell | 5 | 1 |
Broadwell | 5 | 1 |
Skylake | 4 | 1 |


_mm_rem_epi16

__m128i _mm_rem_epi16( __m128i a, __m128i b )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Arithmetic

Description

Divide packed 16-bit integers in "a" by packed elements in "b", and store the remainders as packed 32-bit integers in "dst".

Operation

FOR j := 0 to 7
    i := 16*j
    dst[i+15:i] := REMAINDER(a[i+15:i] / b[i+15:i])
ENDFOR
dst[MAX:128] := 0


_mm_rem_epi32

__m128i _mm_rem_epi32( __m128i a, __m128i b )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Arithmetic

Description

Divide packed 32-bit integers in "a" by packed elements in "b", and store the remainders as packed 32-bit integers in "dst".

Operation

FOR j := 0 to 3
    i := 32*j
    dst[i+31:i] := REMAINDER(a[i+31:i] / b[i+31:i])
ENDFOR
dst[MAX:128] := 0


_mm_rem_epi64

__m128i _mm_rem_epi64( __m128i a, __m128i b )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Arithmetic

Description

Divide packed 64-bit integers in "a" by packed elements in "b", and store the remainders as packed 32-bit integers in "dst".

Operation

FOR j := 0 to 1
    i := 64*j
    dst[i+63:i] := REMAINDER(a[i+63:i] / b[i+63:i])
ENDFOR
dst[MAX:128] := 0


_mm_rem_epi8

__m128i _mm_rem_epi8( __m128i a, __m128i b )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Arithmetic

Description

Divide packed 8-bit integers in "a" by packed elements in "b", and store the remainders as packed 32-bit integers in "dst".

Operation

FOR j := 0 to 15
    i := 8*j
    dst[i+7:i] := REMAINDER(a[i+7:i] / b[i+7:i])
ENDFOR
dst[MAX:128] := 0


_mm_rem_epu16

__m128i _mm_rem_epu16( __m128i a, __m128i b )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Arithmetic

Description

Divide packed unsigned 16-bit integers in "a" by packed elements in "b", and store the remainders as packed unsigned 32-bit integers in "dst".

Operation

FOR j := 0 to 7
    i := 16*j
    dst[i+15:i] := REMAINDER(a[i+15:i] / b[i+15:i])
ENDFOR
dst[MAX:128] := 0


_mm_rem_epu32

__m128i _mm_rem_epu32( __m128i a, __m128i b )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Arithmetic

Description

Divide packed unsigned 32-bit integers in "a" by packed elements in "b", and store the remainders as packed unsigned 32-bit integers in "dst".

Operation

FOR j := 0 to 3
    i := 32*j
    dst[i+31:i] := REMAINDER(a[i+31:i] / b[i+31:i])
ENDFOR
dst[MAX:128] := 0


_mm_rem_epu64

__m128i _mm_rem_epu64( __m128i a, __m128i b )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Arithmetic

Description

Divide packed unsigned 64-bit integers in "a" by packed elements in "b", and store the remainders as packed unsigned 32-bit integers in "dst".

Operation

FOR j := 0 to 1
    i := 64*j
    dst[i+63:i] := REMAINDER(a[i+63:i] / b[i+63:i])
ENDFOR
dst[MAX:128] := 0


_mm_rem_epu8

__m128i _mm_rem_epu8( __m128i a, __m128i b )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Arithmetic

Description

Divide packed unsigned 8-bit integers in "a" by packed elements in "b", and store the remainders as packed unsigned 32-bit integers in "dst".

Operation

FOR j := 0 to 15
    i := 8*j
    dst[i+7:i] := REMAINDER(a[i+7:i] / b[i+7:i])
ENDFOR
dst[MAX:128] := 0


_mm_round_pd

__m128d _mm_round_pd( __m128d a, int rounding )

Synopsis

#include "smmintrin.h"
Instruction: roundpd
CPUID Flag: SSE4.1
Category: Special Math Functions

Description

Round the packed double-precision (64-bit) floating-point elements in "a" using the "rounding" parameter, and store the results as packed double-precision floating-point elements in "dst". [round_note]

Operation

FOR j := 0 to 1
    i := j*64
    dst[i+63:i] := ROUND(a[i+63:i], rounding)
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 4 | 1 | 1
Jaguar | 4 | 1 | 1
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 6 | 2 | 2
Broadwell | 6 | 2 | 2
Skylake | 8 | 1 | 2
Knights Landing | 6 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 6 | 2 |
Broadwell | 6 | 2 |
Skylake | 6 | 2 |


_mm_round_ps

__m128 _mm_round_ps( __m128 a, int rounding )

Synopsis

#include "smmintrin.h"
Instruction: roundps
CPUID Flag: SSE4.1
Category: Special Math Functions

Description

Round the packed single-precision (32-bit) floating-point elements in "a" using the "rounding" parameter, and store the results as packed single-precision floating-point elements in "dst". [round_note]

Operation

FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := ROUND(a[i+31:i], rounding)
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 4 | 1 | 1
Jaguar | 4 | 1 | 1
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 6 | 2 | 2
Broadwell | 6 | 2 | 2
Skylake | 8 | 1 | 2
Knights Landing | 6 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 6 | 2 |
Broadwell | 6 | 2 |
Skylake | 6 | 2 |


_mm_round_sd

__m128d _mm_round_sd( __m128d a, __m128d b, int rounding )

Synopsis

#include "smmintrin.h"
Instruction: roundsd
CPUID Flag: SSE4.1
Category: Special Math Functions

Description

Round the lower double-precision (64-bit) floating-point element in "b" using the "rounding" parameter, store the result as a double-precision floating-point element in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". [round_note]

Operation

dst[63:0] := ROUND(b[63:0], rounding)
dst[127:64] := a[127:64]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 4 | 1 | 1
Jaguar | 4 | 1 | 1
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 6 | 2 | 2
Broadwell | 6 | 2 | 2
Skylake | 8 | 1 | 2
Knights Landing | 6 | 2 | 1
Ivy Bridge | 3 | 1 |
Haswell | 6 | 2 |
Broadwell | 6 | 2 |
Skylake | 6 | 2 |


_mm_round_ss

__m128 _mm_round_ss( __m128 a, __m128 b, int rounding )

Synopsis

#include "smmintrin.h"
Instruction: roundss
CPUID Flag: SSE4.1
Category: Special Math Functions

Description

Round the lower single-precision (32-bit) floating-point element in "b" using the "rounding" parameter, store the result as a single-precision floating-point element in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". [round_note]

Operation

dst[31:0] := ROUND(b[31:0], rounding)
dst[127:32] := a[127:32]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 4 | 1 | 1
Jaguar | 4 | 1 | 1
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 6 | 2 | 2
Broadwell | 6 | 2 | 2
Skylake | 8 | 1 | 2
Knights Landing | 6 | 2 | 1
Ivy Bridge | 3 | 1 |
Haswell | 6 | 2 |
Broadwell | 6 | 2 |
Skylake | 6 | 2 |


_mm_rsqrt_ps

__m128 _mm_rsqrt_ps( __m128 a )

Synopsis

#include "xmmintrin.h"
Instruction: rsqrtps
CPUID Flag: SSE
Category: Elementary Math Functions

Description

Compute the approximate reciprocal square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". The maximum relative error for this approximation is less than 1.5*2^-12.

Operation

FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := APPROXIMATE(1.0 / SQRT(a[i+31:i]))
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 5 | 1 | 1
Jaguar | 2 | 1 | 1
Sandy Bridge | 5 | 1 | 1
Ivy Bridge | 5 | 1 | 1
Haswell | 5 | 1 | 1
Broadwell | 5 | 1 | 1
Skylake | 4 | 1 | 1
Knights Landing | 8 | 3 | 1
Ivy Bridge | 5 | 1 |
Haswell | 5 | 1 |
Broadwell | 5 | 1 |
Skylake | 4 | 1 |


_mm_rsqrt_ss

__m128 _mm_rsqrt_ss( __m128 a )

Synopsis

#include "xmmintrin.h"
Instruction: rsqrtss
CPUID Flag: SSE
Category: Elementary Math Functions

Description

Compute the approximate reciprocal square root of the lower single-precision (32-bit) floating-point element in "a", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". The maximum relative error for this approximation is less than 1.5*2^-12.

Operation

dst[31:0] := APPROXIMATE(1.0 / SQRT(a[31:0]))
dst[127:32] := a[127:32]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 5 | 1 | 1
Jaguar | 2 | 1 | 1
Sandy Bridge | 5 | 1 | 1
Ivy Bridge | 5 | 1 | 1
Haswell | 5 | 1 | 1
Broadwell | 5 | 1 | 1
Skylake | 4 | 1 | 1
Knights Landing | 7 | 2 | 1
Ivy Bridge | 5 | 1 |
Haswell | 5 | 1 |
Broadwell | 5 | 1 |
Skylake | 4 | 1 |


_mm_sad_epu8

__m128i _mm_sad_epu8( __m128i a, __m128i b )

Synopsis

#include "emmintrin.h"
Instruction: psadbw
CPUID Flag: SSE2
Category: Arithmetic

Description

Compute the absolute differences of packed unsigned 8-bit integers in "a" and "b", then horizontally sum each consecutive 8 differences to produce two unsigned 16-bit integers, and pack these unsigned 16-bit integers in the low 16 bits of 64-bit elements in "dst".

Operation

FOR j := 0 to 15
    i := j*8
    tmp[i+7:i] := ABS(a[i+7:i] - b[i+7:i])
ENDFOR
FOR j := 0 to 1
    i := j*64
    dst[i+15:i] := tmp[i+7:i] + tmp[i+15:i+8] + tmp[i+23:i+16] + tmp[i+31:i+24] + \
                   tmp[i+39:i+32] + tmp[i+47:i+40] + tmp[i+55:i+48] + tmp[i+63:i+56]
    dst[i+63:i+16] := 0
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 1 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 5 | 1 | 1
Ivy Bridge | 5 | 1 | 1
Haswell | 5 | 1 | 1
Broadwell | 5 | 1 | 1
Skylake | 3 | 1 | 1
Knights Landing | 16 | 9 | 5
Ivy Bridge | 5 | 1 |
Haswell | 5 | 1 |
Broadwell | 5 | 1 |
Skylake | 3 | 1 |


_mm_sad_pu8

__m64 _mm_sad_pu8( __m64 a, __m64 b )

Synopsis

#include "xmmintrin.h"
Instruction: psadbw
CPUID Flag: SSE
Category: Arithmetic

Description

Compute the absolute differences of packed unsigned 8-bit integers in "a" and "b", then horizontally sum each consecutive 8 differences to produce four unsigned 16-bit integers, and pack these unsigned 16-bit integers in the low 16 bits of "dst".

Operation

FOR j := 0 to 7
    i := j*8
    tmp[i+7:i] := ABS(a[i+7:i] - b[i+7:i])
ENDFOR
dst[15:0] := tmp[7:0] + tmp[15:8] + tmp[23:16] + tmp[31:24] + tmp[39:32] + tmp[47:40] + tmp[55:48] + tmp[63:56]
dst[63:16] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 1 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 5 | 1 | 1
Ivy Bridge | 5 | 1 | 1
Haswell | 5 | 1 | 1
Broadwell | 5 | 1 | 1
Skylake | 3 | 1 | 1
Knights Landing | 16 | 9 | 5


_mm_set_epi16

__m128i _mm_set_epi16( short e7, short e6, short e5, short e4, short e3, short e2, short e1, short e0 )

Synopsis

#include "emmintrin.h"
Instruction: N/A
CPUID Flag: SSE2
Category: Set

Description

Set packed 16-bit integers in "dst" with the supplied values.

Operation

dst[15:0] := e0
dst[31:16] := e1
dst[47:32] := e2
dst[63:48] := e3
dst[79:64] := e4
dst[95:80] := e5
dst[111:96] := e6
dst[127:112] := e7


_mm_set_epi32

__m128i _mm_set_epi32( int e3, int e2, int e1, int e0 )

Synopsis

#include "emmintrin.h"
Instruction: N/A
CPUID Flag: SSE2
Category: Set

Description

Set packed 32-bit integers in "dst" with the supplied values.

Operation

dst[31:0] := e0
dst[63:32] := e1
dst[95:64] := e2
dst[127:96] := e3


_mm_set_epi64

__m128i _mm_set_epi64( __m64 e1, __m64 e0 )

Synopsis

#include "emmintrin.h"
Instruction: N/A
CPUID Flag: SSE2
Category: Set

Description

Set packed 64-bit integers in "dst" with the supplied values.

Operation

dst[63:0] := e0
dst[127:64] := e1


_mm_set_epi64x

__m128i _mm_set_epi64x( __int64 e1, __int64 e0 )

Synopsis

#include "emmintrin.h"
Instruction: N/A
CPUID Flag: SSE2
Category: Set

Description

Set packed 64-bit integers in "dst" with the supplied values.

Operation

dst[63:0] := e0
dst[127:64] := e1


_mm_set_epi8

__m128i _mm_set_epi8( char e15, char e14, char e13, char e12, char e11, char e10, char e9, char e8, char e7, char e6, char e5, char e4, char e3, char e2, char e1, char e0 )

Synopsis

#include "emmintrin.h"
Instruction: N/A
CPUID Flag: SSE2
Category: Set

Description

Set packed 8-bit integers in "dst" with the supplied values in reverse order.

Operation

dst[7:0] := e0
dst[15:8] := e1
dst[23:16] := e2
dst[31:24] := e3
dst[39:32] := e4
dst[47:40] := e5
dst[55:48] := e6
dst[63:56] := e7
dst[71:64] := e8
dst[79:72] := e9
dst[87:80] := e10
dst[95:88] := e11
dst[103:96] := e12
dst[111:104] := e13
dst[119:112] := e14
dst[127:120] := e15


_MM_SET_EXCEPTION_MASK

void _MM_SET_EXCEPTION_MASK( unsigned int a )

Synopsis

#include "xmmintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: General Support

Description

Macro: Set the exception mask bits of the MXCSR control and status register to the value in unsigned 32-bit integer "a". The exception mask may contain any of the following flags: _MM_MASK_INVALID, _MM_MASK_DIV_ZERO, _MM_MASK_DENORM, _MM_MASK_OVERFLOW, _MM_MASK_UNDERFLOW, _MM_MASK_INEXACT

Operation

MXCSR := a[31:0] AND ~_MM_MASK_MASK


_MM_SET_EXCEPTION_STATE

void _MM_SET_EXCEPTION_STATE( unsigned int a )

Synopsis

#include "xmmintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: General Support

Description

Macro: Set the exception state bits of the MXCSR control and status register to the value in unsigned 32-bit integer "a". The exception state may contain any of the following flags: _MM_EXCEPT_INVALID, _MM_EXCEPT_DIV_ZERO, _MM_EXCEPT_DENORM, _MM_EXCEPT_OVERFLOW, _MM_EXCEPT_UNDERFLOW, _MM_EXCEPT_INEXACT

Operation

MXCSR := a[31:0] AND ~_MM_EXCEPT_MASK


_MM_SET_FLUSH_ZERO_MODE

void _MM_SET_FLUSH_ZERO_MODE( unsigned int a )

Synopsis

#include "xmmintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: General Support

Description

Macro: Set the flush zero bits of the MXCSR control and status register to the value in unsigned 32-bit integer "a". The flush zero may contain any of the following flags: _MM_FLUSH_ZERO_ON or _MM_FLUSH_ZERO_OFF

Operation

MXCSR := a[31:0] AND ~_MM_FLUSH_MASK


_mm_set_pd

__m128d _mm_set_pd( double e1, double e0 )

Synopsis

#include "emmintrin.h"
Instruction: N/A
CPUID Flag: SSE2
Category: Set

Description

Set packed double-precision (64-bit) floating-point elements in "dst" with the supplied values.

Operation

dst[63:0] := e0
dst[127:64] := e1


_mm_set_pd1

__m128d _mm_set_pd1( double a )

Synopsis

#include "emmintrin.h"
Instruction: N/A
CPUID Flag: SSE2
Category: Set

Description

Broadcast double-precision (64-bit) floating-point value "a" to all elements of "dst".

Operation

FOR j := 0 to 1
    i := j*64
    dst[i+63:i] := a[63:0]
ENDFOR


_mm_set_pi16

__m64 _mm_set_pi16( short e3, short e2, short e1, short e0 )

Synopsis

#include "mmintrin.h"
Instruction: N/A
CPUID Flag: MMX
Category: Set

Description

Set packed 16-bit integers in "dst" with the supplied values.

Operation

dst[15:0] := e0
dst[31:16] := e1
dst[47:32] := e2
dst[63:48] := e3


_mm_set_pi32

__m64 _mm_set_pi32( int e1, int e0 )

Synopsis

#include "mmintrin.h"
Instruction: N/A
CPUID Flag: MMX
Category: Set

Description

Set packed 32-bit integers in "dst" with the supplied values.

Operation

dst[31:0] := e0
dst[63:32] := e1


_mm_set_pi8

__m64 _mm_set_pi8( char e7, char e6, char e5, char e4, char e3, char e2, char e1, char e0 )

Synopsis

#include "mmintrin.h"
Instruction: N/A
CPUID Flag: MMX
Category: Set

Description

Set packed 8-bit integers in "dst" with the supplied values in reverse order.

Operation

dst[7:0] := e0
dst[15:8] := e1
dst[23:16] := e2
dst[31:24] := e3
dst[39:32] := e4
dst[47:40] := e5
dst[55:48] := e6
dst[63:56] := e7


_mm_set_ps

__m128 _mm_set_ps( float e3, float e2, float e1, float e0 )

Synopsis

#include "xmmintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Set

Description

Set packed single-precision (32-bit) floating-point elements in "dst" with the supplied values.

Operation

dst[31:0] := e0
dst[63:32] := e1
dst[95:64] := e2
dst[127:96] := e3


_mm_set_ps1

__m128 _mm_set_ps1( float a )

Synopsis

#include "xmmintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Set

Description

Broadcast single-precision (32-bit) floating-point value "a" to all elements of "dst".

Operation

FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := a[31:0]
ENDFOR


_MM_SET_ROUNDING_MODE

void _MM_SET_ROUNDING_MODE( unsigned int a )

Synopsis

#include "xmmintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: General Support

Description

Macro: Set the rounding mode bits of the MXCSR control and status register to the value in unsigned 32-bit integer "a". The rounding mode may contain any of the following flags: _MM_ROUND_NEAREST, _MM_ROUND_DOWN, _MM_ROUND_UP, _MM_ROUND_TOWARD_ZERO

Operation

MXCSR := a[31:0] AND ~_MM_ROUND_MASK


_mm_set_sd

__m128d _mm_set_sd( double a )

Synopsis

#include "emmintrin.h"
Instruction: N/A
CPUID Flag: SSE2
Category: Set

Description

Copy double-precision (64-bit) floating-point element "a" to the lower element of "dst", and zero the upper element.

Operation

dst[63:0] := a[63:0]
dst[127:64] := 0


_mm_set_ss

__m128 _mm_set_ss( float a )

Synopsis

#include "xmmintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Set

Description

Copy single-precision (32-bit) floating-point element "a" to the lower element of "dst", and zero the upper 3 elements.

Operation

dst[31:0] := a[31:0]
dst[127:32] := 0


_mm_set1_epi16

__m128i _mm_set1_epi16( short a )

Synopsis

#include "emmintrin.h"
Instruction: N/A
CPUID Flag: SSE2
Category: Set

Description

Broadcast 16-bit integer "a" to all all elements of "dst". This intrinsic may generate "vpbroadcastw".

Operation

FOR j := 0 to 7
    i := j*16
    dst[i+15:i] := a[15:0]
ENDFOR


_mm_set1_epi32

__m128i _mm_set1_epi32( int a )

Synopsis

#include "emmintrin.h"
Instruction: N/A
CPUID Flag: SSE2
Category: Set

Description

Broadcast 32-bit integer "a" to all elements of "dst". This intrinsic may generate "vpbroadcastd".

Operation

FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := a[31:0]
ENDFOR


_mm_set1_epi64

__m128i _mm_set1_epi64( __m64 a )

Synopsis

#include "emmintrin.h"
Instruction: N/A
CPUID Flag: SSE2
Category: Set

Description

Broadcast 64-bit integer "a" to all elements of "dst".

Operation

FOR j := 0 to 1
    i := j*64
    dst[i+63:i] := a[63:0]
ENDFOR


_mm_set1_epi64x

__m128i _mm_set1_epi64x( __int64 a )

Synopsis

#include "emmintrin.h"
Instruction: N/A
CPUID Flag: SSE2
Category: Set

Description

Broadcast 64-bit integer "a" to all elements of "dst". This intrinsic may generate the "vpbroadcastq".

Operation

FOR j := 0 to 1
    i := j*64
    dst[i+63:i] := a[63:0]
ENDFOR


_mm_set1_epi8

__m128i _mm_set1_epi8( char a )

Synopsis

#include "emmintrin.h"
Instruction: N/A
CPUID Flag: SSE2
Category: Set

Description

Broadcast 8-bit integer "a" to all elements of "dst". This intrinsic may generate "vpbroadcastb".

Operation

FOR j := 0 to 15
    i := j*8
    dst[i+7:i] := a[7:0]
ENDFOR


_mm_set1_pd

__m128d _mm_set1_pd( double a )

Synopsis

#include "emmintrin.h"
Instruction: N/A
CPUID Flag: SSE2
Category: Set

Description

Broadcast double-precision (64-bit) floating-point value "a" to all elements of "dst".

Operation

FOR j := 0 to 1
    i := j*64
    dst[i+63:i] := a[63:0]
ENDFOR


_mm_set1_pi16

__m64 _mm_set1_pi16( short a )

Synopsis

#include "mmintrin.h"
Instruction: N/A
CPUID Flag: MMX
Category: Set

Description

Broadcast 16-bit integer "a" to all all elements of "dst".

Operation

FOR j := 0 to 3
    i := j*16
    dst[i+15:i] := a[15:0]
ENDFOR


_mm_set1_pi32

__m64 _mm_set1_pi32( int a )

Synopsis

#include "mmintrin.h"
Instruction: N/A
CPUID Flag: MMX
Category: Set

Description

Broadcast 32-bit integer "a" to all elements of "dst".

Operation

FOR j := 0 to 1
    i := j*32
    dst[i+31:i] := a[31:0]
ENDFOR


_mm_set1_pi8

__m64 _mm_set1_pi8( char a )

Synopsis

#include "mmintrin.h"
Instruction: N/A
CPUID Flag: MMX
Category: Set

Description

Broadcast 8-bit integer "a" to all elements of "dst".

Operation

FOR j := 0 to 7
    i := j*8
    dst[i+7:i] := a[7:0]
ENDFOR


_mm_set1_ps

__m128 _mm_set1_ps( float a )

Synopsis

#include "xmmintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Set

Description

Broadcast single-precision (32-bit) floating-point value "a" to all elements of "dst".

Operation

FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := a[31:0]
ENDFOR


_mm_setcsr

void _mm_setcsr( unsigned int a )

Synopsis

#include "xmmintrin.h"
Instruction: ldmxcsr
CPUID Flag: SSE
Category: General Support

Description

Set the MXCSR control and status register with the value in unsigned 32-bit integer "a".

Operation

MXCSR := a[31:0]

Performance

Architecture | Latency | Throughput | μops
Ryzen |  | 16 | 1
Jaguar | 9 | 8 | 12
Sandy Bridge |  | 3 | 3
Ivy Bridge | 6 | 3 | 3
Haswell | 6 | 3 | 3
Broadwell | 6 | 3 | 3
Skylake | 5 | 3 | 4
Knights Landing |  | 21 | 6


_mm_setr_epi16

__m128i _mm_setr_epi16( short e7, short e6, short e5, short e4, short e3, short e2, short e1, short e0 )

Synopsis

#include "emmintrin.h"
Instruction: N/A
CPUID Flag: SSE2
Category: Set

Description

Set packed 16-bit integers in "dst" with the supplied values in reverse order.

Operation

dst[15:0] := e7
dst[31:16] := e6
dst[47:32] := e5
dst[63:48] := e4
dst[79:64] := e3
dst[95:80] := e2
dst[111:96] := e1
dst[127:112] := e0


_mm_setr_epi32

__m128i _mm_setr_epi32( int e3, int e2, int e1, int e0 )

Synopsis

#include "emmintrin.h"
Instruction: N/A
CPUID Flag: SSE2
Category: Set

Description

Set packed 32-bit integers in "dst" with the supplied values in reverse order.

Operation

dst[31:0] := e3
dst[63:32] := e2
dst[95:64] := e1
dst[127:96] := e0


_mm_setr_epi64

__m128i _mm_setr_epi64( __m64 e1, __m64 e0 )

Synopsis

#include "emmintrin.h"
Instruction: N/A
CPUID Flag: SSE2
Category: Set

Description

Set packed 64-bit integers in "dst" with the supplied values in reverse order.

Operation

dst[63:0] := e1
dst[127:64] := e0


_mm_setr_epi8

__m128i _mm_setr_epi8( char e15, char e14, char e13, char e12, char e11, char e10, char e9, char e8, char e7, char e6, char e5, char e4, char e3, char e2, char e1, char e0 )

Synopsis

#include "emmintrin.h"
Instruction: N/A
CPUID Flag: SSE2
Category: Set

Description

Set packed 8-bit integers in "dst" with the supplied values in reverse order.

Operation

dst[7:0] := e15
dst[15:8] := e14
dst[23:16] := e13
dst[31:24] := e12
dst[39:32] := e11
dst[47:40] := e10
dst[55:48] := e9
dst[63:56] := e8
dst[71:64] := e7
dst[79:72] := e6
dst[87:80] := e5
dst[95:88] := e4
dst[103:96] := e3
dst[111:104] := e2
dst[119:112] := e1
dst[127:120] := e0


_mm_setr_pd

__m128d _mm_setr_pd( double e1, double e0 )

Synopsis

#include "emmintrin.h"
Instruction: N/A
CPUID Flag: SSE2
Category: Set

Description

Set packed double-precision (64-bit) floating-point elements in "dst" with the supplied values in reverse order.

Operation

dst[63:0] := e1
dst[127:64] := e0


_mm_setr_pi16

__m64 _mm_setr_pi16( short e3, short e2, short e1, short e0 )

Synopsis

#include "mmintrin.h"
Instruction: N/A
CPUID Flag: MMX
Category: Set

Description

Set packed 16-bit integers in "dst" with the supplied values in reverse order.

Operation

dst[15:0] := e3
dst[31:16] := e2
dst[47:32] := e1
dst[63:48] := e0


_mm_setr_pi32

__m64 _mm_setr_pi32( int e1, int e0 )

Synopsis

#include "mmintrin.h"
Instruction: N/A
CPUID Flag: MMX
Category: Set

Description

Set packed 32-bit integers in "dst" with the supplied values in reverse order.

Operation

dst[31:0] := e1
dst[63:32] := e0


_mm_setr_pi8

__m64 _mm_setr_pi8( char e7, char e6, char e5, char e4, char e3, char e2, char e1, char e0 )

Synopsis

#include "mmintrin.h"
Instruction: N/A
CPUID Flag: MMX
Category: Set

Description

Set packed 8-bit integers in "dst" with the supplied values in reverse order.

Operation

dst[7:0] := e7
dst[15:8] := e6
dst[23:16] := e5
dst[31:24] := e4
dst[39:32] := e3
dst[47:40] := e2
dst[55:48] := e1
dst[63:56] := e0


_mm_setr_ps

__m128 _mm_setr_ps( float e3, float e2, float e1, float e0 )

Synopsis

#include "xmmintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Set

Description

Set packed single-precision (32-bit) floating-point elements in "dst" with the supplied values in reverse order.

Operation

dst[31:0] := e3
dst[63:32] := e2
dst[95:64] := e1
dst[127:96] := e0


_mm_setzero_pd

__m128d _mm_setzero_pd( void )

Synopsis

#include "emmintrin.h"
Instruction: xorpd
CPUID Flag: SSE2
Category: Set

Description

Return vector of type __m128d with all elements set to zero.

Operation

dst[MAX:0] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.25 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 1 | 1
Ivy Bridge | 1 | 1 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 0.33 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 1 | 1 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 0.33 |


_mm_setzero_ps

__m128 _mm_setzero_ps( void )

Synopsis

#include "xmmintrin.h"
Instruction: xorps
CPUID Flag: SSE
Category: Set

Description

Return vector of type __m128 with all elements set to zero.

Operation

dst[MAX:0] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.25 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 1 | 1
Ivy Bridge | 1 | 1 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 0.33 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 1 | 1 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm_setzero_si128

__m128i _mm_setzero_si128()

Synopsis

#include "emmintrin.h"
Instruction: pxor
CPUID Flag: SSE2
Category: Set

Description

Return vector of type __m128i with all elements set to zero.

Operation

dst[MAX:0] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.25 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 |  | 1
Ivy Bridge | 1 | 0.33 | 1
Haswell | 1 | 0.33 | 1
Broadwell | 1 | 0.33 | 1
Skylake | 1 | 0.33 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 1 | 0.33 |
Haswell | 1 | 0.33 |
Broadwell | 1 | 0.33 |
Skylake | 1 | 0.33 |


_mm_setzero_si64

__m64 _mm_setzero_si64( void )

Synopsis

#include "mmintrin.h"
Instruction: pxor
CPUID Flag: MMX
Category: Set

Description

Return vector of type __m64 with all elements set to zero.

Operation

dst[MAX:0] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.25 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 |  | 1
Ivy Bridge | 1 | 0.33 | 1
Haswell | 1 | 0.33 | 1
Broadwell | 1 | 0.33 | 1
Skylake | 1 | 0.33 | 1
Knights Landing | 2 | 0.5 | 1


_mm_sfence

void _mm_sfence( void )

Synopsis

#include "xmmintrin.h"
Instruction: sfence
CPUID Flag: SSE
Category: General Support

Description

Perform a serializing operation on all store-to-memory instructions that were issued prior to this instruction. Guarantees that every store instruction that precedes, in program order, is globally visible before any store instruction which follows the fence in program order.

Performance

Architecture | Latency | Throughput | μops
Ivy Bridge |  | 5 |
Haswell |  | 6 |
Broadwell |  | 6 |
Skylake |  | 7 |


_mm_sha1msg1_epu32

__m128i _mm_sha1msg1_epu32( __m128i a, __m128i b )

Synopsis

#include "immintrin.h"
Instruction: sha1msg1
CPUID Flag: SHA
Category: Cryptography

Description

Perform an intermediate calculation for the next four SHA1 message values (unsigned 32-bit integers) using previous message values from "a" and "b", and store the result in "dst".

Operation

W0 := a[127:96]
W1 := a[95:64]
W2 := a[63:32]
W3 := a[31:0]
W4 := b[127:96]
W5 := b[95:64]
dst[127:96] := W2 XOR W0
dst[95:64] := W3 XOR W1
dst[63:32] := W4 XOR W2
dst[31:0] := W5 XOR W3

Performance

Architecture | Latency | Throughput | μops
Ryzen | 2 | 1 | 2


_mm_sha1msg2_epu32

__m128i _mm_sha1msg2_epu32( __m128i a, __m128i b )

Synopsis

#include "immintrin.h"
Instruction: sha1msg2
CPUID Flag: SHA
Category: Cryptography

Description

Perform the final calculation for the next four SHA1 message values (unsigned 32-bit integers) using the intermediate result in "a" and the previous message values in "b", and store the result in "dst".

Operation

W13 := b[95:64]
W14 := b[63:32]
W15 := b[31:0]
W16 := (a[127:96] XOR W13) <<< 1
W17 := (a[95:64] XOR W14) <<< 1
W18 := (a[63:32] XOR W15) <<< 1
W19 := (a[31:0] XOR W16) <<< 1
dst[127:96] := W16
dst[95:64] := W17
dst[63:32] := W18
dst[31:0] := W19

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1


_mm_sha1nexte_epu32

__m128i _mm_sha1nexte_epu32( __m128i a, __m128i b )

Synopsis

#include "immintrin.h"
Instruction: sha1nexte
CPUID Flag: SHA
Category: Cryptography

Description

Calculate SHA1 state variable E after four rounds of operation from the current SHA1 state variable "a", add that value to the scheduled values (unsigned 32-bit integers) in "b", and store the result in "dst".

Operation

tmp := (a[127:96] <<< 30)
dst[127:96] := b[127:96] + tmp
dst[95:64] := b[95:64]
dst[63:32] := b[63:32]
dst[31:0] := b[31:0]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 1 | 1


_mm_sha1rnds4_epu32

__m128i _mm_sha1rnds4_epu32( __m128i a, __m128i b, const int func )

Synopsis

#include "immintrin.h"
Instruction: sha1rnds4
CPUID Flag: SHA
Category: Cryptography

Description

Perform four rounds of SHA1 operation using an initial SHA1 state (A,B,C,D) from "a" and some pre-computed sum of the next 4 round message values (unsigned 32-bit integers), and state variable E from "b", and store the updated SHA1 state (A,B,C,D) in "dst". "func" contains the logic functions and round constants.

Operation

IF (func[1:0] == 0)
    f := f0()
    K := K0
ELSE IF (func[1:0] == 1)
    f := f1()
    K := K1
ELSE IF (func[1:0] == 2)
    f := f2()
    K := K2
ELSE IF (func[1:0] == 3)
    f := f3()
    K := K3
FI
A := a[127:96]
B := a[95:64]
C := a[63:32]
D := a[31:0]
W[0] := b[127:96]
W[1] := b[95:64]
W[2] := b[63:32]
W[3] := b[31:0]
A[1] := f(B, C, D) + (A <<< 5) + W[0] + K
B[1] := A
C[1] := B <<< 30
D[1] := C
E[1] := D
FOR i := 1 to 3
    A[i+1] := f(B[i], C[i], D[i]) + (A[i] <<< 5) + W[i] + E[i] + K
    B[i+1] := A[i]
    C[i+1] := B[i] <<< 30
    D[i+1] := C[i]
    E[i+1] := D[i]
ENDFOR
dst[127:96] := A[4]
dst[95:64] := B[4]
dst[63:32] := C[4]
dst[31:0] := D[4]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 6 | 4 | 1


_mm_sha256msg1_epu32

__m128i _mm_sha256msg1_epu32( __m128i a, __m128i b )

Synopsis

#include "immintrin.h"
Instruction: sha256msg1
CPUID Flag: SHA
Category: Cryptography

Description

Perform an intermediate calculation for the next four SHA256 message values (unsigned 32-bit integers) using previous message values from "a" and "b", and store the result in "dst".

Operation

W4 := b[31:0]
W3 := a[127:96]
W2 := a[95:64]
W1 := a[63:32]
W0 := a[31:0]
dst[127:96] := W3 + sigma0(W4)
dst[95:64] := W2 + sigma0(W3)
dst[63:32] := W1 + sigma0(W2)
dst[31:0] := W0 + sigma0(W1)

Performance

Architecture | Latency | Throughput | μops
Ryzen | 2 | 0.5 | 2


_mm_sha256msg2_epu32

__m128i _mm_sha256msg2_epu32( __m128i a, __m128i b )

Synopsis

#include "immintrin.h"
Instruction: sha256msg2
CPUID Flag: SHA
Category: Cryptography

Description

Perform the final calculation for the next four SHA256 message values (unsigned 32-bit integers) using previous message values from "a" and "b", and store the result in "dst"."

Operation

W14 := b[95:64]
W15 := b[127:96]
W16 := a[31:0] + sigma1(W14)
W17 := a[63:32] + sigma1(W15)
W18 := a[95:64] + sigma1(W16)
W19 := a[127:96] + sigma1(W17)
dst[127:96] := W19
dst[95:64] := W18
dst[63:32] := W17
dst[31:0] := W16

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 2 | 4


_mm_sha256rnds2_epu32

__m128i _mm_sha256rnds2_epu32( __m128i a, __m128i b, __m128i k )

Synopsis

#include "immintrin.h"
Instruction: sha256rnds2
CPUID Flag: SHA
Category: Cryptography

Description

Perform 2 rounds of SHA256 operation using an initial SHA256 state (C,D,G,H) from "a", an initial SHA256 state (A,B,E,F) from "b", and a pre-computed sum of the next 2 round message values (unsigned 32-bit integers) and the corresponding round constants from "k", and store the updated SHA256 state (A,B,E,F) in "dst".

Operation

A[0] := b[127:96]
B[0] := b[95:64]
C[0] := a[127:96]
D[0] := a[95:64]
E[0] := b[63:32]
F[0] := b[31:0]
G[0] := a[63:32]
H[0] := a[31:0]
W_K[0] := k[31:0]
W_K[1] := k[63:32]
FOR i := 0 to 1
    A[i+1] := Ch(E[i], F[i], G[i]) + sum1(E[i]) + W_K[i] + H[i] + Maj(A[i], B[i], C[i]) + sum0(A[i])
    B[i+1] := A[i]
    C[i+1] := B[i]
    D[i+1] := C[i]
    E[i+1] := Ch(E[i], F[i], G[i]) + sum1(E[i]) + W_K[i] + H[i] + D[i]
    F[i+1] := E[i]
    G[i+1] := F[i]
    H[i+1] := G[i]
ENDFOR
dst[127:96] := A[2]
dst[95:64] := B[2]
dst[63:32] := E[2]
dst[31:0] := F[2]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 4 | 2 | 1


_mm_shuffle_epi32

__m128i _mm_shuffle_epi32( __m128i a, int imm8 )

Synopsis

#include "emmintrin.h"
Instruction: pshufd
CPUID Flag: SSE2
Category: Swizzle

Description

Shuffle 32-bit integers in "a" using the control in "imm8", and store the results in "dst".

Operation

DEFINE SELECT4(src, control) {
    CASE(control[1:0]) OF
    0:	tmp[31:0] := src[31:0]
    1:	tmp[31:0] := src[63:32]
    2:	tmp[31:0] := src[95:64]
    3:	tmp[31:0] := src[127:96]
    ESAC
    RETURN tmp[31:0]
}
dst[31:0] := SELECT4(a[127:0], imm8[1:0])
dst[63:32] := SELECT4(a[127:0], imm8[3:2])
dst[95:64] := SELECT4(a[127:0], imm8[5:4])
dst[127:96] := SELECT4(a[127:0], imm8[7:6])

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 3-6 | 1 | 1
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm_shuffle_epi8

__m128i _mm_shuffle_epi8( __m128i a, __m128i b )

Synopsis

#include "tmmintrin.h"
Instruction: pshufb
CPUID Flag: SSSE3
Category: Swizzle

Description

Shuffle packed 8-bit integers in "a" according to shuffle control mask in the corresponding 8-bit element of "b", and store the results in "dst".

Operation

FOR j := 0 to 15
    i := j*8
    IF b[i+7] == 1
        dst[i+7:i] := 0
    ELSE
        index[3:0] := b[i+3:i]
        dst[i+7:i] := a[index*8+7:index*8]
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 4 | 2 | 3
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 11-13 | 10 | 5
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm_shuffle_pd

__m128d _mm_shuffle_pd( __m128d a, __m128d b, int imm8 )

Synopsis

#include "emmintrin.h"
Instruction: shufpd
CPUID Flag: SSE2
Category: Swizzle

Description

Shuffle double-precision (64-bit) floating-point elements using the control in "imm8", and store the results in "dst".

Operation

dst[63:0] := (imm8[0] == 0) ? a[63:0] : a[127:64]
dst[127:64] := (imm8[1] == 0) ? b[63:0] : b[127:64]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 1 | 1 | 1
Ivy Bridge | 1 | 1 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 4 | 2 | 1
Ivy Bridge | 1 | 1 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm_shuffle_pi16

__m64 _mm_shuffle_pi16( __m64 a, int imm8 )

Synopsis

#include "xmmintrin.h"
Instruction: pshufw
CPUID Flag: SSE
Category: Swizzle

Description

Shuffle 16-bit integers in "a" using the control in "imm8", and store the results in "dst".

Operation

DEFINE SELECT4(src, control) {
    CASE(control[1:0]) OF
    0:	tmp[15:0] := src[15:0]
    1:	tmp[15:0] := src[31:16]
    2:	tmp[15:0] := src[47:32]
    3:	tmp[15:0] := src[63:48]
    ESAC
    RETURN tmp[15:0]
}
dst[15:0] := SELECT4(a[63:0], imm8[1:0])
dst[31:16] := SELECT4(a[63:0], imm8[3:2])
dst[47:32] := SELECT4(a[63:0], imm8[5:4])
dst[63:48] := SELECT4(a[63:0], imm8[7:6])

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 2-6 | 1 | 1


_mm_shuffle_pi8

__m64 _mm_shuffle_pi8( __m64 a, __m64 b )

Synopsis

#include "tmmintrin.h"
Instruction: pshufb
CPUID Flag: SSSE3
Category: Swizzle

Description

Shuffle packed 8-bit integers in "a" according to shuffle control mask in the corresponding 8-bit element of "b", and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*8
    IF b[i+7] == 1
        dst[i+7:i] := 0
    ELSE
        index[2:0] := b[i+2:i]
        dst[i+7:i] := a[index*8+7:index*8]
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 4 | 2 | 3
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 11-13 | 10 | 5
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm_shuffle_ps

__m128 _mm_shuffle_ps( __m128 a, __m128 b, unsigned int imm8 )

Synopsis

#include "xmmintrin.h"
Instruction: shufps
CPUID Flag: SSE
Category: Swizzle

Description

Shuffle single-precision (32-bit) floating-point elements in "a" using the control in "imm8", and store the results in "dst".

Operation

DEFINE SELECT4(src, control) {
    CASE(control[1:0]) OF
    0:	tmp[31:0] := src[31:0]
    1:	tmp[31:0] := src[63:32]
    2:	tmp[31:0] := src[95:64]
    3:	tmp[31:0] := src[127:96]
    ESAC
    RETURN tmp[31:0]
}
dst[31:0] := SELECT4(a[127:0], imm8[1:0])
dst[63:32] := SELECT4(a[127:0], imm8[3:2])
dst[95:64] := SELECT4(b[127:0], imm8[5:4])
dst[127:96] := SELECT4(b[127:0], imm8[7:6])

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 1 | 1 | 1
Ivy Bridge | 1 | 1 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 4 | 2 | 1
Ivy Bridge | 1 | 1 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm_shufflehi_epi16

__m128i _mm_shufflehi_epi16( __m128i a, int imm8 )

Synopsis

#include "emmintrin.h"
Instruction: pshufhw
CPUID Flag: SSE2
Category: Swizzle

Description

Shuffle 16-bit integers in the high 64 bits of "a" using the control in "imm8". Store the results in the high 64 bits of "dst", with the low 64 bits being copied from from "a" to "dst".

Operation

dst[63:0] := a[63:0]
dst[79:64] := (a >> (imm8[1:0] * 16))[79:64]
dst[95:80] := (a >> (imm8[3:2] * 16))[79:64]
dst[111:96] := (a >> (imm8[5:4] * 16))[79:64]
dst[127:112] := (a >> (imm8[7:6] * 16))[79:64]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 2-6 | 1 | 1
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm_shufflelo_epi16

__m128i _mm_shufflelo_epi16( __m128i a, int imm8 )

Synopsis

#include "emmintrin.h"
Instruction: pshuflw
CPUID Flag: SSE2
Category: Swizzle

Description

Shuffle 16-bit integers in the low 64 bits of "a" using the control in "imm8". Store the results in the low 64 bits of "dst", with the high 64 bits being copied from from "a" to "dst".

Operation

dst[15:0] := (a >> (imm8[1:0] * 16))[15:0]
dst[31:16] := (a >> (imm8[3:2] * 16))[15:0]
dst[47:32] := (a >> (imm8[5:4] * 16))[15:0]
dst[63:48] := (a >> (imm8[7:6] * 16))[15:0]
dst[127:64] := a[127:64]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 2-6 | 1 | 1
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm_sign_epi16

__m128i _mm_sign_epi16( __m128i a, __m128i b )

Synopsis

#include "tmmintrin.h"
Instruction: psignw
CPUID Flag: SSSE3
Category: Arithmetic

Description

Negate packed 16-bit integers in "a" when the corresponding signed 16-bit integer in "b" is negative, and store the results in "dst". Element in "dst" are zeroed out when the corresponding element in "b" is zero.

Operation

FOR j := 0 to 7
    i := j*16
    IF b[i+15:i] < 0
        dst[i+15:i] := -(a[i+15:i])
    ELSE IF b[i+15:i] == 0
        dst[i+15:i] := 0
    ELSE
        dst[i+15:i] := a[i+15:i]
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.5 | 1
Knights Landing | 2 | 2 | 1
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.5 |


_mm_sign_epi32

__m128i _mm_sign_epi32( __m128i a, __m128i b )

Synopsis

#include "tmmintrin.h"
Instruction: psignd
CPUID Flag: SSSE3
Category: Arithmetic

Description

Negate packed 32-bit integers in "a" when the corresponding signed 32-bit integer in "b" is negative, and store the results in "dst". Element in "dst" are zeroed out when the corresponding element in "b" is zero.

Operation

FOR j := 0 to 3
    i := j*32
    IF b[i+31:i] < 0
        dst[i+31:i] := -(a[i+31:i])
    ELSE IF b[i+31:i] == 0
        dst[i+31:i] := 0
    ELSE
        dst[i+31:i] := a[i+31:i]
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.5 | 1
Knights Landing | 2 | 2 | 1
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.5 |


_mm_sign_epi8

__m128i _mm_sign_epi8( __m128i a, __m128i b )

Synopsis

#include "tmmintrin.h"
Instruction: psignb
CPUID Flag: SSSE3
Category: Arithmetic

Description

Negate packed 8-bit integers in "a" when the corresponding signed 8-bit integer in "b" is negative, and store the results in "dst". Element in "dst" are zeroed out when the corresponding element in "b" is zero.

Operation

FOR j := 0 to 15
    i := j*8
    IF b[i+7:i] < 0
        dst[i+7:i] := -(a[i+7:i])
    ELSE IF b[i+7:i] == 0
        dst[i+7:i] := 0
    ELSE
        dst[i+7:i] := a[i+7:i]
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.5 | 1
Knights Landing | 2 | 2 | 1
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.5 |


_mm_sign_pi16

__m64 _mm_sign_pi16( __m64 a, __m64 b )

Synopsis

#include "tmmintrin.h"
Instruction: psignw
CPUID Flag: SSSE3
Category: Arithmetic

Description

Negate packed 16-bit integers in "a" when the corresponding signed 16-bit integer in "b" is negative, and store the results in "dst". Element in "dst" are zeroed out when the corresponding element in "b" is zero.

Operation

FOR j := 0 to 3
    i := j*16
    IF b[i+15:i] < 0
        dst[i+15:i] := -(a[i+15:i])
    ELSE IF b[i+15:i] == 0
        dst[i+15:i] := 0
    ELSE
        dst[i+15:i] := a[i+15:i]
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.5 | 1
Knights Landing | 2 | 2 | 1
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.5 |


_mm_sign_pi32

__m64 _mm_sign_pi32( __m64 a, __m64 b )

Synopsis

#include "tmmintrin.h"
Instruction: psignd
CPUID Flag: SSSE3
Category: Arithmetic

Description

Negate packed 32-bit integers in "a" when the corresponding signed 32-bit integer in "b" is negative, and store the results in "dst". Element in "dst" are zeroed out when the corresponding element in "b" is zero.

Operation

FOR j := 0 to 1
    i := j*32
    IF b[i+31:i] < 0
        dst[i+31:i] := -(a[i+31:i])
    ELSE IF b[i+31:i] == 0
        dst[i+31:i] := 0
    ELSE
        dst[i+31:i] := a[i+31:i]
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.5 | 1
Knights Landing | 2 | 2 | 1
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.5 |


_mm_sign_pi8

__m64 _mm_sign_pi8( __m64 a, __m64 b )

Synopsis

#include "tmmintrin.h"
Instruction: psignb
CPUID Flag: SSSE3
Category: Arithmetic

Description

Negate packed 8-bit integers in "a" when the corresponding signed 8-bit integer in "b" is negative, and store the results in "dst". Element in "dst" are zeroed out when the corresponding element in "b" is zero.

Operation

FOR j := 0 to 7
    i := j*8
    IF b[i+7:i] < 0
        dst[i+7:i] := -(a[i+7:i])
    ELSE IF b[i+7:i] == 0
        dst[i+7:i] := 0
    ELSE
        dst[i+7:i] := a[i+7:i]
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.5 | 1
Knights Landing | 2 | 2 | 1
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.5 |


_mm_sin_pd

__m128d _mm_sin_pd( __m128d a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Trigonometry

Description

Compute the sine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*64
    dst[i+63:i] := SIN(a[i+63:i])
ENDFOR
dst[MAX:128] := 0


_mm_sin_ps

__m128 _mm_sin_ps( __m128 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Trigonometry

Description

Compute the sine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := SIN(a[i+31:i])
ENDFOR
dst[MAX:128] := 0


_mm_sincos_pd

__m128d _mm_sincos_pd( __m128d * mem_addr, __m128d a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Trigonometry

Description

Compute the sine and cosine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, store the sine in "dst", and store the cosine into memory at "mem_addr".

Operation

FOR j := 0 to 1
    i := j*64
    dst[i+63:i] := SIN(a[i+63:i])
    MEM[mem_addr+i+63:mem_addr+i] := COS(a[i+63:i])
ENDFOR
dst[MAX:128] := 0


_mm_sincos_ps

__m128 _mm_sincos_ps( __m128 * mem_addr, __m128 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Trigonometry

Description

Compute the sine and cosine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, store the sine in "dst", and store the cosine into memory at "mem_addr".

Operation

FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := SIN(a[i+31:i])
    MEM[mem_addr+i+31:mem_addr+i] := COS(a[i+31:i])
ENDFOR
dst[MAX:128] := 0


_mm_sind_pd

__m128d _mm_sind_pd( __m128d a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Trigonometry

Description

Compute the sine of packed double-precision (64-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*64
    dst[i+63:i] := SIND(a[i+63:i])
ENDFOR
dst[MAX:128] := 0


_mm_sind_ps

__m128 _mm_sind_ps( __m128 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Trigonometry

Description

Compute the sine of packed single-precision (32-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := SIND(a[i+31:i])
ENDFOR
dst[MAX:128] := 0


_mm_sinh_pd

__m128d _mm_sinh_pd( __m128d a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Trigonometry

Description

Compute the hyperbolic sine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*64
    dst[i+63:i] := SINH(a[i+63:i])
ENDFOR
dst[MAX:128] := 0


_mm_sinh_ps

__m128 _mm_sinh_ps( __m128 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Trigonometry

Description

Compute the hyperbolic sine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := SINH(a[i+31:i])
ENDFOR
dst[MAX:128] := 0


_mm_sll_epi16

__m128i _mm_sll_epi16( __m128i a, __m128i count )

Synopsis

#include "emmintrin.h"
Instruction: psllw
CPUID Flag: SSE2
Category: Shift

Description

Shift packed 16-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*16
    IF count[63:0] > 15
        dst[i+15:i] := 0
    ELSE
        dst[i+15:i] := ZeroExtend(a[i+15:i] << count[63:0])
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 1 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 2 | 1 | 2
Ivy Bridge | 2 | 1 | 2
Haswell | 2 | 1 | 2
Broadwell | 2 | 1 | 2
Skylake | 1 | 1 | 2
Knights Landing | 13 | 13 | 2
Ivy Bridge | 1 | 1 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm_sll_epi32

__m128i _mm_sll_epi32( __m128i a, __m128i count )

Synopsis

#include "emmintrin.h"
Instruction: pslld
CPUID Flag: SSE2
Category: Shift

Description

Shift packed 32-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    IF count[63:0] > 31
        dst[i+31:i] := 0
    ELSE
        dst[i+31:i] := ZeroExtend(a[i+31:i] << count[63:0])
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 1 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 2 | 1 | 2
Ivy Bridge | 2 | 1 | 2
Haswell | 2 | 1 | 2
Broadwell | 2 | 1 | 2
Skylake | 1 | 1 | 2
Knights Landing | 13 | 13 | 2
Ivy Bridge | 1 | 1 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm_sll_epi64

__m128i _mm_sll_epi64( __m128i a, __m128i count )

Synopsis

#include "emmintrin.h"
Instruction: psllq
CPUID Flag: SSE2
Category: Shift

Description

Shift packed 64-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*64
    IF count[63:0] > 63
        dst[i+63:i] := 0
    ELSE
        dst[i+63:i] := ZeroExtend(a[i+63:i] << count[63:0])
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 1 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 2 | 1 | 2
Ivy Bridge | 2 | 1 | 2
Haswell | 2 | 1 | 2
Broadwell | 2 | 1 | 2
Skylake | 1 | 1 | 2
Knights Landing | 13 | 13 | 2
Ivy Bridge | 1 | 1 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm_sll_pi16

__m64 _mm_sll_pi16( __m64 a, __m64 count )

Synopsis

#include "mmintrin.h"
Instruction: psllw
CPUID Flag: MMX
Category: Shift

Description

Shift packed 16-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*16
    IF count[63:0] > 15
        dst[i+15:i] := 0
    ELSE
        dst[i+15:i] := ZeroExtend(a[i+15:i] << count[63:0])
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 1 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 2 | 1 | 2
Ivy Bridge | 2 | 1 | 2
Haswell | 2 | 1 | 2
Broadwell | 2 | 1 | 2
Skylake | 1 | 1 | 2
Knights Landing | 13 | 13 | 2


_mm_sll_pi32

__m64 _mm_sll_pi32( __m64 a, __m64 count )

Synopsis

#include "mmintrin.h"
Instruction: pslld
CPUID Flag: MMX
Category: Shift

Description

Shift packed 32-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*32
    IF count[63:0] > 31
        dst[i+31:i] := 0
    ELSE
        dst[i+31:i] := ZeroExtend(a[i+31:i] << count[63:0])
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 1 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 2 | 1 | 2
Ivy Bridge | 2 | 1 | 2
Haswell | 2 | 1 | 2
Broadwell | 2 | 1 | 2
Skylake | 1 | 1 | 2
Knights Landing | 13 | 13 | 2


_mm_sll_si64

__m64 _mm_sll_si64( __m64 a, __m64 count )

Synopsis

#include "mmintrin.h"
Instruction: psllq
CPUID Flag: MMX
Category: Shift

Description

Shift 64-bit integer "a" left by "count" while shifting in zeros, and store the result in "dst".

Operation

IF count[63:0] > 63
    dst[63:0] := 0
ELSE
    dst[63:0] := ZeroExtend(a[63:0] << count[63:0])
FI

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 1 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 2 | 1 | 2
Ivy Bridge | 2 | 1 | 2
Haswell | 2 | 1 | 2
Broadwell | 2 | 1 | 2
Skylake | 1 | 1 | 2
Knights Landing | 13 | 13 | 2


_mm_slli_epi16

__m128i _mm_slli_epi16( __m128i a, int imm8 )

Synopsis

#include "emmintrin.h"
Instruction: psllw
CPUID Flag: SSE2
Category: Shift

Description

Shift packed 16-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*16
    IF imm8[7:0] > 15
        dst[i+15:i] := 0
    ELSE
        dst[i+15:i] := ZeroExtend(a[i+15:i] << imm8[7:0])
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 1 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 2 | 1 | 2
Ivy Bridge | 2 | 1 | 2
Haswell | 2 | 1 | 2
Broadwell | 2 | 1 | 2
Skylake | 1 | 1 | 2
Knights Landing | 13 | 13 | 2
Ivy Bridge | 1 | 1 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm_slli_epi32

__m128i _mm_slli_epi32( __m128i a, int imm8 )

Synopsis

#include "emmintrin.h"
Instruction: pslld
CPUID Flag: SSE2
Category: Shift

Description

Shift packed 32-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    IF imm8[7:0] > 31
        dst[i+31:i] := 0
    ELSE
        dst[i+31:i] := ZeroExtend(a[i+31:i] << imm8[7:0])
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 1 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 2 | 1 | 2
Ivy Bridge | 2 | 1 | 2
Haswell | 2 | 1 | 2
Broadwell | 2 | 1 | 2
Skylake | 1 | 1 | 2
Knights Landing | 13 | 13 | 2
Ivy Bridge | 1 | 1 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm_slli_epi64

__m128i _mm_slli_epi64( __m128i a, int imm8 )

Synopsis

#include "emmintrin.h"
Instruction: psllq
CPUID Flag: SSE2
Category: Shift

Description

Shift packed 64-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*64
    IF imm8[7:0] > 63
        dst[i+63:i] := 0
    ELSE
        dst[i+63:i] := ZeroExtend(a[i+63:i] << imm8[7:0])
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 1 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 2 | 1 | 2
Ivy Bridge | 2 | 1 | 2
Haswell | 2 | 1 | 2
Broadwell | 2 | 1 | 2
Skylake | 1 | 1 | 2
Knights Landing | 13 | 13 | 2
Ivy Bridge | 1 | 1 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm_slli_pi16

__m64 _mm_slli_pi16( __m64 a, int imm8 )

Synopsis

#include "mmintrin.h"
Instruction: psllw
CPUID Flag: MMX
Category: Shift

Description

Shift packed 16-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*16
    IF imm8[7:0] > 15
        dst[i+15:i] := 0
    ELSE
        dst[i+15:i] := ZeroExtend(a[i+15:i] << imm8[7:0])
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 1 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 2 | 1 | 2
Ivy Bridge | 2 | 1 | 2
Haswell | 2 | 1 | 2
Broadwell | 2 | 1 | 2
Skylake | 1 | 1 | 2
Knights Landing | 13 | 13 | 2


_mm_slli_pi32

__m64 _mm_slli_pi32( __m64 a, int imm8 )

Synopsis

#include "mmintrin.h"
Instruction: pslld
CPUID Flag: MMX
Category: Shift

Description

Shift packed 32-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*32
    IF imm8[7:0] > 31
        dst[i+31:i] := 0
    ELSE
        dst[i+31:i] := ZeroExtend(a[i+31:i] << imm8[7:0])
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 1 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 2 | 1 | 2
Ivy Bridge | 2 | 1 | 2
Haswell | 2 | 1 | 2
Broadwell | 2 | 1 | 2
Skylake | 1 | 1 | 2
Knights Landing | 13 | 13 | 2


_mm_slli_si128

__m128i _mm_slli_si128( __m128i a, int imm8 )

Synopsis

#include "emmintrin.h"
Instruction: pslldq
CPUID Flag: SSE2
Category: Shift

Description

Shift "a" left by "imm8" bytes while shifting in zeros, and store the results in "dst".

Operation

tmp := imm8[7:0]
IF tmp > 15
    tmp := 16
FI
dst[127:0] := a[127:0] << (tmp*8)

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 1 | 1 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm_slli_si64

__m64 _mm_slli_si64( __m64 a, int imm8 )

Synopsis

#include "mmintrin.h"
Instruction: psllq
CPUID Flag: MMX
Category: Shift

Description

Shift 64-bit integer "a" left by "imm8" while shifting in zeros, and store the result in "dst".

Operation

IF imm8[7:0] > 63
    dst[63:0] := 0
ELSE
    dst[63:0] := ZeroExtend(a[63:0] << imm8[7:0])
FI

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 1 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 2 | 1 | 2
Ivy Bridge | 2 | 1 | 2
Haswell | 2 | 1 | 2
Broadwell | 2 | 1 | 2
Skylake | 1 | 1 | 2
Knights Landing | 13 | 13 | 2


_mm_sllv_epi32

__m128i _mm_sllv_epi32( __m128i a, __m128i count )

Synopsis

#include "immintrin.h"
Instruction: vpsllvd
CPUID Flag: AVX2
Category: Shift

Description

Shift packed 32-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := ZeroExtend(a[i+31:i] << count[i+31:i])
ENDFOR
dst[MAX:128] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 2 | 1
Haswell | 2 | 2 | 3
Broadwell | 2 | 2 | 3
Skylake | 1 | 0.5 | 1
Knights Landing | 2 | 1 | 1
Haswell | 2 | 2 |
Broadwell | 2 | 2 |
Skylake | 2 | 0.5 |


_mm_sllv_epi64

__m128i _mm_sllv_epi64( __m128i a, __m128i count )

Synopsis

#include "immintrin.h"
Instruction: vpsllvq
CPUID Flag: AVX2
Category: Shift

Description

Shift packed 64-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*64
    dst[i+63:i] := ZeroExtend(a[i+63:i] << count[i+63:i])
ENDFOR
dst[MAX:128] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 2 | 1
Haswell | 2 | 2 | 3
Broadwell | 2 | 2 | 3
Skylake | 1 | 0.5 | 1
Knights Landing | 2 | 1 | 1
Haswell | 2 | 2 |
Broadwell | 2 | 2 |
Skylake | 2 | 0.5 |


_mm_sqrt_pd

__m128d _mm_sqrt_pd( __m128d a )

Synopsis

#include "emmintrin.h"
Instruction: sqrtpd
CPUID Flag: SSE2
Category: Elementary Math Functions

Description

Compute the square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*64
    dst[i+63:i] := SQRT(a[i+63:i])
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 14-15 | 4-8 | 1
Jaguar | 27 | 27 | 2
Sandy Bridge | 10-21 | 10-21 | 1
Ivy Bridge | 16 | 8-14 | 1
Haswell | 16 | 8-14 | 1
Broadwell | 15-16 | 8-14 | 1
Skylake | 15-16 | 4-6 | 1
Knights Landing | 37 | 16 | 18
Ivy Bridge | 21 | 14 |
Haswell | 20 | 13 |
Broadwell | 20 | 13 |
Skylake | 18 | 6 |
Knights Landing | 38 | ~10 |


_mm_sqrt_ps

__m128 _mm_sqrt_ps( __m128 a )

Synopsis

#include "xmmintrin.h"
Instruction: sqrtps
CPUID Flag: SSE
Category: Elementary Math Functions

Description

Compute the square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := SQRT(a[i+31:i])
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 9-10 | 4-5 | 1
Jaguar | 21 | 21 | 2
Sandy Bridge | 10-14 | 10-14 | 1
Ivy Bridge | 11 | 7 | 1
Haswell | 11 | 7 | 1
Broadwell | 11 | 7 | 1
Skylake | 12 | 3 | 1
Knights Landing | 38 | 16 | 18
Ivy Bridge | 14 | 7 |
Haswell | 13 | 7 |
Broadwell | 13 | 7 |
Skylake | 13 | 3 |
Knights Landing | 38 | ~10 |


_mm_sqrt_sd

__m128d _mm_sqrt_sd( __m128d a, __m128d b )

Synopsis

#include "emmintrin.h"
Instruction: sqrtsd
CPUID Flag: SSE2
Category: Elementary Math Functions

Description

Compute the square root of the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".

Operation

dst[63:0] := SQRT(b[63:0])
dst[127:64] := a[127:64]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 14-15 | 4-8 | 1
Jaguar | 27 | 27 | 1
Sandy Bridge | 10-21 | 10-21 | 1
Ivy Bridge | 16 | 8-14 | 1
Haswell | 16 | 8-14 | 1
Broadwell | 15-16 | 4-8 | 1
Skylake | 15-16 | 4-6 | 1
Knights Landing | 43 | 35 | 30
Ivy Bridge | 21 | 14 |
Haswell | 20 | 13 |
Broadwell | 20 | 7 |
Skylake | 18 | 6 |
Knights Landing | 40 | ~33 |


_mm_sqrt_ss

__m128 _mm_sqrt_ss( __m128 a )

Synopsis

#include "xmmintrin.h"
Instruction: sqrtss
CPUID Flag: SSE
Category: Elementary Math Functions

Description

Compute the square root of the lower single-precision (32-bit) floating-point element in "a", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".

Operation

dst[31:0] := SQRT(a[31:0])
dst[127:32] := a[127:32]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 9-10 | 4-5 | 1
Jaguar | 16 | 16 | 1
Sandy Bridge | 10-14 | 10-14 | 1
Ivy Bridge | 11 | 7 | 1
Haswell | 11 | 7 | 1
Broadwell | 11 | 4 | 1
Skylake | 12 | 3 | 1
Knights Landing | 28 | 18 | 3
Ivy Bridge | 14 | 7 |
Haswell | 13 | 7 |
Broadwell | 13 | 4 |
Skylake | 13 | 3 |
Knights Landing | 25 | ~20 |


_mm_sra_epi16

__m128i _mm_sra_epi16( __m128i a, __m128i count )

Synopsis

#include "emmintrin.h"
Instruction: psraw
CPUID Flag: SSE2
Category: Shift

Description

Shift packed 16-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*16
    IF count[63:0] > 15
        dst[i+15:i] := SignBit
    ELSE
        dst[i+15:i] := SignExtend(a[i+15:i] >> count[63:0])
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 1 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 2 | 1 | 2
Ivy Bridge | 2 | 1 | 2
Haswell | 2 | 1 | 2
Broadwell | 2 | 1 | 2
Skylake | 1 | 1 | 2
Knights Landing | 13 | 13 | 2
Ivy Bridge | 2 | 1 |
Haswell | 2 | 1 |
Broadwell | 2 | 1 |
Skylake | 2 | 1 |


_mm_sra_epi32

__m128i _mm_sra_epi32( __m128i a, __m128i count )

Synopsis

#include "emmintrin.h"
Instruction: psrad
CPUID Flag: SSE2
Category: Shift

Description

Shift packed 32-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    IF count[63:0] > 31
        dst[i+31:i] := SignBit
    ELSE
        dst[i+31:i] := SignExtend(a[i+31:i] >> count[63:0])
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 1 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 2 | 1 | 2
Ivy Bridge | 2 | 1 | 2
Haswell | 2 | 1 | 2
Broadwell | 2 | 1 | 2
Skylake | 1 | 1 | 2
Knights Landing | 13 | 13 | 2
Ivy Bridge | 2 | 1 |
Haswell | 2 | 1 |
Broadwell | 2 | 1 |
Skylake | 2 | 1 |


_mm_sra_pi16

__m64 _mm_sra_pi16( __m64 a, __m64 count )

Synopsis

#include "mmintrin.h"
Instruction: psraw
CPUID Flag: MMX
Category: Shift

Description

Shift packed 16-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*16
    IF count[63:0] > 15
        dst[i+15:i] := SignBit
    ELSE
        dst[i+15:i] := SignExtend(a[i+15:i] >> count[63:0])
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 1 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 2 | 1 | 2
Ivy Bridge | 2 | 1 | 2
Haswell | 2 | 1 | 2
Broadwell | 2 | 1 | 2
Skylake | 1 | 1 | 2
Knights Landing | 13 | 13 | 2


_mm_sra_pi32

__m64 _mm_sra_pi32( __m64 a, __m64 count )

Synopsis

#include "mmintrin.h"
Instruction: psrad
CPUID Flag: MMX
Category: Shift

Description

Shift packed 32-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*32
    IF count[63:0] > 31
        dst[i+31:i] := SignBit
    ELSE
        dst[i+31:i] := SignExtend(a[i+31:i] >> count[63:0])
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 1 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 2 | 1 | 2
Ivy Bridge | 2 | 1 | 2
Haswell | 2 | 1 | 2
Broadwell | 2 | 1 | 2
Skylake | 1 | 1 | 2
Knights Landing | 13 | 13 | 2


_mm_srai_epi16

__m128i _mm_srai_epi16( __m128i a, int imm8 )

Synopsis

#include "emmintrin.h"
Instruction: psraw
CPUID Flag: SSE2
Category: Shift

Description

Shift packed 16-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*16
    IF imm8[7:0] > 15
        dst[i+15:i] := SignBit
    ELSE
        dst[i+15:i] := SignExtend(a[i+15:i] >> imm8[7:0])
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 1 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 2 | 1 | 2
Ivy Bridge | 2 | 1 | 2
Haswell | 2 | 1 | 2
Broadwell | 2 | 1 | 2
Skylake | 1 | 1 | 2
Knights Landing | 13 | 13 | 2
Ivy Bridge | 1 | 1 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm_srai_epi32

__m128i _mm_srai_epi32( __m128i a, int imm8 )

Synopsis

#include "emmintrin.h"
Instruction: psrad
CPUID Flag: SSE2
Category: Shift

Description

Shift packed 32-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    IF imm8[7:0] > 31
        dst[i+31:i] := SignBit
    ELSE
        dst[i+31:i] := SignExtend(a[i+31:i] >> imm8[7:0])
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 1 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 2 | 1 | 2
Ivy Bridge | 2 | 1 | 2
Haswell | 2 | 1 | 2
Broadwell | 2 | 1 | 2
Skylake | 1 | 1 | 2
Knights Landing | 13 | 13 | 2
Ivy Bridge | 1 | 1 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm_srai_pi16

__m64 _mm_srai_pi16( __m64 a, int imm8 )

Synopsis

#include "mmintrin.h"
Instruction: psraw
CPUID Flag: MMX
Category: Shift

Description

Shift packed 16-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*16
    IF imm8[7:0] > 15
        dst[i+15:i] := SignBit
    ELSE
        dst[i+15:i] := SignExtend(a[i+15:i] >> imm8[7:0])
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 1 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 2 | 1 | 2
Ivy Bridge | 2 | 1 | 2
Haswell | 2 | 1 | 2
Broadwell | 2 | 1 | 2
Skylake | 1 | 1 | 2
Knights Landing | 13 | 13 | 2


_mm_srai_pi32

__m64 _mm_srai_pi32( __m64 a, int imm8 )

Synopsis

#include "mmintrin.h"
Instruction: psrad
CPUID Flag: MMX
Category: Shift

Description

Shift packed 32-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*32
    IF imm8[7:0] > 31
        dst[i+31:i] := SignBit
    ELSE
        dst[i+31:i] := SignExtend(a[i+31:i] >> imm8[7:0])
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 1 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 2 | 1 | 2
Ivy Bridge | 2 | 1 | 2
Haswell | 2 | 1 | 2
Broadwell | 2 | 1 | 2
Skylake | 1 | 1 | 2
Knights Landing | 13 | 13 | 2


_mm_srav_epi32

__m128i _mm_srav_epi32( __m128i a, __m128i count )

Synopsis

#include "immintrin.h"
Instruction: vpsravd
CPUID Flag: AVX2
Category: Shift

Description

Shift packed 32-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := SignExtend(a[i+31:i] >> count[i+31:i])
ENDFOR
dst[MAX:128] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 2 | 1
Haswell | 2 | 2 | 3
Broadwell | 2 | 2 | 3
Skylake | 1 | 0.5 | 1
Knights Landing | 2 | 1 | 1
Haswell | 2 | 2 |
Broadwell | 2 | 2 |
Skylake | 2 | 0.5 |


_mm_srl_epi16

__m128i _mm_srl_epi16( __m128i a, __m128i count )

Synopsis

#include "emmintrin.h"
Instruction: psrlw
CPUID Flag: SSE2
Category: Shift

Description

Shift packed 16-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*16
    IF count[63:0] > 15
        dst[i+15:i] := 0
    ELSE
        dst[i+15:i] := ZeroExtend(a[i+15:i] >> count[63:0])
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 1 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 2 | 1 | 2
Ivy Bridge | 2 | 1 | 2
Haswell | 2 | 1 | 2
Broadwell | 2 | 1 | 2
Skylake | 1 | 1 | 2
Knights Landing | 13 | 13 | 2
Ivy Bridge | 1 | 1 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm_srl_epi32

__m128i _mm_srl_epi32( __m128i a, __m128i count )

Synopsis

#include "emmintrin.h"
Instruction: psrld
CPUID Flag: SSE2
Category: Shift

Description

Shift packed 32-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    IF count[63:0] > 31
        dst[i+31:i] := 0
    ELSE
        dst[i+31:i] := ZeroExtend(a[i+31:i] >> count[63:0])
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 1 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 2 | 1 | 2
Ivy Bridge | 2 | 1 | 2
Haswell | 2 | 1 | 2
Broadwell | 2 | 1 | 2
Skylake | 1 | 1 | 2
Knights Landing | 13 | 13 | 2
Ivy Bridge | 1 | 1 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm_srl_epi64

__m128i _mm_srl_epi64( __m128i a, __m128i count )

Synopsis

#include "emmintrin.h"
Instruction: psrlq
CPUID Flag: SSE2
Category: Shift

Description

Shift packed 64-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*64
    IF count[63:0] > 63
        dst[i+63:i] := 0
    ELSE
        dst[i+63:i] := ZeroExtend(a[i+63:i] >> count[63:0])
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 1 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 2 | 1 | 2
Ivy Bridge | 2 | 1 | 2
Haswell | 2 | 1 | 2
Broadwell | 2 | 1 | 2
Skylake | 1 | 1 | 2
Knights Landing | 13 | 13 | 2
Ivy Bridge | 1 | 1 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm_srl_pi16

__m64 _mm_srl_pi16( __m64 a, __m64 count )

Synopsis

#include "mmintrin.h"
Instruction: psrlw
CPUID Flag: MMX
Category: Shift

Description

Shift packed 16-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*16
    IF count[63:0] > 15
        dst[i+15:i] := 0
    ELSE
        dst[i+15:i] := ZeroExtend(a[i+15:i] >> count[63:0])
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 1 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 2 | 1 | 2
Ivy Bridge | 2 | 1 | 2
Haswell | 2 | 1 | 2
Broadwell | 2 | 1 | 2
Skylake | 1 | 1 | 2
Knights Landing | 13 | 13 | 2


_mm_srl_pi32

__m64 _mm_srl_pi32( __m64 a, __m64 count )

Synopsis

#include "mmintrin.h"
Instruction: psrld
CPUID Flag: MMX
Category: Shift

Description

Shift packed 32-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*32
    IF count[63:0] > 31
        dst[i+31:i] := 0
    ELSE
        dst[i+31:i] := ZeroExtend(a[i+31:i] >> count[63:0])
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 1 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 2 | 1 | 2
Ivy Bridge | 2 | 1 | 2
Haswell | 2 | 1 | 2
Broadwell | 2 | 1 | 2
Skylake | 1 | 1 | 2
Knights Landing | 13 | 13 | 2


_mm_srl_si64

__m64 _mm_srl_si64( __m64 a, __m64 count )

Synopsis

#include "mmintrin.h"
Instruction: psrlq
CPUID Flag: MMX
Category: Shift

Description

Shift 64-bit integer "a" right by "count" while shifting in zeros, and store the result in "dst".

Operation

IF count[63:0] > 63
    dst[63:0] := 0
ELSE
    dst[63:0] := ZeroExtend(a[63:0] >> count[63:0])
FI

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 1 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 2 | 1 | 2
Ivy Bridge | 2 | 1 | 2
Haswell | 2 | 1 | 2
Broadwell | 2 | 1 | 2
Skylake | 1 | 1 | 2
Knights Landing | 13 | 13 | 2


_mm_srli_epi16

__m128i _mm_srli_epi16( __m128i a, int imm8 )

Synopsis

#include "emmintrin.h"
Instruction: psrlw
CPUID Flag: SSE2
Category: Shift

Description

Shift packed 16-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*16
    IF imm8[7:0] > 15
        dst[i+15:i] := 0
    ELSE
        dst[i+15:i] := ZeroExtend(a[i+15:i] >> imm8[7:0])
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 1 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 2 | 1 | 2
Ivy Bridge | 2 | 1 | 2
Haswell | 2 | 1 | 2
Broadwell | 2 | 1 | 2
Skylake | 1 | 1 | 2
Knights Landing | 13 | 13 | 2
Ivy Bridge | 1 | 1 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm_srli_epi32

__m128i _mm_srli_epi32( __m128i a, int imm8 )

Synopsis

#include "emmintrin.h"
Instruction: psrld
CPUID Flag: SSE2
Category: Shift

Description

Shift packed 32-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    IF imm8[7:0] > 31
        dst[i+31:i] := 0
    ELSE
        dst[i+31:i] := ZeroExtend(a[i+31:i] >> imm8[7:0])
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 1 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 2 | 1 | 2
Ivy Bridge | 2 | 1 | 2
Haswell | 2 | 1 | 2
Broadwell | 2 | 1 | 2
Skylake | 1 | 1 | 2
Knights Landing | 13 | 13 | 2
Ivy Bridge | 1 | 1 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm_srli_epi64

__m128i _mm_srli_epi64( __m128i a, int imm8 )

Synopsis

#include "emmintrin.h"
Instruction: psrlq
CPUID Flag: SSE2
Category: Shift

Description

Shift packed 64-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*64
    IF imm8[7:0] > 63
        dst[i+63:i] := 0
    ELSE
        dst[i+63:i] := ZeroExtend(a[i+63:i] >> imm8[7:0])
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 1 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 2 | 1 | 2
Ivy Bridge | 2 | 1 | 2
Haswell | 2 | 1 | 2
Broadwell | 2 | 1 | 2
Skylake | 1 | 1 | 2
Knights Landing | 13 | 13 | 2
Ivy Bridge | 1 | 1 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm_srli_pi16

__m64 _mm_srli_pi16( __m64 a, int imm8 )

Synopsis

#include "mmintrin.h"
Instruction: psrlw
CPUID Flag: MMX
Category: Shift

Description

Shift packed 16-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*16
    IF imm8[7:0] > 15
        dst[i+15:i] := 0
    ELSE
        dst[i+15:i] := ZeroExtend(a[i+15:i] >> imm8[7:0])
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 1 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 2 | 1 | 2
Ivy Bridge | 2 | 1 | 2
Haswell | 2 | 1 | 2
Broadwell | 2 | 1 | 2
Skylake | 1 | 1 | 2
Knights Landing | 13 | 13 | 2


_mm_srli_pi32

__m64 _mm_srli_pi32( __m64 a, int imm8 )

Synopsis

#include "mmintrin.h"
Instruction: psrld
CPUID Flag: MMX
Category: Shift

Description

Shift packed 32-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*32
    IF imm8[7:0] > 31
        dst[i+31:i] := 0
    ELSE
        dst[i+31:i] := ZeroExtend(a[i+31:i] >> imm8[7:0])
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 1 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 2 | 1 | 2
Ivy Bridge | 2 | 1 | 2
Haswell | 2 | 1 | 2
Broadwell | 2 | 1 | 2
Skylake | 1 | 1 | 2
Knights Landing | 13 | 13 | 2


_mm_srli_si128

__m128i _mm_srli_si128( __m128i a, int imm8 )

Synopsis

#include "emmintrin.h"
Instruction: psrldq
CPUID Flag: SSE2
Category: Shift

Description

Shift "a" right by "imm8" bytes while shifting in zeros, and store the results in "dst".

Operation

tmp := imm8[7:0]
IF tmp > 15
    tmp := 16
FI
dst[127:0] := a[127:0] >> (tmp*8)

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 1 | 1 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm_srli_si64

__m64 _mm_srli_si64( __m64 a, int imm8 )

Synopsis

#include "mmintrin.h"
Instruction: psrlq
CPUID Flag: MMX
Category: Shift

Description

Shift 64-bit integer "a" right by "imm8" while shifting in zeros, and store the result in "dst".

Operation

IF imm8[7:0] > 63
    dst[63:0] := 0
ELSE
    dst[63:0] := ZeroExtend(a[63:0] >> imm8[7:0])
FI

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 1 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 2 | 1 | 2
Ivy Bridge | 2 | 1 | 2
Haswell | 2 | 1 | 2
Broadwell | 2 | 1 | 2
Skylake | 1 | 1 | 2
Knights Landing | 13 | 13 | 2


_mm_srlv_epi32

__m128i _mm_srlv_epi32( __m128i a, __m128i count )

Synopsis

#include "immintrin.h"
Instruction: vpsrlvd
CPUID Flag: AVX2
Category: Shift

Description

Shift packed 32-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := ZeroExtend(a[i+31:i] >> count[i+31:i])
ENDFOR
dst[MAX:128] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 2 | 1
Haswell | 2 | 2 | 3
Broadwell | 2 | 2 | 3
Skylake | 1 | 0.5 | 1
Knights Landing | 2 | 1 | 1


_mm_srlv_epi64

__m128i _mm_srlv_epi64( __m128i a, __m128i count )

Synopsis

#include "immintrin.h"
Instruction: vpsrlvq
CPUID Flag: AVX2
Category: Shift

Description

Shift packed 64-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*64
    dst[i+63:i] := ZeroExtend(a[i+63:i] >> count[i+63:i])
ENDFOR
dst[MAX:128] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 2 | 1
Haswell | 2 | 2 | 3
Broadwell | 2 | 2 | 3
Skylake | 1 | 0.5 | 1
Knights Landing | 2 | 1 | 1


_mm_store_pd

void _mm_store_pd( double* mem_addr, __m128d a )

Synopsis

#include "emmintrin.h"
Instruction: movapd
CPUID Flag: SSE2
Category: Store

Description

Store 128-bits (composed of 2 packed double-precision (64-bit) floating-point elements) from "a" into memory. "mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.

Operation

MEM[mem_addr+127:mem_addr] := a[127:0]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 0 | 0.25 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 1 | 1
Ivy Bridge | 0-1 | ≤1 | 1
Haswell | 0-1 | 1 | 1
Broadwell | 0-1 | 1 | 1
Skylake | 0-1 | 0.25 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 1 | 1 |
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.33 |


_mm_store_pd1

void _mm_store_pd1( double* mem_addr, __m128d a )

Synopsis

#include "emmintrin.h"
Instruction: N/A
CPUID Flag: SSE2
Category: Store

Description

Store the lower double-precision (64-bit) floating-point element from "a" into 2 contiguous elements in memory. "mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.

Operation

MEM[mem_addr+63:mem_addr] := a[63:0]
MEM[mem_addr+127:mem_addr+64] := a[63:0]


_mm_store_ps

void _mm_store_ps( float* mem_addr, __m128 a )

Synopsis

#include "xmmintrin.h"
Instruction: movaps
CPUID Flag: SSE
Category: Store

Description

Store 128-bits (composed of 4 packed single-precision (32-bit) floating-point elements) from "a" into memory. "mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.

Operation

MEM[mem_addr+127:mem_addr] := a[127:0]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 0 | 0.25 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 1 | 1
Ivy Bridge | 0-1 | ≤1 | 1
Haswell | 0-1 | 1 | 1
Broadwell | 0-1 | 1 | 1
Skylake | 0-1 | 0.25 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 1 | 1 |
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.25 |


_mm_store_ps1

void _mm_store_ps1( float* mem_addr, __m128 a )

Synopsis

#include "xmmintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Store

Description

Store the lower single-precision (32-bit) floating-point element from "a" into 4 contiguous elements in memory. "mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.

Operation

MEM[mem_addr+31:mem_addr] := a[31:0]
MEM[mem_addr+63:mem_addr+32] := a[31:0]
MEM[mem_addr+95:mem_addr+64] := a[31:0]
MEM[mem_addr+127:mem_addr+96] := a[31:0]


_mm_store_sd

void _mm_store_sd( double* mem_addr, __m128d a )

Synopsis

#include "emmintrin.h"
Instruction: movsd
CPUID Flag: SSE2
Category: Store

Description

Store the lower double-precision (64-bit) floating-point element from "a" into memory. "mem_addr" does not need to be aligned on any particular boundary.

Operation

MEM[mem_addr+63:mem_addr] := a[63:0]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.25 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 1 | 1
Ivy Bridge | 1 | 1 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 1 | 1 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm_store_si128

void _mm_store_si128( __m128i* mem_addr, __m128i a )

Synopsis

#include "emmintrin.h"
Instruction: movdqa
CPUID Flag: SSE2
Category: Store

Description

Store 128-bits of integer data from "a" into memory. "mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.

Operation

MEM[mem_addr+127:mem_addr] := a[127:0]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 0 | 0.25 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 |  | 1
Ivy Bridge | 0-1 | 0.25 | 1
Haswell | 0-1 | 0.33 | 1
Broadwell | 0-1 | 0.25 | 1
Skylake | 0-1 | 0.25 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 0.33 |
Broadwell | 1 | 0.33 |
Skylake | 1 | 0.25 |


_mm_store_ss

void _mm_store_ss( float* mem_addr, __m128 a )

Synopsis

#include "xmmintrin.h"
Instruction: movss
CPUID Flag: SSE
Category: Store

Description

Store the lower single-precision (32-bit) floating-point element from "a" into memory. "mem_addr" does not need to be aligned on any particular boundary.

Operation

MEM[mem_addr+31:mem_addr] := a[31:0]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.25 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 1 | 1
Ivy Bridge | 1 | 1 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 1 | 1 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm_store1_pd

void _mm_store1_pd( double* mem_addr, __m128d a )

Synopsis

#include "emmintrin.h"
Instruction: N/A
CPUID Flag: SSE2
Category: Store

Description

Store the lower double-precision (64-bit) floating-point element from "a" into 2 contiguous elements in memory. "mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.

Operation

MEM[mem_addr+63:mem_addr] := a[63:0]
MEM[mem_addr+127:mem_addr+64] := a[63:0]


_mm_store1_ps

void _mm_store1_ps( float* mem_addr, __m128 a )

Synopsis

#include "xmmintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Store

Description

Store the lower single-precision (32-bit) floating-point element from "a" into 4 contiguous elements in memory. "mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.

Operation

MEM[mem_addr+31:mem_addr] := a[31:0]
MEM[mem_addr+63:mem_addr+32] := a[31:0]
MEM[mem_addr+95:mem_addr+64] := a[31:0]
MEM[mem_addr+127:mem_addr+96] := a[31:0]


_mm_storeh_pd

void _mm_storeh_pd( double* mem_addr, __m128d a )

Synopsis

#include "emmintrin.h"
Instruction: movhpd
CPUID Flag: SSE2
Category: Store

Description

Store the upper double-precision (64-bit) floating-point element from "a" into memory.

Operation

MEM[mem_addr+63:mem_addr] := a[127:64]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 4 | 0.5 | 1
Jaguar | 5 | 1 | 1
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 4 | 1 | 2
Haswell | 4 | 1 | 1
Broadwell | 4 | 1 | 1
Skylake | 4 | 1 | 1
Knights Landing | 6 | 1.5 | 1


_mm_storeh_pi

void _mm_storeh_pi( __m64* mem_addr, __m128 a )

Synopsis

#include "xmmintrin.h"
Instruction: movhps
CPUID Flag: SSE
Category: Store

Description

Store the upper 2 single-precision (32-bit) floating-point elements from "a" into memory.

Operation

MEM[mem_addr+31:mem_addr] := a[95:64]
MEM[mem_addr+63:mem_addr+32] := a[127:96]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 4 | 0.5 | 1
Jaguar | 5 | 1 | 1
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 4 | 1 | 2
Haswell | 4 | 1 | 1
Broadwell | 4 | 1 | 1
Skylake | 4 | 1 | 1
Knights Landing | 6 | 1.5 | 1


_mm_storel_epi64

void _mm_storel_epi64( __m128i* mem_addr, __m128i a )

Synopsis

#include "emmintrin.h"
Instruction: movq
CPUID Flag: SSE2
Category: Store

Description

Store 64-bit integer from the first element of "a" into memory.

Operation

MEM[mem_addr+63:mem_addr] := a[63:0]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.25 | 1
Jaguar | 4 | 1 | 1
Sandy Bridge | 1 |  | 1
Ivy Bridge | 1 | 0.33 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 2 | 1 | 1
Knights Landing | 4 | 1 | 1
Ivy Bridge | 1 | 0.33 |
Haswell | 1 | 0.33 |
Broadwell | 1 | 0.33 |
Skylake | 1 | 0.33 |


_mm_storel_pd

void _mm_storel_pd( double* mem_addr, __m128d a )

Synopsis

#include "emmintrin.h"
Instruction: movlpd
CPUID Flag: SSE2
Category: Store

Description

Store the lower double-precision (64-bit) floating-point element from "a" into memory.

Operation

MEM[mem_addr+63:mem_addr] := a[63:0]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 4 | 0.5 | 1
Jaguar | 5 | 1 | 1
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 4 | 1 | 2
Haswell | 4 | 1 | 1
Broadwell | 4 | 1 | 1
Skylake | 4 | 1 | 1
Knights Landing | 6 | 1.5 | 1


_mm_storel_pi

void _mm_storel_pi( __m64* mem_addr, __m128 a )

Synopsis

#include "xmmintrin.h"
Instruction: movlps
CPUID Flag: SSE
Category: Store

Description

Store the lower 2 single-precision (32-bit) floating-point elements from "a" into memory.

Operation

MEM[mem_addr+31:mem_addr] := a[31:0]
MEM[mem_addr+63:mem_addr+32] := a[63:32]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 4 | 0.5 | 1
Jaguar | 5 | 1 | 1
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 4 | 1 | 2
Haswell | 4 | 1 | 1
Broadwell | 4 | 1 | 1
Skylake | 4 | 1 | 1
Knights Landing | 6 | 1.5 | 1


_mm_storer_pd

void _mm_storer_pd( double* mem_addr, __m128d a )

Synopsis

#include "emmintrin.h"
Instruction: N/A
CPUID Flag: SSE2
Category: Store

Description

Store 2 double-precision (64-bit) floating-point elements from "a" into memory in reverse order. "mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.

Operation

MEM[mem_addr+63:mem_addr] := a[127:64]
MEM[mem_addr+127:mem_addr+64] := a[63:0]


_mm_storer_ps

void _mm_storer_ps( float* mem_addr, __m128 a )

Synopsis

#include "xmmintrin.h"
Instruction: movups
CPUID Flag: SSE
Category: Store

Description

Store 4 single-precision (32-bit) floating-point elements from "a" into memory in reverse order. "mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.

Operation

MEM[mem_addr+31:mem_addr] := a[127:96]
MEM[mem_addr+63:mem_addr+32] := a[95:64]
MEM[mem_addr+95:mem_addr+64] := a[63:32]
MEM[mem_addr+127:mem_addr+96] := a[31:0]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 0 | 0.25 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 3 | 0.5 | 1
Ivy Bridge | 3 | 0.5 | 1
Haswell | 3 | 0.5 | 1
Broadwell | 3 | 0.5 | 1
Skylake | 2 | 0.5 | 1
Knights Landing | 5 | 0.5 | 1
Ivy Bridge | 1 | 1 |
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.25 |


_mm_storeu_pd

void _mm_storeu_pd( double* mem_addr, __m128d a )

Synopsis

#include "emmintrin.h"
Instruction: movupd
CPUID Flag: SSE2
Category: Store

Description

Store 128-bits (composed of 2 packed double-precision (64-bit) floating-point elements) from "a" into memory. "mem_addr" does not need to be aligned on any particular boundary.

Operation

MEM[mem_addr+127:mem_addr] := a[127:0]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 0 | 0.25 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 3 | 0.5 | 1
Ivy Bridge | 3 | 0.5 | 1
Haswell | 3 | 0.5 | 1
Broadwell | 3 | 0.5 | 1
Skylake | 2 | 0.5 | 1
Knights Landing | 5 | 0.5 | 1
Ivy Bridge | 1 | 1 |
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.33 |


_mm_storeu_ps

void _mm_storeu_ps( float* mem_addr, __m128 a )

Synopsis

#include "xmmintrin.h"
Instruction: movups
CPUID Flag: SSE
Category: Store

Description

Store 128-bits (composed of 4 packed single-precision (32-bit) floating-point elements) from "a" into memory. "mem_addr" does not need to be aligned on any particular boundary.

Operation

MEM[mem_addr+127:mem_addr] := a[127:0]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 0 | 0.25 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 3 | 0.5 | 1
Ivy Bridge | 3 | 0.5 | 1
Haswell | 3 | 0.5 | 1
Broadwell | 3 | 0.5 | 1
Skylake | 2 | 0.5 | 1
Knights Landing | 5 | 0.5 | 1
Ivy Bridge | 1 | 1 |
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.25 |


_mm_storeu_si128

void _mm_storeu_si128( __m128i* mem_addr, __m128i a )

Synopsis

#include "emmintrin.h"
Instruction: movdqu
CPUID Flag: SSE2
Category: Store

Description

Store 128-bits of integer data from "a" into memory. "mem_addr" does not need to be aligned on any particular boundary.

Operation

MEM[mem_addr+127:mem_addr] := a[127:0]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 0 | 0.25 | 1
Jaguar | 4 | 1 | 1
Sandy Bridge | 3 | 0.5 | 1
Ivy Bridge | 0-1 | 0.25 | 1
Haswell | 0-1 | 0.33 | 1
Broadwell | 0-1 | 0.25 | 1
Skylake | 0-1 | 0.25 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 0.33 |
Broadwell | 1 | 0.33 |
Skylake | 1 | 0.25 |


_mm_storeu_si16

void _mm_storeu_si16( void* mem_addr, __m128i a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Store

Description

Store 16-bit integer from the first element of "a" into memory. "mem_addr" does not need to be aligned on any particular boundary.

Operation

MEM[mem_addr+15:mem_addr] := a[15:0]


_mm_storeu_si32

void _mm_storeu_si32( void* mem_addr, __m128i a )

Synopsis

#include "immintrin.h"
Instruction: movd
CPUID Flag: SSE2
Category: Store

Description

Store 32-bit integer from the first element of "a" into memory. "mem_addr" does not need to be aligned on any particular boundary.

Operation

MEM[mem_addr+31:mem_addr] := a[31:0]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 1 | 1
Jaguar | 4 | 1 | 1
Sandy Bridge | 1 |  | 1
Ivy Bridge | 1 | 1 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 2 | 1 | 1
Knights Landing | 4 | 1 | 1


_mm_storeu_si64

void _mm_storeu_si64( void* mem_addr, __m128i a )

Synopsis

#include "immintrin.h"
Instruction: movq
CPUID Flag: SSE
Category: Store

Description

Store 64-bit integer from the first element of "a" into memory. "mem_addr" does not need to be aligned on any particular boundary.

Operation

MEM[mem_addr+63:mem_addr] := a[63:0]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.25 | 1
Jaguar | 4 | 1 | 1
Sandy Bridge | 1 |  | 1
Ivy Bridge | 1 | 0.33 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 2 | 1 | 1
Knights Landing | 4 | 1 | 1


_mm_stream_load_si128

__m128i _mm_stream_load_si128( __m128i * mem_addr )

Synopsis

#include "smmintrin.h"
Instruction: movntdqa
CPUID Flag: SSE4.1
Category: Load

Description

Load 128-bits of integer data from memory into "dst" using a non-temporal memory hint. "mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.

Operation

dst[127:0] := MEM[mem_addr+127:mem_addr]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 0.5 | 1
Sandy Bridge |  | 0.5 | 1
Ivy Bridge | 3 | 0.5 | 1
Haswell | 3 | 0.5 | 1
Broadwell | 3 | 0.5 | 1
Skylake | 3 | 0.5 | 2
Knights Landing | 5 | 0.5 | 1


_mm_stream_pd

void _mm_stream_pd( double* mem_addr, __m128d a )

Synopsis

#include "emmintrin.h"
Instruction: movntpd
CPUID Flag: SSE2
Category: Store

Description

Store 128-bits (composed of 2 packed double-precision (64-bit) floating-point elements) from "a" into memory using a non-temporal memory hint. "mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.

Operation

MEM[mem_addr+127:mem_addr] := a[127:0]

Performance

Architecture | Latency | Throughput | μops
Ryzen | ~950 | 1 | 1
Jaguar | 429 | 1 | 1
Sandy Bridge | ~300 | 1 | 1
Ivy Bridge | ~380 | 1 | 1
Haswell | ~400 | 1 | 1
Broadwell | ~400 | 1 | 1
Skylake | ~400 | 1 | 1
Knights Landing | ~500 |  | 1


_mm_stream_pi

void _mm_stream_pi( __m64* mem_addr, __m64 a )

Synopsis

#include "xmmintrin.h"
Instruction: movntq
CPUID Flag: SSE
Category: Store

Description

Store 64-bits of integer data from "a" into memory using a non-temporal memory hint.

Operation

MEM[mem_addr+63:mem_addr] := a[63:0]

Performance

Architecture | Latency | Throughput | μops
Ryzen | ~900 | 1 | 1
Jaguar | 429 | 2 | 1
Sandy Bridge | ~300 | 1 | 1
Ivy Bridge | ~360 | 1 | 1
Haswell | ~400 | 1 | 1
Broadwell | ~400 | 1 | 1
Skylake | ~418 | 1 | 1
Knights Landing | ~650 | 1 | 1


_mm_stream_ps

void _mm_stream_ps( float* mem_addr, __m128 a )

Synopsis

#include "xmmintrin.h"
Instruction: movntps
CPUID Flag: SSE
Category: Store

Description

Store 128-bits (composed of 4 packed single-precision (32-bit) floating-point elements) from "a" into memory using a non-temporal memory hint. "mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.

Operation

MEM[mem_addr+127:mem_addr] := a[127:0]

Performance

Architecture | Latency | Throughput | μops
Ryzen | ~950 | 1 | 1
Jaguar | 429 | 1 | 1
Sandy Bridge | ~300 | 1 | 1
Ivy Bridge | ~380 | 1 | 1
Haswell | ~400 | 1 | 1
Broadwell | ~400 | 1 | 1
Skylake | ~400 | 1 | 1
Knights Landing | ~500 |  | 1


_mm_stream_si128

void _mm_stream_si128( __m128i* mem_addr, __m128i a )

Synopsis

#include "emmintrin.h"
Instruction: movntdq
CPUID Flag: SSE2
Category: Store

Description

Store 128-bits of integer data from "a" into memory using a non-temporal memory hint. "mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.

Operation

MEM[mem_addr+127:mem_addr] := a[127:0]

Performance

Architecture | Latency | Throughput | μops
Ryzen | ~900 | 1 | 1
Jaguar | 429 | 2 | 1
Sandy Bridge | ~300 |  | 1
Ivy Bridge | ~360 | 1 | 1
Haswell | ~400 | 1 | 1
Broadwell | ~400 | 1 | 1
Skylake | ~450 | 1 | 1
Knights Landing | ~550 | 1 | 1


_mm_stream_si32

void _mm_stream_si32( int* mem_addr, int a )

Synopsis

#include "emmintrin.h"
Instruction: movnti
CPUID Flag: SSE2
Category: Store

Description

Store 32-bit integer "a" into memory using a non-temporal hint to minimize cache pollution. If the cache line containing address "mem_addr" is already in the cache, the cache will be updated.

Operation

MEM[mem_addr+31:mem_addr] := a[31:0]


_mm_stream_si64

void _mm_stream_si64( __int64* mem_addr, __int64 a )

Synopsis

#include "emmintrin.h"
Instruction: movnti
CPUID Flag: SSE2
Category: Store

Description

Store 64-bit integer "a" into memory using a non-temporal hint to minimize cache pollution. If the cache line containing address "mem_addr" is already in the cache, the cache will be updated.

Operation

MEM[mem_addr+63:mem_addr] := a[63:0]


_mm_sub_epi16

__m128i _mm_sub_epi16( __m128i a, __m128i b )

Synopsis

#include "emmintrin.h"
Instruction: psubw
CPUID Flag: SSE2
Category: Arithmetic

Description

Subtract packed 16-bit integers in "b" from packed 16-bit integers in "a", and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*16
    dst[i+15:i] := a[i+15:i] - b[i+15:i]
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.33 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.33 |


_mm_sub_epi32

__m128i _mm_sub_epi32( __m128i a, __m128i b )

Synopsis

#include "emmintrin.h"
Instruction: psubd
CPUID Flag: SSE2
Category: Arithmetic

Description

Subtract packed 32-bit integers in "b" from packed 32-bit integers in "a", and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := a[i+31:i] - b[i+31:i]
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.33 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.33 |


_mm_sub_epi64

__m128i _mm_sub_epi64( __m128i a, __m128i b )

Synopsis

#include "emmintrin.h"
Instruction: psubq
CPUID Flag: SSE2
Category: Arithmetic

Description

Subtract packed 64-bit integers in "b" from packed 64-bit integers in "a", and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*64
    dst[i+63:i] := a[i+63:i] - b[i+63:i]
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.33 | 1
Knights Landing | 2 | 0.5 | 1


_mm_sub_epi8

__m128i _mm_sub_epi8( __m128i a, __m128i b )

Synopsis

#include "emmintrin.h"
Instruction: psubb
CPUID Flag: SSE2
Category: Arithmetic

Description

Subtract packed 8-bit integers in "b" from packed 8-bit integers in "a", and store the results in "dst".

Operation

FOR j := 0 to 15
    i := j*8
    dst[i+7:i] := a[i+7:i] - b[i+7:i]
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.33 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.33 |


_mm_sub_pd

__m128d _mm_sub_pd( __m128d a, __m128d b )

Synopsis

#include "emmintrin.h"
Instruction: subpd
CPUID Flag: SSE2
Category: Arithmetic

Description

Subtract packed double-precision (64-bit) floating-point elements in "b" from packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*64
    dst[i+63:i] := a[i+63:i] - b[i+63:i]
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 0.5 | 1
Jaguar | 3 | 1 | 1
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 4 | 0.5 | 1
Knights Landing | 6 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 4 | 0.5 |


_mm_sub_pi16

__m64 _mm_sub_pi16( __m64 a, __m64 b )

Synopsis

#include "mmintrin.h"
Instruction: psubw
CPUID Flag: MMX
Category: Arithmetic

Description

Subtract packed 16-bit integers in "b" from packed 16-bit integers in "a", and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*16
    dst[i+15:i] := a[i+15:i] - b[i+15:i]
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.33 | 1
Knights Landing | 2 | 0.5 | 1


_mm_sub_pi32

__m64 _mm_sub_pi32( __m64 a, __m64 b )

Synopsis

#include "mmintrin.h"
Instruction: psubd
CPUID Flag: MMX
Category: Arithmetic

Description

Subtract packed 32-bit integers in "b" from packed 32-bit integers in "a", and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*32
    dst[i+31:i] := a[i+31:i] - b[i+31:i]
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.33 | 1
Knights Landing | 2 | 0.5 | 1


_mm_sub_pi8

__m64 _mm_sub_pi8( __m64 a, __m64 b )

Synopsis

#include "mmintrin.h"
Instruction: psubb
CPUID Flag: MMX
Category: Arithmetic

Description

Subtract packed 8-bit integers in "b" from packed 8-bit integers in "a", and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*8
    dst[i+7:i] := a[i+7:i] - b[i+7:i]
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.33 | 1
Knights Landing | 2 | 0.5 | 1


_mm_sub_ps

__m128 _mm_sub_ps( __m128 a, __m128 b )

Synopsis

#include "xmmintrin.h"
Instruction: subps
CPUID Flag: SSE
Category: Arithmetic

Description

Subtract packed single-precision (32-bit) floating-point elements in "b" from packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := a[i+31:i] - b[i+31:i]
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 0.5 | 1
Jaguar | 3 | 1 | 1
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 4 | 0.5 | 1
Knights Landing | 6 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 4 | 0.5 |


_mm_sub_sd

__m128d _mm_sub_sd( __m128d a, __m128d b )

Synopsis

#include "emmintrin.h"
Instruction: subsd
CPUID Flag: SSE2
Category: Arithmetic

Description

Subtract the lower double-precision (64-bit) floating-point element in "b" from the lower double-precision (64-bit) floating-point element in "a", store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".

Operation

dst[63:0] := a[63:0] - b[63:0]
dst[127:64] := a[127:64]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 0.5 | 1
Jaguar | 3 | 1 | 1
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 4 | 0.5 | 1
Knights Landing | 6 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 4 | 0.5 |


_mm_sub_si64

__m64 _mm_sub_si64( __m64 a, __m64 b )

Synopsis

#include "emmintrin.h"
Instruction: psubq
CPUID Flag: SSE2
Category: Arithmetic

Description

Subtract 64-bit integer "b" from 64-bit integer "a", and store the result in "dst".

Operation

dst[63:0] := a[63:0] - b[63:0]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.33 | 1
Knights Landing | 2 | 0.5 | 1


_mm_sub_ss

__m128 _mm_sub_ss( __m128 a, __m128 b )

Synopsis

#include "xmmintrin.h"
Instruction: subss
CPUID Flag: SSE
Category: Arithmetic

Description

Subtract the lower single-precision (32-bit) floating-point element in "b" from the lower single-precision (32-bit) floating-point element in "a", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".

Operation

dst[31:0] := a[31:0] - b[31:0]
dst[127:32] := a[127:32]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 0.5 | 1
Jaguar | 3 | 1 | 1
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 4 | 0.5 | 1
Knights Landing | 6 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 4 | 0.5 |


_mm_subs_epi16

__m128i _mm_subs_epi16( __m128i a, __m128i b )

Synopsis

#include "emmintrin.h"
Instruction: psubsw
CPUID Flag: SSE2
Category: Arithmetic

Description

Subtract packed 16-bit integers in "b" from packed 16-bit integers in "a" using saturation, and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*16
    dst[i+15:i] := Saturate_To_Int16(a[i+15:i] - b[i+15:i])
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.33 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.5 |


_mm_subs_epi8

__m128i _mm_subs_epi8( __m128i a, __m128i b )

Synopsis

#include "emmintrin.h"
Instruction: psubsb
CPUID Flag: SSE2
Category: Arithmetic

Description

Subtract packed 8-bit integers in "b" from packed 8-bit integers in "a" using saturation, and store the results in "dst".

Operation

FOR j := 0 to 15
    i := j*8
    dst[i+7:i] := Saturate_To_Int8(a[i+7:i] - b[i+7:i])
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.33 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.5 |


_mm_subs_epu16

__m128i _mm_subs_epu16( __m128i a, __m128i b )

Synopsis

#include "emmintrin.h"
Instruction: psubusw
CPUID Flag: SSE2
Category: Arithmetic

Description

Subtract packed unsigned 16-bit integers in "b" from packed unsigned 16-bit integers in "a" using saturation, and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*16
    dst[i+15:i] := Saturate_To_UnsignedInt16(a[i+15:i] - b[i+15:i])
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Jaguar | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.33 | 1
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.5 |


_mm_subs_epu8

__m128i _mm_subs_epu8( __m128i a, __m128i b )

Synopsis

#include "emmintrin.h"
Instruction: psubusb
CPUID Flag: SSE2
Category: Arithmetic

Description

Subtract packed unsigned 8-bit integers in "b" from packed unsigned 8-bit integers in "a" using saturation, and store the results in "dst".

Operation

FOR j := 0 to 15
    i := j*8
    dst[i+7:i] := Saturate_To_UnsignedInt8(a[i+7:i] - b[i+7:i])
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Jaguar | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.33 | 1
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.5 |


_mm_subs_pi16

__m64 _mm_subs_pi16( __m64 a, __m64 b )

Synopsis

#include "mmintrin.h"
Instruction: psubsw
CPUID Flag: MMX
Category: Arithmetic

Description

Subtract packed 16-bit integers in "b" from packed 16-bit integers in "a" using saturation, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*16
    dst[i+15:i] := Saturate_To_Int16(a[i+15:i] - b[i+15:i])
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.33 | 1
Knights Landing | 2 | 0.5 | 1


_mm_subs_pi8

__m64 _mm_subs_pi8( __m64 a, __m64 b )

Synopsis

#include "mmintrin.h"
Instruction: psubsb
CPUID Flag: MMX
Category: Arithmetic

Description

Subtract packed 8-bit integers in "b" from packed 8-bit integers in "a" using saturation, and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*8
    dst[i+7:i] := Saturate_To_Int8(a[i+7:i] - b[i+7:i])
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.33 | 1
Knights Landing | 2 | 0.5 | 1


_mm_subs_pu16

__m64 _mm_subs_pu16( __m64 a, __m64 b )

Synopsis

#include "mmintrin.h"
Instruction: psubusw
CPUID Flag: MMX
Category: Arithmetic

Description

Subtract packed unsigned 16-bit integers in "b" from packed unsigned 16-bit integers in "a" using saturation, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*16
    dst[i+15:i] := Saturate_To_UnsignedInt16(a[i+15:i] - b[i+15:i])
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Jaguar | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.33 | 1


_mm_subs_pu8

__m64 _mm_subs_pu8( __m64 a, __m64 b )

Synopsis

#include "mmintrin.h"
Instruction: psubusb
CPUID Flag: MMX
Category: Arithmetic

Description

Subtract packed unsigned 8-bit integers in "b" from packed unsigned 8-bit integers in "a" using saturation, and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*8
    dst[i+7:i] := Saturate_To_UnsignedInt8(a[i+7:i] - b[i+7:i])
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Jaguar | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.33 | 1


_mm_svml_ceil_pd

__m128d _mm_svml_ceil_pd( __m128d a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Special Math Functions

Description

Round the packed double-precision (64-bit) floating-point elements in "a" up to an integer value, and store the results as packed double-precision floating-point elements in "dst". This intrinsic may generate the "roundpd"/"vroundpd" instruction.

Operation

FOR j := 0 to 1
    i := j*64
    dst[i+63:i] := CEIL(a[i+63:i])
ENDFOR
dst[MAX:128] := 0


_mm_svml_ceil_ps

__m128 _mm_svml_ceil_ps( __m128 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Special Math Functions

Description

Round the packed single-precision (32-bit) floating-point elements in "a" up to an integer value, and store the results as packed single-precision floating-point elements in "dst". This intrinsic may generate the "roundps"/"vroundps" instruction.

Operation

FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := CEIL(a[i+31:i])
ENDFOR
dst[MAX:128] := 0


_mm_svml_floor_pd

__m128d _mm_svml_floor_pd( __m128d a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Special Math Functions

Description

Round the packed double-precision (64-bit) floating-point elements in "a" down to an integer value, and store the results as packed double-precision floating-point elements in "dst". This intrinsic may generate the "roundpd"/"vroundpd" instruction.

Operation

FOR j := 0 to 1
    i := j*64
    dst[i+63:i] := FLOOR(a[i+63:i])
ENDFOR
dst[MAX:128] := 0


_mm_svml_floor_ps

__m128 _mm_svml_floor_ps( __m128 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Special Math Functions

Description

Round the packed single-precision (32-bit) floating-point elements in "a" down to an integer value, and store the results as packed single-precision floating-point elements in "dst". This intrinsic may generate the "roundps"/"vroundps" instruction.

Operation

FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := FLOOR(a[i+31:i])
ENDFOR
dst[MAX:128] := 0


_mm_svml_round_pd

__m128d _mm_svml_round_pd( __m128d a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Special Math Functions

Description

Round the packed double-precision (64-bit) floating-point elements in "a" to the nearest integer value, and store the results as packed double-precision floating-point elements in "dst". This intrinsic may generate the "roundpd"/"vroundpd" instruction.

Operation

FOR j := 0 to 1
    i := j*64
    dst[i+63:i] := ROUND(a[i+63:i])
ENDFOR
dst[MAX:128] := 0


_mm_svml_round_ps

__m128 _mm_svml_round_ps( __m128 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Special Math Functions

Description

Round the packed single-precision (32-bit) floating-point elements in "a" to the nearest integer value, and store the results as packed single-precision floating-point elements in "dst". This intrinsic may generate the "roundps"/"vroundps" instruction.

Operation

FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := ROUND(a[i+31:i])
ENDFOR
dst[MAX:128] := 0


_mm_svml_sqrt_pd

__m128d _mm_svml_sqrt_pd( __m128d a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Elementary Math Functions

Description

Compute the square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". Note that this intrinsic is less efficient than "_mm_sqrt_pd".

Operation

FOR j := 0 to 1
    i := j*64
    dst[i+63:i] := SQRT(a[i+63:i])
ENDFOR
dst[MAX:128] := 0


_mm_svml_sqrt_ps

__m128 _mm_svml_sqrt_ps( __m128 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Elementary Math Functions

Description

Compute the square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". Note that this intrinsic is less efficient than "_mm_sqrt_ps".

Operation

FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := SQRT(a[i+31:i])
ENDFOR
dst[MAX:128] := 0


_mm_tan_pd

__m128d _mm_tan_pd( __m128d a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Trigonometry

Description

Compute the tangent of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*64
    dst[i+63:i] := TAN(a[i+63:i])
ENDFOR
dst[MAX:128] := 0


_mm_tan_ps

__m128 _mm_tan_ps( __m128 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Trigonometry

Description

Compute the tangent of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := TAN(a[i+31:i])
ENDFOR
dst[MAX:128] := 0


_mm_tand_pd

__m128d _mm_tand_pd( __m128d a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Trigonometry

Description

Compute the tangent of packed double-precision (64-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*64
    dst[i+63:i] := TAND(a[i+63:i])
ENDFOR
dst[MAX:128] := 0


_mm_tand_ps

__m128 _mm_tand_ps( __m128 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Trigonometry

Description

Compute the tangent of packed single-precision (32-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := TAND(a[i+31:i])
ENDFOR
dst[MAX:128] := 0


_mm_tanh_pd

__m128d _mm_tanh_pd( __m128d a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Trigonometry

Description

Compute the hyperbolic tangent of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*64
    dst[i+63:i] := TANH(a[i+63:i])
ENDFOR
dst[MAX:128] := 0


_mm_tanh_ps

__m128 _mm_tanh_ps( __m128 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Trigonometry

Description

Compute the hyperbolic tangent of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := TANH(a[i+31:i])
ENDFOR
dst[MAX:128] := 0


_mm_test_all_ones

int _mm_test_all_ones( __m128i a )

Synopsis

#include "smmintrin.h"
Instruction: pcmpeqd
CPUID Flag: SSE4.1
Category: Logical

Description

Compute the bitwise NOT of "a" and then AND with a 128-bit vector containing all 1's, and return 1 if the result is zero, otherwise return 0.

Operation

FOR j := 0 to 127
    tmp[j] := 1
ENDFOR
IF ((NOT a[127:0]) AND tmp[127:0] == 0)
    CF := 1
ELSE
    CF := 0
FI
dst := CF

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1


_mm_test_all_zeros

int _mm_test_all_zeros( __m128i a, __m128i mask )

Synopsis

#include "smmintrin.h"
Instruction: ptest
CPUID Flag: SSE4.1
Category: Logical

Description

Compute the bitwise AND of 128 bits (representing integer data) in "a" and "mask", and return 1 if the result is zero, otherwise return 0.

Operation

IF (a[127:0] AND mask[127:0] == 0)
    ZF := 1
ELSE
    ZF := 0
FI
dst := ZF

Performance

Architecture | Latency | Throughput | μops
Ryzen | 2 | 1 | 1
Jaguar | 3 | 1 | 1
Sandy Bridge | 1 | 1 | 1
Ivy Bridge | 1 | 1 | 2
Haswell | 2 | 1 | 2
Broadwell | 2 | 1 | 2
Skylake | 3 | 1 | 2
Knights Landing | 9 | 9 | 4
Ivy Bridge | 2 | 1 |
Haswell | 2 | 1 |
Broadwell | 2 | 1 |
Skylake | 3 | 1 |


_mm_test_mix_ones_zeros

int _mm_test_mix_ones_zeros( __m128i a, __m128i mask )

Synopsis

#include "smmintrin.h"
Instruction: ptest
CPUID Flag: SSE4.1
Category: Logical

Description

Compute the bitwise AND of 128 bits (representing integer data) in "a" and "mask", and set "ZF" to 1 if the result is zero, otherwise set "ZF" to 0. Compute the bitwise NOT of "a" and then AND with "mask", and set "CF" to 1 if the result is zero, otherwise set "CF" to 0. Return 1 if both the "ZF" and "CF" values are zero, otherwise return 0.

Operation

IF (a[127:0] AND mask[127:0] == 0)
    ZF := 1
ELSE
    ZF := 0
FI
IF ((NOT a[127:0]) AND mask[127:0] == 0)
    CF := 1
ELSE
    CF := 0
FI
IF (ZF == 0 && CF == 0)
    dst := 1
ELSE
    dst := 0
FI

Performance

Architecture | Latency | Throughput | μops
Ryzen | 2 | 1 | 1
Jaguar | 3 | 1 | 1
Sandy Bridge | 1 | 1 | 1
Ivy Bridge | 1 | 1 | 2
Haswell | 2 | 1 | 2
Broadwell | 2 | 1 | 2
Skylake | 3 | 1 | 2
Knights Landing | 9 | 9 | 4
Ivy Bridge | 2 | 1 |
Haswell | 2 | 1 |
Broadwell | 2 | 1 |
Skylake | 3 | 1 |


_mm_testc_pd

int _mm_testc_pd( __m128d a, __m128d b )

Synopsis

#include "immintrin.h"
Instruction: vtestpd
CPUID Flag: AVX
Category: Logical

Description

Compute the bitwise AND of 128 bits (representing double-precision (64-bit) floating-point elements) in "a" and "b", producing an intermediate 128-bit value, and set "ZF" to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set "ZF" to 0. Compute the bitwise NOT of "a" and then AND with "b", producing an intermediate value, and set "CF" to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set "CF" to 0. Return the "CF" value.

Operation

tmp[127:0] := a[127:0] AND b[127:0]
IF (tmp[63] == tmp[127] == 0)
    ZF := 1
ELSE
    ZF := 0
FI
tmp[127:0] := (NOT a[127:0]) AND b[127:0]
IF (tmp[63] == tmp[127] == 0)
    CF := 1
ELSE
    CF := 0
FI
dst := CF


_mm_testc_ps

int _mm_testc_ps( __m128 a, __m128 b )

Synopsis

#include "immintrin.h"
Instruction: vtestps
CPUID Flag: AVX
Category: Logical

Description

Compute the bitwise AND of 128 bits (representing single-precision (32-bit) floating-point elements) in "a" and "b", producing an intermediate 128-bit value, and set "ZF" to 1 if the sign bit of each 32-bit element in the intermediate value is zero, otherwise set "ZF" to 0. Compute the bitwise NOT of "a" and then AND with "b", producing an intermediate value, and set "CF" to 1 if the sign bit of each 32-bit element in the intermediate value is zero, otherwise set "CF" to 0. Return the "CF" value.

Operation

tmp[127:0] := a[127:0] AND b[127:0]
IF (tmp[31] == tmp[63] == tmp[95] == tmp[127] == 0)
    ZF := 1
ELSE
    ZF := 0
FI
tmp[127:0] := (NOT a[127:0]) AND b[127:0]
IF (tmp[31] == tmp[63] == tmp[95] == tmp[127] == 0)
    CF := 1
ELSE
    CF := 0
FI
dst := CF

Performance

Architecture | Latency | Throughput | μops
Ivy Bridge | 2 | 1 |
Haswell | 2 | 1 |
Broadwell | 2 | 1 |
Skylake | 3 | 1 |


_mm_testc_si128

int _mm_testc_si128( __m128i a, __m128i b )

Synopsis

#include "smmintrin.h"
Instruction: ptest
CPUID Flag: SSE4.1
Category: Logical

Description

Compute the bitwise AND of 128 bits (representing integer data) in "a" and "b", and set "ZF" to 1 if the result is zero, otherwise set "ZF" to 0. Compute the bitwise NOT of "a" and then AND with "b", and set "CF" to 1 if the result is zero, otherwise set "CF" to 0. Return the "CF" value.

Operation

IF (a[127:0] AND b[127:0] == 0)
    ZF := 1
ELSE
    ZF := 0
FI
IF ((NOT a[127:0]) AND b[127:0] == 0)
    CF := 1
ELSE
    CF := 0
FI
RETURN CF

Performance

Architecture | Latency | Throughput | μops
Ryzen | 2 | 1 | 1
Jaguar | 3 | 1 | 1
Sandy Bridge | 1 | 1 | 1
Ivy Bridge | 1 | 1 | 2
Haswell | 2 | 1 | 2
Broadwell | 2 | 1 | 2
Skylake | 3 | 1 | 2
Knights Landing | 9 | 9 | 4
Ivy Bridge | 2 | 1 |
Haswell | 2 | 1 |
Broadwell | 2 | 1 |
Skylake | 3 | 1 |


_mm_testnzc_pd

int _mm_testnzc_pd( __m128d a, __m128d b )

Synopsis

#include "immintrin.h"
Instruction: vtestpd
CPUID Flag: AVX
Category: Logical

Description

Compute the bitwise AND of 128 bits (representing double-precision (64-bit) floating-point elements) in "a" and "b", producing an intermediate 128-bit value, and set "ZF" to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set "ZF" to 0. Compute the bitwise NOT of "a" and then AND with "b", producing an intermediate value, and set "CF" to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set "CF" to 0. Return 1 if both the "ZF" and "CF" values are zero, otherwise return 0.

Operation

tmp[127:0] := a[127:0] AND b[127:0]
IF (tmp[63] == tmp[127] == 0)
    ZF := 1
ELSE
    ZF := 0
FI
tmp[127:0] := (NOT a[127:0]) AND b[127:0]
IF (tmp[63] == tmp[127] == 0)
    CF := 1
ELSE
    CF := 0
FI
IF (ZF == 0 && CF == 0)
    dst := 1
ELSE
    dst := 0
FI


_mm_testnzc_ps

int _mm_testnzc_ps( __m128 a, __m128 b )

Synopsis

#include "immintrin.h"
Instruction: vtestps
CPUID Flag: AVX
Category: Logical

Description

Compute the bitwise AND of 128 bits (representing single-precision (32-bit) floating-point elements) in "a" and "b", producing an intermediate 128-bit value, and set "ZF" to 1 if the sign bit of each 32-bit element in the intermediate value is zero, otherwise set "ZF" to 0. Compute the bitwise NOT of "a" and then AND with "b", producing an intermediate value, and set "CF" to 1 if the sign bit of each 32-bit element in the intermediate value is zero, otherwise set "CF" to 0. Return 1 if both the "ZF" and "CF" values are zero, otherwise return 0.

Operation

tmp[127:0] := a[127:0] AND b[127:0]
IF (tmp[31] == tmp[63] == tmp[95] == tmp[127] == 0)
    ZF := 1
ELSE
    ZF := 0
FI
tmp[127:0] := (NOT a[127:0]) AND b[127:0]
IF (tmp[31] == tmp[63] == tmp[95] == tmp[127] == 0)
    CF := 1
ELSE
    CF := 0
FI
IF (ZF == 0 && CF == 0)
    dst := 1
ELSE
    dst := 0
FI

Performance

Architecture | Latency | Throughput | μops
Ivy Bridge | 2 | 1 |
Haswell | 2 | 1 |
Broadwell | 2 | 1 |
Skylake | 3 | 1 |


_mm_testnzc_si128

int _mm_testnzc_si128( __m128i a, __m128i b )

Synopsis

#include "smmintrin.h"
Instruction: ptest
CPUID Flag: SSE4.1
Category: Logical

Description

Compute the bitwise AND of 128 bits (representing integer data) in "a" and "b", and set "ZF" to 1 if the result is zero, otherwise set "ZF" to 0. Compute the bitwise NOT of "a" and then AND with "b", and set "CF" to 1 if the result is zero, otherwise set "CF" to 0. Return 1 if both the "ZF" and "CF" values are zero, otherwise return 0.

Operation

IF (a[127:0] AND b[127:0] == 0)
    ZF := 1
ELSE
    ZF := 0
FI
IF ((NOT a[127:0]) AND b[127:0] == 0)
    CF := 1
ELSE
    CF := 0
FI
IF (ZF == 0 && CF == 0)
    dst := 1
ELSE
    dst := 0
FI

Performance

Architecture | Latency | Throughput | μops
Ryzen | 2 | 1 | 1
Jaguar | 3 | 1 | 1
Sandy Bridge | 1 | 1 | 1
Ivy Bridge | 1 | 1 | 2
Haswell | 2 | 1 | 2
Broadwell | 2 | 1 | 2
Skylake | 3 | 1 | 2
Knights Landing | 9 | 9 | 4
Ivy Bridge | 2 | 1 |
Haswell | 2 | 1 |
Broadwell | 2 | 1 |
Skylake | 3 | 1 |


_mm_testz_pd

int _mm_testz_pd( __m128d a, __m128d b )

Synopsis

#include "immintrin.h"
Instruction: vtestpd
CPUID Flag: AVX
Category: Logical

Description

Compute the bitwise AND of 128 bits (representing double-precision (64-bit) floating-point elements) in "a" and "b", producing an intermediate 128-bit value, and set "ZF" to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set "ZF" to 0. Compute the bitwise NOT of "a" and then AND with "b", producing an intermediate value, and set "CF" to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set "CF" to 0. Return the "ZF" value.

Operation

tmp[127:0] := a[127:0] AND b[127:0]
IF (tmp[63] == tmp[127] == 0)
    ZF := 1
ELSE
    ZF := 0
FI
tmp[127:0] := (NOT a[127:0]) AND b[127:0]
IF (tmp[63] == tmp[127] == 0)
    CF := 1
ELSE
    CF := 0
FI
dst := ZF


_mm_testz_ps

int _mm_testz_ps( __m128 a, __m128 b )

Synopsis

#include "immintrin.h"
Instruction: vtestps
CPUID Flag: AVX
Category: Logical

Description

Compute the bitwise AND of 128 bits (representing single-precision (32-bit) floating-point elements) in "a" and "b", producing an intermediate 128-bit value, and set "ZF" to 1 if the sign bit of each 32-bit element in the intermediate value is zero, otherwise set "ZF" to 0. Compute the bitwise NOT of "a" and then AND with "b", producing an intermediate value, and set "CF" to 1 if the sign bit of each 32-bit element in the intermediate value is zero, otherwise set "CF" to 0. Return the "ZF" value.

Operation

tmp[127:0] := a[127:0] AND b[127:0]
IF (tmp[31] == tmp[63] == tmp[95] == tmp[127] == 0)
    ZF := 1
ELSE
    ZF := 0
FI
tmp[127:0] := (NOT a[127:0]) AND b[127:0]
IF (tmp[31] == tmp[63] == tmp[95] == tmp[127] == 0)
    CF := 1
ELSE
    CF := 0
FI
dst := ZF

Performance

Architecture | Latency | Throughput | μops
Ivy Bridge | 2 | 1 |
Haswell | 2 | 1 |
Broadwell | 2 | 1 |
Skylake | 3 | 1 |


_mm_testz_si128

int _mm_testz_si128( __m128i a, __m128i b )

Synopsis

#include "smmintrin.h"
Instruction: ptest
CPUID Flag: SSE4.1
Category: Logical

Description

Compute the bitwise AND of 128 bits (representing integer data) in "a" and "b", and set "ZF" to 1 if the result is zero, otherwise set "ZF" to 0. Compute the bitwise NOT of "a" and then AND with "b", and set "CF" to 1 if the result is zero, otherwise set "CF" to 0. Return the "ZF" value.

Operation

IF (a[127:0] AND b[127:0] == 0)
    ZF := 1
ELSE
    ZF := 0
FI
IF ((NOT a[127:0]) AND b[127:0] == 0)
    CF := 1
ELSE
    CF := 0
FI
RETURN ZF

Performance

Architecture | Latency | Throughput | μops
Ryzen | 2 | 1 | 1
Jaguar | 3 | 1 | 1
Sandy Bridge | 1 | 1 | 1
Ivy Bridge | 1 | 1 | 2
Haswell | 2 | 1 | 2
Broadwell | 2 | 1 | 2
Skylake | 3 | 1 | 2
Knights Landing | 9 | 9 | 4
Ivy Bridge | 2 | 1 |
Haswell | 2 | 1 |
Broadwell | 2 | 1 |
Skylake | 3 | 1 |


_MM_TRANSPOSE4_PS

_MM_TRANSPOSE4_PS( __m128 row0, __m128 row1, __m128 row2, __m128 row3 )

Synopsis

#include "xmmintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Swizzle

Description

Macro: Transpose the 4x4 matrix formed by the 4 rows of single-precision (32-bit) floating-point elements in "row0", "row1", "row2", and "row3", and store the transposed matrix in these vectors ("row0" now contains column 0, etc.).

Operation

__m128 tmp3, tmp2, tmp1, tmp0;
tmp0 := _mm_unpacklo_ps(row0, row1);
tmp2 := _mm_unpacklo_ps(row2, row3);
tmp1 := _mm_unpackhi_ps(row0, row1);
tmp3 := _mm_unpackhi_ps(row2, row3);
row0 := _mm_movelh_ps(tmp0, tmp2);
row1 := _mm_movehl_ps(tmp2, tmp0);
row2 := _mm_movelh_ps(tmp1, tmp3);
row3 := _mm_movehl_ps(tmp3, tmp1);


_mm_trunc_pd

__m128d _mm_trunc_pd( __m128d a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Miscellaneous

Description

Truncate the packed double-precision (64-bit) floating-point elements in "a", and store the results as packed double-precision floating-point elements in "dst". This intrinsic may generate the "roundpd"/"vroundpd" instruction.

Operation

FOR j := 0 to 1
    i := j*64
    dst[i+63:i] := TRUNCATE(a[i+63:i])
ENDFOR
dst[MAX:128] := 0


_mm_trunc_ps

__m128 _mm_trunc_ps( __m128 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Miscellaneous

Description

Truncate the packed single-precision (32-bit) floating-point elements in "a", and store the results as packed single-precision floating-point elements in "dst". This intrinsic may generate the "roundps"/"vroundps" instruction.

Operation

FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := TRUNCATE(a[i+31:i])
ENDFOR
dst[MAX:128] := 0


_mm_tzcnt_32

int _mm_tzcnt_32( unsigned int a )

Synopsis

#include "immintrin.h"
Instruction: tzcnt
CPUID Flag: BMI1
Category: Bit Manipulation

Description

Count the number of trailing zero bits in unsigned 32-bit integer "a", and return that count in "dst".

Operation

tmp := 0
dst := 0
DO WHILE ((tmp < 32) AND a[tmp] == 0)
    tmp := tmp + 1
    dst := dst + 1
OD

Performance

Architecture | Latency | Throughput | μops
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 3 | 1 |


_mm_tzcnt_64

__int64 _mm_tzcnt_64( unsigned __int64 a )

Synopsis

#include "immintrin.h"
Instruction: tzcnt
CPUID Flag: BMI1
Category: Bit Manipulation

Description

Count the number of trailing zero bits in unsigned 64-bit integer "a", and return that count in "dst".

Operation

tmp := 0
dst := 0
DO WHILE ((tmp < 64) AND a[tmp] == 0)
    tmp := tmp + 1
    dst := dst + 1
OD

Performance

Architecture | Latency | Throughput | μops
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 3 | 1 |


_mm_ucomieq_sd

int _mm_ucomieq_sd( __m128d a, __m128d b )

Synopsis

#include "emmintrin.h"
Instruction: ucomisd
CPUID Flag: SSE2
Category: Compare

Description

Compare the lower double-precision (64-bit) floating-point element in "a" and "b" for equality, and return the boolean result (0 or 1). This instruction will not signal an exception for QNaNs.

Operation

RETURN ( a[63:0] == b[63:0] ) ? 1 : 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 4 | 1 | 2
Jaguar |  | 1 | 1
Sandy Bridge | 2 | 1 | 2
Ivy Bridge |  | 1 | 2
Haswell |  | 1 | 1
Broadwell |  | 1 | 1
Skylake |  | 1 | 1
Knights Landing | 7 | 7 | 2
Ivy Bridge | 2 | 1 |
Haswell | 2 | 1 |
Broadwell | 2 | 1 |
Skylake | 2 | 1 |


_mm_ucomieq_ss

int _mm_ucomieq_ss( __m128 a, __m128 b )

Synopsis

#include "xmmintrin.h"
Instruction: ucomiss
CPUID Flag: SSE
Category: Compare

Description

Compare the lower single-precision (32-bit) floating-point element in "a" and "b" for equality, and return the boolean result (0 or 1). This instruction will not signal an exception for QNaNs.

Operation

RETURN ( a[31:0] == b[31:0] ) ? 1 : 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 4 | 1 | 2
Jaguar |  | 1 | 1
Sandy Bridge | 2 | 1 | 2
Ivy Bridge |  | 1 | 2
Haswell |  | 1 | 1
Broadwell |  | 1 | 1
Skylake |  | 1 | 1
Knights Landing | 7 | 7 | 2
Ivy Bridge | 2 | 1 |
Haswell | 2 | 1 |
Broadwell | 2 | 1 |
Skylake | 2 | 1 |


_mm_ucomige_sd

int _mm_ucomige_sd( __m128d a, __m128d b )

Synopsis

#include "emmintrin.h"
Instruction: ucomisd
CPUID Flag: SSE2
Category: Compare

Description

Compare the lower double-precision (64-bit) floating-point element in "a" and "b" for greater-than-or-equal, and return the boolean result (0 or 1). This instruction will not signal an exception for QNaNs.

Operation

RETURN ( a[63:0] >= b[63:0] ) ? 1 : 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 4 | 1 | 2
Jaguar |  | 1 | 1
Sandy Bridge | 2 | 1 | 2
Ivy Bridge |  | 1 | 2
Haswell |  | 1 | 1
Broadwell |  | 1 | 1
Skylake |  | 1 | 1
Knights Landing | 7 | 7 | 2
Ivy Bridge | 2 | 1 |
Haswell | 2 | 1 |
Broadwell | 2 | 1 |
Skylake | 2 | 1 |


_mm_ucomige_ss

int _mm_ucomige_ss( __m128 a, __m128 b )

Synopsis

#include "xmmintrin.h"
Instruction: ucomiss
CPUID Flag: SSE
Category: Compare

Description

Compare the lower single-precision (32-bit) floating-point element in "a" and "b" for greater-than-or-equal, and return the boolean result (0 or 1). This instruction will not signal an exception for QNaNs.

Operation

RETURN ( a[31:0] >= b[31:0] ) ? 1 : 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 4 | 1 | 2
Jaguar |  | 1 | 1
Sandy Bridge | 2 | 1 | 2
Ivy Bridge |  | 1 | 2
Haswell |  | 1 | 1
Broadwell |  | 1 | 1
Skylake |  | 1 | 1
Knights Landing | 7 | 7 | 2
Ivy Bridge | 2 | 1 |
Haswell | 2 | 1 |
Broadwell | 2 | 1 |
Skylake | 2 | 1 |


_mm_ucomigt_sd

int _mm_ucomigt_sd( __m128d a, __m128d b )

Synopsis

#include "emmintrin.h"
Instruction: ucomisd
CPUID Flag: SSE2
Category: Compare

Description

Compare the lower double-precision (64-bit) floating-point element in "a" and "b" for greater-than, and return the boolean result (0 or 1). This instruction will not signal an exception for QNaNs.

Operation

RETURN ( a[63:0] > b[63:0] ) ? 1 : 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 4 | 1 | 2
Jaguar |  | 1 | 1
Sandy Bridge | 2 | 1 | 2
Ivy Bridge |  | 1 | 2
Haswell |  | 1 | 1
Broadwell |  | 1 | 1
Skylake |  | 1 | 1
Knights Landing | 7 | 7 | 2
Ivy Bridge | 2 | 1 |
Haswell | 2 | 1 |
Broadwell | 2 | 1 |
Skylake | 2 | 1 |


_mm_ucomigt_ss

int _mm_ucomigt_ss( __m128 a, __m128 b )

Synopsis

#include "xmmintrin.h"
Instruction: ucomiss
CPUID Flag: SSE
Category: Compare

Description

Compare the lower single-precision (32-bit) floating-point element in "a" and "b" for greater-than, and return the boolean result (0 or 1). This instruction will not signal an exception for QNaNs.

Operation

RETURN ( a[31:0] > b[31:0] ) ? 1 : 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 4 | 1 | 2
Jaguar |  | 1 | 1
Sandy Bridge | 2 | 1 | 2
Ivy Bridge |  | 1 | 2
Haswell |  | 1 | 1
Broadwell |  | 1 | 1
Skylake |  | 1 | 1
Knights Landing | 7 | 7 | 2
Ivy Bridge | 2 | 1 |
Haswell | 2 | 1 |
Broadwell | 2 | 1 |
Skylake | 2 | 1 |


_mm_ucomile_sd

int _mm_ucomile_sd( __m128d a, __m128d b )

Synopsis

#include "emmintrin.h"
Instruction: ucomisd
CPUID Flag: SSE2
Category: Compare

Description

Compare the lower double-precision (64-bit) floating-point element in "a" and "b" for less-than-or-equal, and return the boolean result (0 or 1). This instruction will not signal an exception for QNaNs.

Operation

RETURN ( a[63:0] <= b[63:0] ) ? 1 : 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 4 | 1 | 2
Jaguar |  | 1 | 1
Sandy Bridge | 2 | 1 | 2
Ivy Bridge |  | 1 | 2
Haswell |  | 1 | 1
Broadwell |  | 1 | 1
Skylake |  | 1 | 1
Knights Landing | 7 | 7 | 2
Ivy Bridge | 2 | 1 |
Haswell | 2 | 1 |
Broadwell | 2 | 1 |
Skylake | 2 | 1 |


_mm_ucomile_ss

int _mm_ucomile_ss( __m128 a, __m128 b )

Synopsis

#include "xmmintrin.h"
Instruction: ucomiss
CPUID Flag: SSE
Category: Compare

Description

Compare the lower single-precision (32-bit) floating-point element in "a" and "b" for less-than-or-equal, and return the boolean result (0 or 1). This instruction will not signal an exception for QNaNs.

Operation

RETURN ( a[31:0] <= b[31:0] ) ? 1 : 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 4 | 1 | 2
Jaguar |  | 1 | 1
Sandy Bridge | 2 | 1 | 2
Ivy Bridge |  | 1 | 2
Haswell |  | 1 | 1
Broadwell |  | 1 | 1
Skylake |  | 1 | 1
Knights Landing | 7 | 7 | 2
Ivy Bridge | 2 | 1 |
Haswell | 2 | 1 |
Broadwell | 2 | 1 |
Skylake | 2 | 1 |


_mm_ucomilt_sd

int _mm_ucomilt_sd( __m128d a, __m128d b )

Synopsis

#include "emmintrin.h"
Instruction: ucomisd
CPUID Flag: SSE2
Category: Compare

Description

Compare the lower double-precision (64-bit) floating-point element in "a" and "b" for less-than, and return the boolean result (0 or 1). This instruction will not signal an exception for QNaNs.

Operation

RETURN ( a[63:0] < b[63:0] ) ? 1 : 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 4 | 1 | 2
Jaguar |  | 1 | 1
Sandy Bridge | 2 | 1 | 2
Ivy Bridge |  | 1 | 2
Haswell |  | 1 | 1
Broadwell |  | 1 | 1
Skylake |  | 1 | 1
Knights Landing | 7 | 7 | 2
Ivy Bridge | 2 | 1 |
Haswell | 2 | 1 |
Broadwell | 2 | 1 |
Skylake | 2 | 1 |


_mm_ucomilt_ss

int _mm_ucomilt_ss( __m128 a, __m128 b )

Synopsis

#include "xmmintrin.h"
Instruction: ucomiss
CPUID Flag: SSE
Category: Compare

Description

Compare the lower single-precision (32-bit) floating-point element in "a" and "b" for less-than, and return the boolean result (0 or 1). This instruction will not signal an exception for QNaNs.

Operation

RETURN ( a[31:0] < b[31:0] ) ? 1 : 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 4 | 1 | 2
Jaguar |  | 1 | 1
Sandy Bridge | 2 | 1 | 2
Ivy Bridge |  | 1 | 2
Haswell |  | 1 | 1
Broadwell |  | 1 | 1
Skylake |  | 1 | 1
Knights Landing | 7 | 7 | 2
Ivy Bridge | 2 | 1 |
Haswell | 2 | 1 |
Broadwell | 2 | 1 |
Skylake | 2 | 1 |


_mm_ucomineq_sd

int _mm_ucomineq_sd( __m128d a, __m128d b )

Synopsis

#include "emmintrin.h"
Instruction: ucomisd
CPUID Flag: SSE2
Category: Compare

Description

Compare the lower double-precision (64-bit) floating-point element in "a" and "b" for not-equal, and return the boolean result (0 or 1). This instruction will not signal an exception for QNaNs.

Operation

RETURN ( a[63:0] != b[63:0] ) ? 1 : 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 4 | 1 | 2
Jaguar |  | 1 | 1
Sandy Bridge | 2 | 1 | 2
Ivy Bridge |  | 1 | 2
Haswell |  | 1 | 1
Broadwell |  | 1 | 1
Skylake |  | 1 | 1
Knights Landing | 7 | 7 | 2
Ivy Bridge | 2 | 1 |
Haswell | 2 | 1 |
Broadwell | 2 | 1 |
Skylake | 2 | 1 |


_mm_ucomineq_ss

int _mm_ucomineq_ss( __m128 a, __m128 b )

Synopsis

#include "xmmintrin.h"
Instruction: ucomiss
CPUID Flag: SSE
Category: Compare

Description

Compare the lower single-precision (32-bit) floating-point element in "a" and "b" for not-equal, and return the boolean result (0 or 1). This instruction will not signal an exception for QNaNs.

Operation

RETURN ( a[31:0] != b[31:0] ) ? 1 : 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 4 | 1 | 2
Jaguar |  | 1 | 1
Sandy Bridge | 2 | 1 | 2
Ivy Bridge |  | 1 | 2
Haswell |  | 1 | 1
Broadwell |  | 1 | 1
Skylake |  | 1 | 1
Knights Landing | 7 | 7 | 2
Ivy Bridge | 2 | 1 |
Haswell | 2 | 1 |
Broadwell | 2 | 1 |
Skylake | 2 | 1 |


_mm_udiv_epi32

__m128i _mm_udiv_epi32( __m128i a, __m128i b )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Arithmetic

Description

Divide packed unsigned 32-bit integers in "a" by packed elements in "b", and store the truncated results in "dst".

Operation

FOR j := 0 to 3
    i := 32*j
    dst[i+31:i] := TRUNCATE(a[i+31:i] / b[i+31:i])
ENDFOR
dst[MAX:128] := 0


_mm_udivrem_epi32

__m128i _mm_udivrem_epi32( __m128i * mem_addr, __m128i a, __m128i b )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Arithmetic

Description

Divide packed unsigned 32-bit integers in "a" by packed elements in "b", store the truncated results in "dst", and store the remainders as packed unsigned 32-bit integers into memory at "mem_addr".

Operation

FOR j := 0 to 3
    i := 32*j
    dst[i+31:i] := TRUNCATE(a[i+31:i] / b[i+31:i])
    MEM[mem_addr+i+31:mem_addr+i] := REMAINDER(a[i+31:i] / b[i+31:i])
ENDFOR
dst[MAX:128] := 0


_mm_undefined_pd

__m128d _mm_undefined_pd( void )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE2
Category: General Support

Description

Return vector of type __m128d with undefined elements.


_mm_undefined_ps

__m128 _mm_undefined_ps( void )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: General Support

Description

Return vector of type __m128 with undefined elements.


_mm_undefined_si128

__m128i _mm_undefined_si128( void )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE2
Category: General Support

Description

Return vector of type __m128i with undefined elements.


_mm_unpackhi_epi16

__m128i _mm_unpackhi_epi16( __m128i a, __m128i b )

Synopsis

#include "emmintrin.h"
Instruction: punpckhwd
CPUID Flag: SSE2
Category: Swizzle

Description

Unpack and interleave 16-bit integers from the high half of "a" and "b", and store the results in "dst".

Operation

DEFINE INTERLEAVE_HIGH_WORDS(src1[127:0], src2[127:0]) {
    dst[15:0] := src1[79:64]
    dst[31:16] := src2[79:64]
    dst[47:32] := src1[95:80]
    dst[63:48] := src2[95:80]
    dst[79:64] := src1[111:96]
    dst[95:80] := src2[111:96]
    dst[111:96] := src1[127:112]
    dst[127:112] := src2[127:112]
    RETURN dst[127:0]
}
dst[127:0] := INTERLEAVE_HIGH_WORDS(a[127:0], b[127:0])

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 2-6 | 1 | 1
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm_unpackhi_epi32

__m128i _mm_unpackhi_epi32( __m128i a, __m128i b )

Synopsis

#include "emmintrin.h"
Instruction: punpckhdq
CPUID Flag: SSE2
Category: Swizzle

Description

Unpack and interleave 32-bit integers from the high half of "a" and "b", and store the results in "dst".

Operation

DEFINE INTERLEAVE_HIGH_DWORDS(src1[127:0], src2[127:0]) {
    dst[31:0] := src1[95:64]
    dst[63:32] := src2[95:64]
    dst[95:64] := src1[127:96]
    dst[127:96] := src2[127:96]
    RETURN dst[127:0]
}
dst[127:0] := INTERLEAVE_HIGH_DWORDS(a[127:0], b[127:0])

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 2-6 | 1 | 1
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm_unpackhi_epi64

__m128i _mm_unpackhi_epi64( __m128i a, __m128i b )

Synopsis

#include "emmintrin.h"
Instruction: punpckhqdq
CPUID Flag: SSE2
Category: Swizzle

Description

Unpack and interleave 64-bit integers from the high half of "a" and "b", and store the results in "dst".

Operation

DEFINE INTERLEAVE_HIGH_QWORDS(src1[127:0], src2[127:0]) {
    dst[63:0] := src1[127:64]
    dst[127:64] := src2[127:64]
    RETURN dst[127:0]
}
dst[127:0] := INTERLEAVE_HIGH_QWORDS(a[127:0], b[127:0])

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 2-6 | 1 | 1
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm_unpackhi_epi8

__m128i _mm_unpackhi_epi8( __m128i a, __m128i b )

Synopsis

#include "emmintrin.h"
Instruction: punpckhbw
CPUID Flag: SSE2
Category: Swizzle

Description

Unpack and interleave 8-bit integers from the high half of "a" and "b", and store the results in "dst".

Operation

DEFINE INTERLEAVE_HIGH_BYTES(src1[127:0], src2[127:0]) {
    dst[7:0] := src1[71:64]
    dst[15:8] := src2[71:64]
    dst[23:16] := src1[79:72]
    dst[31:24] := src2[79:72]
    dst[39:32] := src1[87:80]
    dst[47:40] := src2[87:80]
    dst[55:48] := src1[95:88]
    dst[63:56] := src2[95:88]
    dst[71:64] := src1[103:96]
    dst[79:72] := src2[103:96]
    dst[87:80] := src1[111:104]
    dst[95:88] := src2[111:104]
    dst[103:96] := src1[119:112]
    dst[111:104] := src2[119:112]
    dst[119:112] := src1[127:120]
    dst[127:120] := src2[127:120]
    RETURN dst[127:0]
}
dst[127:0] := INTERLEAVE_HIGH_BYTES(a[127:0], b[127:0])

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 2-6 | 1 | 1
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm_unpackhi_pd

__m128d _mm_unpackhi_pd( __m128d a, __m128d b )

Synopsis

#include "emmintrin.h"
Instruction: unpckhpd
CPUID Flag: SSE2
Category: Swizzle

Description

Unpack and interleave double-precision (64-bit) floating-point elements from the high half of "a" and "b", and store the results in "dst".

Operation

DEFINE INTERLEAVE_HIGH_QWORDS(src1[127:0], src2[127:0]) {
    dst[63:0] := src1[127:64]
    dst[127:64] := src2[127:64]
    RETURN dst[127:0]
}
dst[127:0] := INTERLEAVE_HIGH_QWORDS(a[127:0], b[127:0])

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 1 | 1 | 1
Ivy Bridge | 1 | 1 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 2 | 2 | 1
Ivy Bridge | 1 | 1 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm_unpackhi_pi16

__m64 _mm_unpackhi_pi16( __m64 a, __m64 b )

Synopsis

#include "mmintrin.h"
Instruction: punpcklbw
CPUID Flag: MMX
Category: Swizzle

Description

Unpack and interleave 16-bit integers from the high half of "a" and "b", and store the results in "dst".

Operation

DEFINE INTERLEAVE_HIGH_WORDS(src1[63:0], src2[63:0]) {
    dst[15:0] := src1[47:32]
    dst[31:16] := src2[47:32]
    dst[47:32] := src1[63:48]
    dst[63:48] := src2[63:48]
    RETURN dst[63:0]
}
dst[63:0] := INTERLEAVE_HIGH_WORDS(a[63:0], b[63:0])

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 2-6 | 1 | 1


_mm_unpackhi_pi32

__m64 _mm_unpackhi_pi32( __m64 a, __m64 b )

Synopsis

#include "mmintrin.h"
Instruction: punpckhdq
CPUID Flag: MMX
Category: Swizzle

Description

Unpack and interleave 32-bit integers from the high half of "a" and "b", and store the results in "dst".

Operation

dst[31:0] := a[63:32]
dst[63:32] := b[63:32]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 2-6 | 1 | 1


_mm_unpackhi_pi8

__m64 _mm_unpackhi_pi8( __m64 a, __m64 b )

Synopsis

#include "mmintrin.h"
Instruction: punpckhbw
CPUID Flag: MMX
Category: Swizzle

Description

Unpack and interleave 8-bit integers from the high half of "a" and "b", and store the results in "dst".

Operation

DEFINE INTERLEAVE_HIGH_BYTES(src1[63:0], src2[63:0]) {
    dst[7:0] := src1[39:32]
    dst[15:8] := src2[39:32]
    dst[23:16] := src1[47:40]
    dst[31:24] := src2[47:40]
    dst[39:32] := src1[55:48]
    dst[47:40] := src2[55:48]
    dst[55:48] := src1[63:56]
    dst[63:56] := src2[63:56]
    RETURN dst[63:0]
}
dst[63:0] := INTERLEAVE_HIGH_BYTES(a[63:0], b[63:0])

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 2-6 | 1 | 1


_mm_unpackhi_ps

__m128 _mm_unpackhi_ps( __m128 a, __m128 b )

Synopsis

#include "xmmintrin.h"
Instruction: unpckhps
CPUID Flag: SSE
Category: Swizzle

Description

Unpack and interleave single-precision (32-bit) floating-point elements from the high half "a" and "b", and store the results in "dst".

Operation

DEFINE INTERLEAVE_HIGH_DWORDS(src1[127:0], src2[127:0]) {
    dst[31:0] := src1[95:64]
    dst[63:32] := src2[95:64]
    dst[95:64] := src1[127:96]
    dst[127:96] := src2[127:96]
    RETURN dst[127:0]
}
dst[127:0] := INTERLEAVE_HIGH_DWORDS(a[127:0], b[127:0])

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 1 | 1 | 1
Ivy Bridge | 1 | 1 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 2 | 2 | 1
Ivy Bridge | 1 | 1 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm_unpacklo_epi16

__m128i _mm_unpacklo_epi16( __m128i a, __m128i b )

Synopsis

#include "emmintrin.h"
Instruction: punpcklwd
CPUID Flag: SSE2
Category: Swizzle

Description

Unpack and interleave 16-bit integers from the low half of "a" and "b", and store the results in "dst".

Operation

DEFINE INTERLEAVE_WORDS(src1[127:0], src2[127:0]) {
    dst[15:0] := src1[15:0]
    dst[31:16] := src2[15:0]
    dst[47:32] := src1[31:16]
    dst[63:48] := src2[31:16]
    dst[79:64] := src1[47:32]
    dst[95:80] := src2[47:32]
    dst[111:96] := src1[63:48]
    dst[127:112] := src2[63:48]
    RETURN dst[127:0]
}
dst[127:0] := INTERLEAVE_WORDS(a[127:0], b[127:0])

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 2-6 | 1 | 1
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm_unpacklo_epi32

__m128i _mm_unpacklo_epi32( __m128i a, __m128i b )

Synopsis

#include "emmintrin.h"
Instruction: punpckldq
CPUID Flag: SSE2
Category: Swizzle

Description

Unpack and interleave 32-bit integers from the low half of "a" and "b", and store the results in "dst".

Operation

DEFINE INTERLEAVE_DWORDS(src1[127:0], src2[127:0]) {
    dst[31:0] := src1[31:0]
    dst[63:32] := src2[31:0]
    dst[95:64] := src1[63:32]
    dst[127:96] := src2[63:32]
    RETURN dst[127:0]
}
dst[127:0] := INTERLEAVE_DWORDS(a[127:0], b[127:0])

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 2-6 | 1 | 1
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm_unpacklo_epi64

__m128i _mm_unpacklo_epi64( __m128i a, __m128i b )

Synopsis

#include "emmintrin.h"
Instruction: punpcklqdq
CPUID Flag: SSE2
Category: Swizzle

Description

Unpack and interleave 64-bit integers from the low half of "a" and "b", and store the results in "dst".

Operation

DEFINE INTERLEAVE_QWORDS(src1[127:0], src2[127:0]) {
    dst[63:0] := src1[63:0]
    dst[127:64] := src2[63:0]
    RETURN dst[127:0]
}
dst[127:0] := INTERLEAVE_QWORDS(a[127:0], b[127:0])

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 2-6 | 1 | 1
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm_unpacklo_epi8

__m128i _mm_unpacklo_epi8( __m128i a, __m128i b )

Synopsis

#include "emmintrin.h"
Instruction: punpcklbw
CPUID Flag: SSE2
Category: Swizzle

Description

Unpack and interleave 8-bit integers from the low half of "a" and "b", and store the results in "dst".

Operation

DEFINE INTERLEAVE_BYTES(src1[127:0], src2[127:0]) {
    dst[7:0] := src1[7:0]
    dst[15:8] := src2[7:0]
    dst[23:16] := src1[15:8]
    dst[31:24] := src2[15:8]
    dst[39:32] := src1[23:16]
    dst[47:40] := src2[23:16]
    dst[55:48] := src1[31:24]
    dst[63:56] := src2[31:24]
    dst[71:64] := src1[39:32]
    dst[79:72] := src2[39:32]
    dst[87:80] := src1[47:40]
    dst[95:88] := src2[47:40]
    dst[103:96] := src1[55:48]
    dst[111:104] := src2[55:48]
    dst[119:112] := src1[63:56]
    dst[127:120] := src2[63:56]
    RETURN dst[127:0]
}
dst[127:0] := INTERLEAVE_BYTES(a[127:0], b[127:0])

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 2-6 | 1 | 1
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm_unpacklo_pd

__m128d _mm_unpacklo_pd( __m128d a, __m128d b )

Synopsis

#include "emmintrin.h"
Instruction: unpcklpd
CPUID Flag: SSE2
Category: Swizzle

Description

Unpack and interleave double-precision (64-bit) floating-point elements from the low half of "a" and "b", and store the results in "dst".

Operation

DEFINE INTERLEAVE_QWORDS(src1[127:0], src2[127:0]) {
    dst[63:0] := src1[63:0]
    dst[127:64] := src2[63:0]
    RETURN dst[127:0]
}
dst[127:0] := INTERLEAVE_QWORDS(a[127:0], b[127:0])

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 1 | 1 | 1
Ivy Bridge | 1 | 1 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 2 | 2 | 1
Ivy Bridge | 1 | 1 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm_unpacklo_pi16

__m64 _mm_unpacklo_pi16( __m64 a, __m64 b )

Synopsis

#include "mmintrin.h"
Instruction: punpcklwd
CPUID Flag: MMX
Category: Swizzle

Description

Unpack and interleave 16-bit integers from the low half of "a" and "b", and store the results in "dst".

Operation

DEFINE INTERLEAVE_WORDS(src1[63:0], src2[63:0]) {
    dst[15:0] := src1[15:0]
    dst[31:16] := src2[15:0]
    dst[47:32] := src1[31:16]
    dst[63:48] := src2[31:16]
    RETURN dst[63:0]
}
dst[63:0] := INTERLEAVE_WORDS(a[63:0], b[63:0])

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 2-6 | 1 | 1


_mm_unpacklo_pi32

__m64 _mm_unpacklo_pi32( __m64 a, __m64 b )

Synopsis

#include "mmintrin.h"
Instruction: punpckldq
CPUID Flag: MMX
Category: Swizzle

Description

Unpack and interleave 32-bit integers from the low half of "a" and "b", and store the results in "dst".

Operation

dst[31:0] := a[31:0]
dst[63:32] := b[31:0]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 2-6 | 1 | 1


_mm_unpacklo_pi8

__m64 _mm_unpacklo_pi8( __m64 a, __m64 b )

Synopsis

#include "mmintrin.h"
Instruction: punpcklbw
CPUID Flag: MMX
Category: Swizzle

Description

Unpack and interleave 8-bit integers from the low half of "a" and "b", and store the results in "dst".

Operation

DEFINE INTERLEAVE_BYTES(src1[63:0], src2[63:0]) {
    dst[7:0] := src1[7:0]
    dst[15:8] := src2[7:0]
    dst[23:16] := src1[15:8]
    dst[31:24] := src2[15:8]
    dst[39:32] := src1[23:16]
    dst[47:40] := src2[23:16]
    dst[55:48] := src1[31:24]
    dst[63:56] := src2[31:24]
    RETURN dst[63:0]
}
dst[63:0] := INTERLEAVE_BYTES(a[63:0], b[63:0])

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 1 | 0.5 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 2-6 | 1 | 1


_mm_unpacklo_ps

__m128 _mm_unpacklo_ps( __m128 a, __m128 b )

Synopsis

#include "xmmintrin.h"
Instruction: unpcklps
CPUID Flag: SSE
Category: Swizzle

Description

Unpack and interleave single-precision (32-bit) floating-point elements from the low half of "a" and "b", and store the results in "dst".

Operation

DEFINE INTERLEAVE_DWORDS(src1[127:0], src2[127:0]) {
    dst[31:0] := src1[31:0]
    dst[63:32] := src2[31:0]
    dst[95:64] := src1[63:32]
    dst[127:96] := src2[63:32]
    RETURN dst[127:0]
}
dst[127:0] := INTERLEAVE_DWORDS(a[127:0], b[127:0])

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Jaguar | 2 | 0.5 | 1
Sandy Bridge | 1 | 1 | 1
Ivy Bridge | 1 | 1 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 2 | 2 | 1
Ivy Bridge | 1 | 1 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm_urem_epi32

__m128i _mm_urem_epi32( __m128i a, __m128i b )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: SSE
Category: Arithmetic

Description

Divide packed unsigned 32-bit integers in "a" by packed elements in "b", and store the remainders as packed unsigned 32-bit integers in "dst".

Operation

FOR j := 0 to 3
    i := 32*j
    dst[i+31:i] := REMAINDER(a[i+31:i] / b[i+31:i])
ENDFOR
dst[MAX:128] := 0


_mm_xor_pd

__m128d _mm_xor_pd( __m128d a, __m128d b )

Synopsis

#include "emmintrin.h"
Instruction: xorpd
CPUID Flag: SSE2
Category: Logical

Description

Compute the bitwise XOR of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst".

Operation

FOR j := 0 to 1
    i := j*64
    dst[i+63:i] := a[i+63:i] XOR b[i+63:i]
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.25 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 1 | 1
Ivy Bridge | 1 | 1 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 0.33 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 1 | 1 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 0.33 |


_mm_xor_ps

__m128 _mm_xor_ps( __m128 a, __m128 b )

Synopsis

#include "xmmintrin.h"
Instruction: xorps
CPUID Flag: SSE
Category: Logical

Description

Compute the bitwise XOR of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    dst[i+31:i] := a[i+31:i] XOR b[i+31:i]
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.25 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 | 1 | 1
Ivy Bridge | 1 | 1 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 0.33 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 1 | 1 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm_xor_si128

__m128i _mm_xor_si128( __m128i a, __m128i b )

Synopsis

#include "emmintrin.h"
Instruction: pxor
CPUID Flag: SSE2
Category: Logical

Description

Compute the bitwise XOR of 128 bits (representing integer data) in "a" and "b", and store the result in "dst".

Operation

dst[127:0] := (a[127:0] XOR b[127:0])

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.25 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 |  | 1
Ivy Bridge | 1 | 0.33 | 1
Haswell | 1 | 0.33 | 1
Broadwell | 1 | 0.33 | 1
Skylake | 1 | 0.33 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 1 | 0.33 |
Haswell | 1 | 0.33 |
Broadwell | 1 | 0.33 |
Skylake | 1 | 0.33 |


_mm_xor_si64

__m64 _mm_xor_si64( __m64 a, __m64 b )

Synopsis

#include "mmintrin.h"
Instruction: pxor
CPUID Flag: MMX
Category: Logical

Description

Compute the bitwise XOR of 64 bits (representing integer data) in "a" and "b", and store the result in "dst".

Operation

dst[63:0] := (a[63:0] XOR b[63:0])

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.25 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 1 |  | 1
Ivy Bridge | 1 | 0.33 | 1
Haswell | 1 | 0.33 | 1
Broadwell | 1 | 0.33 | 1
Skylake | 1 | 0.33 | 1
Knights Landing | 2 | 0.5 | 1


_mm256_abs_epi16

__m256i _mm256_abs_epi16( __m256i a )

Synopsis

#include "immintrin.h"
Instruction: vpabsw
CPUID Flag: AVX2
Category: Special Math Functions

Description

Compute the absolute value of packed 16-bit integers in "a", and store the unsigned results in "dst".

Operation

FOR j := 0 to 15
    i := j*16
    dst[i+15:i] := ABS(a[i+15:i])
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 1 | 2
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1


_mm256_abs_epi32

__m256i _mm256_abs_epi32( __m256i a )

Synopsis

#include "immintrin.h"
Instruction: vpabsd
CPUID Flag: AVX2
Category: Special Math Functions

Description

Compute the absolute value of packed 32-bit integers in "a", and store the unsigned results in "dst".

Operation

FOR j := 0 to 7
    i := j*32
    dst[i+31:i] := ABS(a[i+31:i])
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 1 | 2
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1


_mm256_abs_epi8

__m256i _mm256_abs_epi8( __m256i a )

Synopsis

#include "immintrin.h"
Instruction: vpabsb
CPUID Flag: AVX2
Category: Special Math Functions

Description

Compute the absolute value of packed 8-bit integers in "a", and store the unsigned results in "dst".

Operation

FOR j := 0 to 31
    i := j*8
    dst[i+7:i] := ABS(a[i+7:i])
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 1 | 2
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1


_mm256_acos_pd

__m256d _mm256_acos_pd( __m256d a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Trigonometry

Description

Compute the inverse cosine of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*64
    dst[i+63:i] := ACOS(a[i+63:i])
ENDFOR
dst[MAX:256] := 0


_mm256_acos_ps

__m256 _mm256_acos_ps( __m256 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Trigonometry

Description

Compute the inverse cosine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*32
    dst[i+31:i] := ACOS(a[i+31:i])
ENDFOR
dst[MAX:256] := 0


_mm256_acosh_pd

__m256d _mm256_acosh_pd( __m256d a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Trigonometry

Description

Compute the inverse hyperbolic cosine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*64
    dst[i+63:i] := ACOSH(a[i+63:i])
ENDFOR
dst[MAX:256] := 0


_mm256_acosh_ps

__m256 _mm256_acosh_ps( __m256 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Trigonometry

Description

Compute the inverse hyperbolic cosine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*32
    dst[i+31:i] := ACOSH(a[i+31:i])
ENDFOR
dst[MAX:256] := 0


_mm256_add_epi16

__m256i _mm256_add_epi16( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: vpaddw
CPUID Flag: AVX2
Category: Arithmetic

Description

Add packed 16-bit integers in "a" and "b", and store the results in "dst".

Operation

FOR j := 0 to 15
    i := j*16
    dst[i+15:i] := a[i+15:i] + b[i+15:i]
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.33 | 1
Knights Landing | 2 | 0.5 | 1
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.33 |


_mm256_add_epi32

__m256i _mm256_add_epi32( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: vpaddd
CPUID Flag: AVX2
Category: Arithmetic

Description

Add packed 32-bit integers in "a" and "b", and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*32
    dst[i+31:i] := a[i+31:i] + b[i+31:i]
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.33 | 1
Knights Landing | 2 | 0.5 | 1
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.33 |


_mm256_add_epi64

__m256i _mm256_add_epi64( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: vpaddq
CPUID Flag: AVX2
Category: Arithmetic

Description

Add packed 64-bit integers in "a" and "b", and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*64
    dst[i+63:i] := a[i+63:i] + b[i+63:i]
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.33 | 1
Knights Landing | 2 | 0.5 | 1
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.33 |


_mm256_add_epi8

__m256i _mm256_add_epi8( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: vpaddb
CPUID Flag: AVX2
Category: Arithmetic

Description

Add packed 8-bit integers in "a" and "b", and store the results in "dst".

Operation

FOR j := 0 to 31
    i := j*8
    dst[i+7:i] := a[i+7:i] + b[i+7:i]
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.33 | 1
Knights Landing | 2 | 0.5 | 1
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.33 |


_mm256_add_pd

__m256d _mm256_add_pd( __m256d a, __m256d b )

Synopsis

#include "immintrin.h"
Instruction: vaddpd
CPUID Flag: AVX
Category: Arithmetic

Description

Add packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*64
    dst[i+63:i] := a[i+63:i] + b[i+63:i]
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 1 | 2
Jaguar | 3 | 2 | 2
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 4 | 0.5 | 1
Knights Landing | 6 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 4 | 0.5 |


_mm256_add_ps

__m256 _mm256_add_ps( __m256 a, __m256 b )

Synopsis

#include "immintrin.h"
Instruction: vaddps
CPUID Flag: AVX
Category: Arithmetic

Description

Add packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*32
    dst[i+31:i] := a[i+31:i] + b[i+31:i]
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 1 | 2
Jaguar | 3 | 2 | 2
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 4 | 0.5 | 1
Knights Landing | 6 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 4 | 0.5 |


_mm256_adds_epi16

__m256i _mm256_adds_epi16( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: vpaddsw
CPUID Flag: AVX2
Category: Arithmetic

Description

Add packed 16-bit integers in "a" and "b" using saturation, and store the results in "dst".

Operation

FOR j := 0 to 15
    i := j*16
    dst[i+15:i] := Saturate_To_Int16( a[i+15:i] + b[i+15:i] )
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.33 | 1
Knights Landing | 2 | 0.5 | 1


_mm256_adds_epi8

__m256i _mm256_adds_epi8( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: vpaddsb
CPUID Flag: AVX2
Category: Arithmetic

Description

Add packed 8-bit integers in "a" and "b" using saturation, and store the results in "dst".

Operation

FOR j := 0 to 31
    i := j*8
    dst[i+7:i] := Saturate_To_Int8( a[i+7:i] + b[i+7:i] )
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.33 | 1
Knights Landing | 2 | 0.5 | 1
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.5 |


_mm256_adds_epu16

__m256i _mm256_adds_epu16( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: vpaddusw
CPUID Flag: AVX2
Category: Arithmetic

Description

Add packed unsigned 16-bit integers in "a" and "b" using saturation, and store the results in "dst".

Operation

FOR j := 0 to 15
    i := j*16
    dst[i+15:i] := Saturate_To_UnsignedInt16( a[i+15:i] + b[i+15:i] )
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.33 | 1


_mm256_adds_epu8

__m256i _mm256_adds_epu8( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: vpaddusb
CPUID Flag: AVX2
Category: Arithmetic

Description

Add packed unsigned 8-bit integers in "a" and "b" using saturation, and store the results in "dst".

Operation

FOR j := 0 to 31
    i := j*8
    dst[i+7:i] := Saturate_To_UnsignedInt8( a[i+7:i] + b[i+7:i] )
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.33 | 1
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.5 |


_mm256_addsub_pd

__m256d _mm256_addsub_pd( __m256d a, __m256d b )

Synopsis

#include "immintrin.h"
Instruction: vaddsubpd
CPUID Flag: AVX
Category: Arithmetic

Description

Alternatively add and subtract packed double-precision (64-bit) floating-point elements in "a" to/from packed elements in "b", and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*64
    IF (j % 1 == 0)
        dst[i+63:i] := a[i+63:i] - b[i+63:i]
    ELSE
        dst[i+63:i] := a[i+63:i] + b[i+63:i]
    FI
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 1 | 2
Jaguar | 3 | 2 | 2
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 4 | 0.5 | 1
Knights Landing | 6 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 4 | 0.5 |


_mm256_addsub_ps

__m256 _mm256_addsub_ps( __m256 a, __m256 b )

Synopsis

#include "immintrin.h"
Instruction: vaddsubps
CPUID Flag: AVX
Category: Arithmetic

Description

Alternatively add and subtract packed single-precision (32-bit) floating-point elements in "a" to/from packed elements in "b", and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*32
    IF (j % 1 == 0)
        dst[i+31:i] := a[i+31:i] - b[i+31:i]
    ELSE
        dst[i+31:i] := a[i+31:i] + b[i+31:i]
    FI
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 1 | 2
Jaguar | 3 | 2 | 2
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 4 | 0.5 | 1
Knights Landing | 6 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 4 | 0.5 |


_mm256_alignr_epi8

__m256i _mm256_alignr_epi8( __m256i a, __m256i b, const int count )

Synopsis

#include "immintrin.h"
Instruction: vpalignr
CPUID Flag: AVX2
Category: Miscellaneous

Description

Concatenate pairs of 16-byte blocks in "a" and "b" into a 32-byte temporary result, shift the result right by "count" bytes, and store the low 16 bytes in "dst".

Operation

FOR j := 0 to 1
    i := j*128
    tmp[255:0] := ((a[i+127:i] << 128) OR b[i+127:i]) >> (count[7:0]*8)
    dst[i+127:i] := tmp[127:0]
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 1 | 2
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 11-14 | 9 | 5
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm256_and_pd

__m256d _mm256_and_pd( __m256d a, __m256d b )

Synopsis

#include "immintrin.h"
Instruction: vandpd
CPUID Flag: AVX
Category: Logical

Description

Compute the bitwise AND of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*64
    dst[i+63:i] := (a[i+63:i] AND b[i+63:i])
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 2
Jaguar | 1 | 1 | 2
Sandy Bridge | 1 | 1 | 1
Ivy Bridge | 1 | 1 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 0.33 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 1 | 1 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 0.33 |


_mm256_and_ps

__m256 _mm256_and_ps( __m256 a, __m256 b )

Synopsis

#include "immintrin.h"
Instruction: vandps
CPUID Flag: AVX
Category: Logical

Description

Compute the bitwise AND of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*32
    dst[i+31:i] := (a[i+31:i] AND b[i+31:i])
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 2
Jaguar | 1 | 1 | 2
Sandy Bridge | 1 | 1 | 1
Ivy Bridge | 1 | 1 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 0.33 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 1 | 1 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 0.33 |


_mm256_and_si256

__m256i _mm256_and_si256( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: vpand
CPUID Flag: AVX2
Category: Logical

Description

Compute the bitwise AND of 256 bits (representing integer data) in "a" and "b", and store the result in "dst".

Operation

dst[255:0] := (a[255:0] AND b[255:0])
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 2
Haswell | 1 | 0.33 | 1
Broadwell | 1 | 0.33 | 1
Skylake | 1 | 0.33 | 1
Knights Landing | 2 | 0.5 | 1


_mm256_andnot_pd

__m256d _mm256_andnot_pd( __m256d a, __m256d b )

Synopsis

#include "immintrin.h"
Instruction: vandnpd
CPUID Flag: AVX
Category: Logical

Description

Compute the bitwise NOT of packed double-precision (64-bit) floating-point elements in "a" and then AND with "b", and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*64
    dst[i+63:i] := ((NOT a[i+63:i]) AND b[i+63:i])
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 2
Sandy Bridge | 1 | 1 | 1
Ivy Bridge | 1 | 1 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 0.33 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 1 | 1 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 0.33 |


_mm256_andnot_ps

__m256 _mm256_andnot_ps( __m256 a, __m256 b )

Synopsis

#include "immintrin.h"
Instruction: vandnps
CPUID Flag: AVX
Category: Logical

Description

Compute the bitwise NOT of packed single-precision (32-bit) floating-point elements in "a" and then AND with "b", and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*32
    dst[i+31:i] := ((NOT a[i+31:i]) AND b[i+31:i])
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 2
Sandy Bridge | 1 | 1 | 1
Ivy Bridge | 1 | 1 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 0.33 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 1 | 1 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 0.33 |


_mm256_andnot_si256

__m256i _mm256_andnot_si256( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: vpandn
CPUID Flag: AVX2
Category: Logical

Description

Compute the bitwise NOT of 256 bits (representing integer data) in "a" and then AND with "b", and store the result in "dst".

Operation

dst[255:0] := ((NOT a[255:0]) AND b[255:0])
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 2
Haswell | 1 | 0.33 | 1
Broadwell | 1 | 0.33 | 1
Skylake | 1 | 0.33 | 1
Knights Landing | 2 | 0.5 | 1


_mm256_asin_pd

__m256d _mm256_asin_pd( __m256d a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Trigonometry

Description

Compute the inverse sine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*64
    dst[i+63:i] := ASIN(a[i+63:i])
ENDFOR
dst[MAX:256] := 0


_mm256_asin_ps

__m256 _mm256_asin_ps( __m256 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Trigonometry

Description

Compute the inverse sine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*32
    dst[i+31:i] := ASIN(a[i+31:i])
ENDFOR
dst[MAX:256] := 0


_mm256_asinh_pd

__m256d _mm256_asinh_pd( __m256d a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Trigonometry

Description

Compute the inverse hyperbolic sine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*64
    dst[i+63:i] := ASINH(a[i+63:i])
ENDFOR
dst[MAX:256] := 0


_mm256_asinh_ps

__m256 _mm256_asinh_ps( __m256 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Trigonometry

Description

Compute the inverse hyperbolic sine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*32
    dst[i+31:i] := ASINH(a[i+31:i])
ENDFOR
dst[MAX:256] := 0


_mm256_atan_pd

__m256d _mm256_atan_pd( __m256d a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Trigonometry

Description

Compute the inverse tangent of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*64
    dst[i+63:i] := ATAN(a[i+63:i])
ENDFOR
dst[MAX:256] := 0


_mm256_atan_ps

__m256 _mm256_atan_ps( __m256 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Trigonometry

Description

Compute the inverse tangent of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*32
    dst[i+31:i] := ATAN(a[i+31:i])
ENDFOR
dst[MAX:256] := 0


_mm256_atan2_pd

__m256d _mm256_atan2_pd( __m256d a, __m256d b )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Trigonometry

Description

Compute the inverse tangent of packed double-precision (64-bit) floating-point elements in "a" divided by packed elements in "b", and store the results in "dst" expressed in radians.

Operation

FOR j := 0 to 3
    i := j*64
    dst[i+63:i] := ATAN(a[i+63:i] / b[i+63:i])
ENDFOR
dst[MAX:256] := 0


_mm256_atan2_ps

__m256 _mm256_atan2_ps( __m256 a, __m256 b )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Trigonometry

Description

Compute the inverse tangent of packed single-precision (32-bit) floating-point elements in "a" divided by packed elements in "b", and store the results in "dst" expressed in radians.

Operation

FOR j := 0 to 7
    i := j*32
    dst[i+31:i] := ATAN(a[i+31:i] / b[i+31:i])
ENDFOR
dst[MAX:256] := 0


_mm256_atanh_pd

__m256d _mm256_atanh_pd( __m256d a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Trigonometry

Description

Compute the inverse hyperbolic tangent of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*64
    dst[i+63:i] := ATANH(a[i+63:i])
ENDFOR
dst[MAX:256] := 0


_mm256_atanh_ps

__m256 _mm256_atanh_ps( __m256 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Trigonometry

Description

Compute the inverse hyperbolic tangent of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*32
    dst[i+31:i] := ATANH(a[i+31:i])
ENDFOR
dst[MAX:256] := 0


_mm256_avg_epu16

__m256i _mm256_avg_epu16( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: vpavgw
CPUID Flag: AVX2
Category: Probability/Statistics

Description

Average packed unsigned 16-bit integers in "a" and "b", and store the results in "dst".

Operation

FOR j := 0 to 15
    i := j*16
    dst[i+15:i] := (a[i+15:i] + b[i+15:i] + 1) >> 1
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 1 | 2
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1


_mm256_avg_epu8

__m256i _mm256_avg_epu8( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: vpavgb
CPUID Flag: AVX2
Category: Probability/Statistics

Description

Average packed unsigned 8-bit integers in "a" and "b", and store the results in "dst".

Operation

FOR j := 0 to 31
    i := j*8
    dst[i+7:i] := (a[i+7:i] + b[i+7:i] + 1) >> 1
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 1 | 2
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.5 |


_mm256_blend_epi16

__m256i _mm256_blend_epi16( __m256i a, __m256i b, const int imm8 )

Synopsis

#include "immintrin.h"
Instruction: vpblendw
CPUID Flag: AVX2
Category: Swizzle

Description

Blend packed 16-bit integers from "a" and "b" within 128-bit lanes using control mask "imm8", and store the results in "dst".

Operation

FOR j := 0 to 15
    i := j*16
    IF imm8[j%8]
        dst[i+15:i] := b[i+15:i]
    ELSE
        dst[i+15:i] := a[i+15:i]
    FI
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 2 | 0.5 | 1
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm256_blend_epi32

__m256i _mm256_blend_epi32( __m256i a, __m256i b, const int imm8 )

Synopsis

#include "immintrin.h"
Instruction: vpblendd
CPUID Flag: AVX2
Category: Swizzle

Description

Blend packed 32-bit integers from "a" and "b" using control mask "imm8", and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*32
    IF imm8[j]
        dst[i+31:i] := b[i+31:i]
    ELSE
        dst[i+31:i] := a[i+31:i]
    FI
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Haswell | 1 | 0.33 | 1
Broadwell | 1 | 0.33 | 1
Skylake | 1 | 0.33 | 1
Knights Landing | 2 | 0.5 | 1
Haswell | 1 | 0.33 |
Broadwell | 1 | 0.33 |
Skylake | 1 | 0.33 |


_mm256_blend_pd

__m256d _mm256_blend_pd( __m256d a, __m256d b, const int imm8 )

Synopsis

#include "immintrin.h"
Instruction: vblendpd
CPUID Flag: AVX
Category: Swizzle

Description

Blend packed double-precision (64-bit) floating-point elements from "a" and "b" using control mask "imm8", and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*64
    IF imm8[j]
        dst[i+63:i] := b[i+63:i]
    ELSE
        dst[i+63:i] := a[i+63:i]
    FI
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 1 | 2
Sandy Bridge | 1 | 1 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.33 | 1
Broadwell | 1 | 0.33 | 1
Skylake | 1 | 0.33 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 0.33 |
Broadwell | 1 | 0.33 |
Skylake | 1 | 0.33 |


_mm256_blend_ps

__m256 _mm256_blend_ps( __m256 a, __m256 b, const int imm8 )

Synopsis

#include "immintrin.h"
Instruction: vblendps
CPUID Flag: AVX
Category: Swizzle

Description

Blend packed single-precision (32-bit) floating-point elements from "a" and "b" using control mask "imm8", and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*32
    IF imm8[j]
        dst[i+31:i] := b[i+31:i]
    ELSE
        dst[i+31:i] := a[i+31:i]
    FI
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 1 | 2
Sandy Bridge | 1 | 1 | 1
Ivy Bridge | 1 | 0.5 | 1
Haswell | 1 | 0.33 | 1
Broadwell | 1 | 0.33 | 1
Skylake | 1 | 0.33 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 0.33 |
Broadwell | 1 | 0.33 |
Skylake | 1 | 0.33 |


_mm256_blendv_epi8

__m256i _mm256_blendv_epi8( __m256i a, __m256i b, __m256i mask )

Synopsis

#include "immintrin.h"
Instruction: vpblendvb
CPUID Flag: AVX2
Category: Swizzle

Description

Blend packed 8-bit integers from "a" and "b" using "mask", and store the results in "dst".

Operation

FOR j := 0 to 31
    i := j*8
    IF mask[i+7]
        dst[i+7:i] := b[i+7:i]
    ELSE
        dst[i+7:i] := a[i+7:i]
    FI
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Haswell | 2 | 2 | 2
Broadwell | 2 | 2 | 2
Skylake | 2 | 1 | 2
Knights Landing | 8-10 | 8 | 4
Haswell | 2 | 2 |
Broadwell | 2 | 2 |
Skylake | 1 | 1 |


_mm256_blendv_pd

__m256d _mm256_blendv_pd( __m256d a, __m256d b, __m256d mask )

Synopsis

#include "immintrin.h"
Instruction: vblendvpd
CPUID Flag: AVX
Category: Swizzle

Description

Blend packed double-precision (64-bit) floating-point elements from "a" and "b" using "mask", and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*64
    IF mask[i+63]
        dst[i+63:i] := b[i+63:i]
    ELSE
        dst[i+63:i] := a[i+63:i]
    FI
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 1 | 2
Sandy Bridge | 2 | 1 | 2
Ivy Bridge | 2 | 1 | 2
Haswell | 2 | 2 | 2
Broadwell | 2 | 2 | 2
Skylake | 2 | 1 | 2
Knights Landing | 7 | 7 | 2
Ivy Bridge | 1 | 1 |
Haswell | 2 | 2 |
Broadwell | 2 | 2 |
Skylake | 1 | 1 |


_mm256_blendv_ps

__m256 _mm256_blendv_ps( __m256 a, __m256 b, __m256 mask )

Synopsis

#include "immintrin.h"
Instruction: vblendvps
CPUID Flag: AVX
Category: Swizzle

Description

Blend packed single-precision (32-bit) floating-point elements from "a" and "b" using "mask", and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*32
    IF mask[i+31]
        dst[i+31:i] := b[i+31:i]
    ELSE
        dst[i+31:i] := a[i+31:i]
    FI
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 1 | 2
Sandy Bridge | 2 | 1 | 2
Ivy Bridge | 2 | 1 | 2
Haswell | 2 | 2 | 2
Broadwell | 2 | 2 | 2
Skylake | 2 | 1 | 2
Knights Landing | 7 | 7 | 2
Ivy Bridge | 1 | 1 |
Haswell | 2 | 2 |
Broadwell | 2 | 2 |
Skylake | 1 | 1 |


_mm256_broadcast_pd

__m256d _mm256_broadcast_pd( __m128d const * mem_addr )

Synopsis

#include "immintrin.h"
Instruction: vbroadcastf128
CPUID Flag: AVX
Category: Load

Description

Broadcast 128 bits from memory (composed of 2 packed double-precision (64-bit) floating-point elements) to all elements of "dst".

Operation

tmp[127:0] := MEM[mem_addr+127:mem_addr]
dst[127:0] := tmp[127:0]
dst[255:128] := tmp[127:0]
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 4 | 5 | 2
Sandy Bridge |  | 1 | 2
Ivy Bridge | 5 | 1 | 2
Haswell | 3 | 0.5 | 1
Broadwell | 4 | 0.5 | 1
Skylake | 3 | 0.5 | 1
Knights Landing | 5 | 0.5 | 1


_mm256_broadcast_ps

__m256 _mm256_broadcast_ps( __m128 const * mem_addr )

Synopsis

#include "immintrin.h"
Instruction: vbroadcastf128
CPUID Flag: AVX
Category: Load

Description

Broadcast 128 bits from memory (composed of 4 packed single-precision (32-bit) floating-point elements) to all elements of "dst".

Operation

tmp[127:0] := MEM[mem_addr+127:mem_addr]
dst[127:0] := tmp[127:0]
dst[255:128] := tmp[127:0]
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 4 | 5 | 2
Sandy Bridge |  | 1 | 2
Ivy Bridge | 5 | 1 | 2
Haswell | 3 | 0.5 | 1
Broadwell | 4 | 0.5 | 1
Skylake | 3 | 0.5 | 1
Knights Landing | 5 | 0.5 | 1


_mm256_broadcast_sd

__m256d _mm256_broadcast_sd( double const * mem_addr )

Synopsis

#include "immintrin.h"
Instruction: vbroadcastsd
CPUID Flag: AVX
Category: Load

Description

Broadcast a double-precision (64-bit) floating-point element from memory to all elements of "dst".

Operation

tmp[63:0] := MEM[mem_addr+63:mem_addr]
FOR j := 0 to 3
    i := j*64
    dst[i+63:i] := tmp[63:0]
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Sandy Bridge |  | 1 | 2
Ivy Bridge | 5 | 1 | 2
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 3 | 1 | 1
Knights Landing | 3-6 | 1 | 1


_mm256_broadcast_ss

__m256 _mm256_broadcast_ss( float const * mem_addr )

Synopsis

#include "immintrin.h"
Instruction: vbroadcastss
CPUID Flag: AVX
Category: Load

Description

Broadcast a single-precision (32-bit) floating-point element from memory to all elements of "dst".

Operation

tmp[31:0] := MEM[mem_addr+31:mem_addr]
FOR j := 0 to 7
    i := j*32
    dst[i+31:i] := tmp[31:0]
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 1 | 2
Sandy Bridge |  | 1 | 1
Ivy Bridge | 5 | 1 | 2
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 3 | 1 | 1
Knights Landing | 3-6 | 1 | 1


_mm256_broadcastb_epi8

__m256i _mm256_broadcastb_epi8( __m128i a )

Synopsis

#include "immintrin.h"
Instruction: vpbroadcastb
CPUID Flag: AVX2
Category: Swizzle

Description

Broadcast the low packed 8-bit integer from "a" to all elements of "dst".

Operation

FOR j := 0 to 31
    i := j*8
    dst[i+7:i] := a[7:0]
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Haswell | 7 | 1 | 3
Broadwell | 7 | 1 | 3
Skylake | 7 | 1 | 2
Knights Landing | 8 | 7 | 2
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 3 | 1 |


_mm256_broadcastd_epi32

__m256i _mm256_broadcastd_epi32( __m128i a )

Synopsis

#include "immintrin.h"
Instruction: vpbroadcastd
CPUID Flag: AVX2
Category: Swizzle

Description

Broadcast the low packed 32-bit integer from "a" to all elements of "dst".

Operation

FOR j := 0 to 7
    i := j*32
    dst[i+31:i] := a[31:0]
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Haswell | 5 | 0.5 | 1
Broadwell | 5 | 0.5 | 1
Skylake | 4 | 0.5 | 1
Knights Landing | 3 | 1 | 1
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 3 | 1 |


_mm256_broadcastq_epi64

__m256i _mm256_broadcastq_epi64( __m128i a )

Synopsis

#include "immintrin.h"
Instruction: vpbroadcastq
CPUID Flag: AVX2
Category: Swizzle

Description

Broadcast the low packed 64-bit integer from "a" to all elements of "dst".

Operation

FOR j := 0 to 3
    i := j*64
    dst[i+63:i] := a[63:0]
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Haswell | 5 | 0.5 | 1
Broadwell | 5 | 0.5 | 1
Skylake | 4 | 0.5 | 1
Knights Landing | 3 | 1 | 1


_mm256_broadcastsd_pd

__m256d _mm256_broadcastsd_pd( __m128d a )

Synopsis

#include "immintrin.h"
Instruction: vbroadcastsd
CPUID Flag: AVX2
Category: Swizzle

Description

Broadcast the low double-precision (64-bit) floating-point element from "a" to all elements of "dst".

Operation

FOR j := 0 to 3
    i := j*64
    dst[i+63:i] := a[63:0]
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Sandy Bridge |  | 1 | 2
Ivy Bridge | 5 | 1 | 2
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 3 | 1 | 1
Knights Landing | 3-6 | 1 | 1


_mm256_broadcastsi128_si256

__m256i _mm256_broadcastsi128_si256( __m128i a )

Synopsis

#include "immintrin.h"
Instruction: vbroadcasti128
CPUID Flag: AVX2
Category: Swizzle

Description

Broadcast 128 bits of integer data from "a" to all 128-bit lanes in "dst".

Operation

dst[127:0] := a[127:0]
dst[255:128] := a[127:0]
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 0.5 | 2
Haswell | 3 | 0.5 | 1
Broadwell | 3 | 0.5 | 1
Skylake | 3 | 0.5 | 1
Knights Landing | 5 | 0.5 | 1


_mm256_broadcastss_ps

__m256 _mm256_broadcastss_ps( __m128 a )

Synopsis

#include "immintrin.h"
Instruction: vbroadcastss
CPUID Flag: AVX2
Category: Swizzle

Description

Broadcast the low single-precision (32-bit) floating-point element from "a" to all elements of "dst".

Operation

FOR j := 0 to 7
    i := j*32
    dst[i+31:i] := a[31:0]
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 1 | 2
Sandy Bridge |  | 1 | 1
Ivy Bridge | 5 | 1 | 2
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 3 | 1 | 1
Knights Landing | 3-6 | 1 | 1


_mm256_broadcastw_epi16

__m256i _mm256_broadcastw_epi16( __m128i a )

Synopsis

#include "immintrin.h"
Instruction: vpbroadcastw
CPUID Flag: AVX2
Category: Swizzle

Description

Broadcast the low packed 16-bit integer from "a" to all elements of "dst".

Operation

FOR j := 0 to 15
    i := j*16
    dst[i+15:i] := a[15:0]
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 1
Haswell | 7 | 1 | 3
Broadwell | 7 | 1 | 3
Skylake | 7 | 1 | 2
Knights Landing | 8 | 7 | 2


_mm256_bslli_epi128

__m256i _mm256_bslli_epi128( __m256i a, const int imm8 )

Synopsis

#include "immintrin.h"
Instruction: vpslldq
CPUID Flag: AVX2
Category: Shift

Description

Shift 128-bit lanes in "a" left by "imm8" bytes while shifting in zeros, and store the results in "dst".

Operation

tmp := imm8[7:0]
IF tmp > 15
    tmp := 16
FI
dst[127:0] := a[127:0] << (tmp*8)
dst[255:128] := a[255:128] << (tmp*8)
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 1 | 2
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm256_bsrli_epi128

__m256i _mm256_bsrli_epi128( __m256i a, const int imm8 )

Synopsis

#include "immintrin.h"
Instruction: vpsrldq
CPUID Flag: AVX2
Category: Shift

Description

Shift 128-bit lanes in "a" right by "imm8" bytes while shifting in zeros, and store the results in "dst".

Operation

tmp := imm8[7:0]
IF tmp > 15
    tmp := 16
FI
dst[127:0] := a[127:0] >> (tmp*8)
dst[255:128] := a[255:128] >> (tmp*8)
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 1 | 2
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1


_mm256_castpd_ps

__m256 _mm256_castpd_ps( __m256d a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Cast

Description

Cast vector of type __m256d to type __m256. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.


_mm256_castpd_si256

__m256i _mm256_castpd_si256( __m256d a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Cast

Description

Casts vector of type __m256d to type __m256i. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.


_mm256_castpd128_pd256

__m256d _mm256_castpd128_pd256( __m128d a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Cast

Description

Casts vector of type __m128d to type __m256d; the upper 128 bits of the result are undefined. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.


_mm256_castpd256_pd128

__m128d _mm256_castpd256_pd128( __m256d a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Cast

Description

Casts vector of type __m256d to type __m128d. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.


_mm256_castps_pd

__m256d _mm256_castps_pd( __m256 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Cast

Description

Cast vector of type __m256 to type __m256d. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.


_mm256_castps_si256

__m256i _mm256_castps_si256( __m256 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Cast

Description

Casts vector of type __m256 to type __m256i. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.


_mm256_castps128_ps256

__m256 _mm256_castps128_ps256( __m128 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Cast

Description

Casts vector of type __m128 to type __m256; the upper 128 bits of the result are undefined. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.


_mm256_castps256_ps128

__m128 _mm256_castps256_ps128( __m256 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Cast

Description

Casts vector of type __m256 to type __m128. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.


_mm256_castsi128_si256

__m256i _mm256_castsi128_si256( __m128i a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Cast

Description

Casts vector of type __m128i to type __m256i; the upper 128 bits of the result are undefined. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.


_mm256_castsi256_pd

__m256d _mm256_castsi256_pd( __m256i a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Cast

Description

Casts vector of type __m256i to type __m256d. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.


_mm256_castsi256_ps

__m256 _mm256_castsi256_ps( __m256i a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Cast

Description

Casts vector of type __m256i to type __m256. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.


_mm256_castsi256_si128

__m128i _mm256_castsi256_si128( __m256i a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Cast

Description

Casts vector of type __m256i to type __m128i. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.


_mm256_cbrt_pd

__m256d _mm256_cbrt_pd( __m256d a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Elementary Math Functions

Description

Compute the cube root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*64
    dst[i+63:i] := CubeRoot(a[i+63:i])
ENDFOR
dst[MAX:256] := 0


_mm256_cbrt_ps

__m256 _mm256_cbrt_ps( __m256 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Elementary Math Functions

Description

Compute the cube root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*32
    dst[i+31:i] := CubeRoot(a[i+31:i])
ENDFOR
dst[MAX:256] := 0


_mm256_cdfnorm_pd

__m256d _mm256_cdfnorm_pd( __m256d a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Probability/Statistics

Description

Compute the cumulative distribution function of packed double-precision (64-bit) floating-point elements in "a" using the normal distribution, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*64
    dst[i+63:i] := CDFNormal(a[i+63:i])
ENDFOR
dst[MAX:256] := 0


_mm256_cdfnorm_ps

__m256 _mm256_cdfnorm_ps( __m256 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Probability/Statistics

Description

Compute the cumulative distribution function of packed single-precision (32-bit) floating-point elements in "a" using the normal distribution, and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*32
    dst[i+31:i] := CDFNormal(a[i+31:i])
ENDFOR
dst[MAX:256] := 0


_mm256_cdfnorminv_pd

__m256d _mm256_cdfnorminv_pd( __m256d a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Probability/Statistics

Description

Compute the inverse cumulative distribution function of packed double-precision (64-bit) floating-point elements in "a" using the normal distribution, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*64
    dst[i+63:i] := InverseCDFNormal(a[i+63:i])
ENDFOR
dst[MAX:256] := 0


_mm256_cdfnorminv_ps

__m256 _mm256_cdfnorminv_ps( __m256 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Probability/Statistics

Description

Compute the inverse cumulative distribution function of packed single-precision (32-bit) floating-point elements in "a" using the normal distribution, and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*32
    dst[i+31:i] := InverseCDFNormal(a[i+31:i])
ENDFOR
dst[MAX:256] := 0


_mm256_ceil_pd

__m256d _mm256_ceil_pd( __m256d a )

Synopsis

#include "immintrin.h"
Instruction: vroundpd
CPUID Flag: AVX
Category: Special Math Functions

Description

Round the packed double-precision (64-bit) floating-point elements in "a" up to an integer value, and store the results as packed double-precision floating-point elements in "dst".

Operation

FOR j := 0 to 3
    i := j*64
    dst[i+63:i] := CEIL(a[i+63:i])
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 4 | 2 | 2
Jaguar | 4 | 2 | 2
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 6 | 2 | 2
Broadwell | 6 | 2 | 2
Skylake | 8 | 1 | 2
Knights Landing | 6 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 6 | 2 |
Broadwell | 6 | 2 |
Skylake | 8 | 1 |


_mm256_ceil_ps

__m256 _mm256_ceil_ps( __m256 a )

Synopsis

#include "immintrin.h"
Instruction: vroundps
CPUID Flag: AVX
Category: Special Math Functions

Description

Round the packed single-precision (32-bit) floating-point elements in "a" up to an integer value, and store the results as packed single-precision floating-point elements in "dst".

Operation

FOR j := 0 to 7
    i := j*32
    dst[i+31:i] := CEIL(a[i+31:i])
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 4 | 2 | 2
Jaguar | 4 | 2 | 2
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 6 | 2 | 2
Broadwell | 6 | 2 | 2
Skylake | 8 | 1 | 2
Knights Landing | 6 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 6 | 2 |
Broadwell | 6 | 2 |
Skylake | 8 | 1 |


_mm256_cexp_ps

__m256 _mm256_cexp_ps( __m256 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Elementary Math Functions

Description

Compute the exponential value of "e" raised to the power of packed complex single-precision (32-bit) floating-point elements in "a", and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*32
    dst[i+31:i] := e^(a[i+31:i])
ENDFOR
dst[MAX:256] := 0


_mm256_clog_ps

__m256 _mm256_clog_ps( __m256 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Elementary Math Functions

Description

Compute the natural logarithm of packed complex single-precision (32-bit) floating-point elements in "a", and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*32
    dst[i+31:i] := ln(a[i+31:i])
ENDFOR
dst[MAX:256] := 0


_mm256_cmp_pd

__m256d _mm256_cmp_pd( __m256d a, __m256d b, const int imm8 )

Synopsis

#include "immintrin.h"
Instruction: vcmppd
CPUID Flag: AVX
Category: Compare

Description

Compare packed double-precision (64-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in "dst".

Operation

CASE (imm8[7:0]) OF
0: OP := _CMP_EQ_OQ
1: OP := _CMP_LT_OS
2: OP := _CMP_LE_OS
3: OP := _CMP_UNORD_Q
4: OP := _CMP_NEQ_UQ
5: OP := _CMP_NLT_US
6: OP := _CMP_NLE_US
7: OP := _CMP_ORD_Q
8: OP := _CMP_EQ_UQ
9: OP := _CMP_NGE_US
10: OP := _CMP_NGT_US
11: OP := _CMP_FALSE_OQ
12: OP := _CMP_NEQ_OQ
13: OP := _CMP_GE_OS
14: OP := _CMP_GT_OS
15: OP := _CMP_TRUE_UQ
16: OP := _CMP_EQ_OS
17: OP := _CMP_LT_OQ
18: OP := _CMP_LE_OQ
19: OP := _CMP_UNORD_S
20: OP := _CMP_NEQ_US
21: OP := _CMP_NLT_UQ
22: OP := _CMP_NLE_UQ
23: OP := _CMP_ORD_S
24: OP := _CMP_EQ_US
25: OP := _CMP_NGE_UQ
26: OP := _CMP_NGT_UQ
27: OP := _CMP_FALSE_OS
28: OP := _CMP_NEQ_OS
29: OP := _CMP_GE_OQ
30: OP := _CMP_GT_OQ
31: OP := _CMP_TRUE_US
ESAC
FOR j := 0 to 3
    i := j*64
    dst[i+63:i] := ( a[i+63:i] OP b[i+63:i] ) ? 0xFFFFFFFFFFFFFFFF : 0
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 1 | 2
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 4 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 4 | 0.5 |


_mm256_cmp_ps

__m256 _mm256_cmp_ps( __m256 a, __m256 b, const int imm8 )

Synopsis

#include "immintrin.h"
Instruction: vcmpps
CPUID Flag: AVX
Category: Compare

Description

Compare packed single-precision (32-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in "dst".

Operation

CASE (imm8[7:0]) OF
0: OP := _CMP_EQ_OQ
1: OP := _CMP_LT_OS
2: OP := _CMP_LE_OS
3: OP := _CMP_UNORD_Q
4: OP := _CMP_NEQ_UQ
5: OP := _CMP_NLT_US
6: OP := _CMP_NLE_US
7: OP := _CMP_ORD_Q
8: OP := _CMP_EQ_UQ
9: OP := _CMP_NGE_US
10: OP := _CMP_NGT_US
11: OP := _CMP_FALSE_OQ
12: OP := _CMP_NEQ_OQ
13: OP := _CMP_GE_OS
14: OP := _CMP_GT_OS
15: OP := _CMP_TRUE_UQ
16: OP := _CMP_EQ_OS
17: OP := _CMP_LT_OQ
18: OP := _CMP_LE_OQ
19: OP := _CMP_UNORD_S
20: OP := _CMP_NEQ_US
21: OP := _CMP_NLT_UQ
22: OP := _CMP_NLE_UQ
23: OP := _CMP_ORD_S
24: OP := _CMP_EQ_US
25: OP := _CMP_NGE_UQ
26: OP := _CMP_NGT_UQ
27: OP := _CMP_FALSE_OS
28: OP := _CMP_NEQ_OS
29: OP := _CMP_GE_OQ
30: OP := _CMP_GT_OQ
31: OP := _CMP_TRUE_US
ESAC
FOR j := 0 to 7
    i := j*32
    dst[i+31:i] := ( a[i+31:i] OP b[i+31:i] ) ? 0xFFFFFFFF : 0
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 1 | 2
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 4 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 4 | 0.5 |


_mm256_cmpeq_epi16

__m256i _mm256_cmpeq_epi16( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: vpcmpeqw
CPUID Flag: AVX2
Category: Compare

Description

Compare packed 16-bit integers in "a" and "b" for equality, and store the results in "dst".

Operation

FOR j := 0 to 15
    i := j*16
    dst[i+15:i] := ( a[i+15:i] == b[i+15:i] ) ? 0xFFFF : 0
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 2 | 0.67 | 2
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.5 |


_mm256_cmpeq_epi32

__m256i _mm256_cmpeq_epi32( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: vpcmpeqd
CPUID Flag: AVX2
Category: Compare

Description

Compare packed 32-bit integers in "a" and "b" for equality, and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*32
    dst[i+31:i] := ( a[i+31:i] == b[i+31:i] ) ? 0xFFFFFFFF : 0
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 2 | 0.67 | 2
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.5 |


_mm256_cmpeq_epi64

__m256i _mm256_cmpeq_epi64( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: vpcmpeqq
CPUID Flag: AVX2
Category: Compare

Description

Compare packed 64-bit integers in "a" and "b" for equality, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*64
    dst[i+63:i] := ( a[i+63:i] == b[i+63:i] ) ? 0xFFFFFFFFFFFFFFFF : 0
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 2 | 1 | 2
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.5 |


_mm256_cmpeq_epi8

__m256i _mm256_cmpeq_epi8( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: vpcmpeqb
CPUID Flag: AVX2
Category: Compare

Description

Compare packed 8-bit integers in "a" and "b" for equality, and store the results in "dst".

Operation

FOR j := 0 to 31
    i := j*8
    dst[i+7:i] := ( a[i+7:i] == b[i+7:i] ) ? 0xFF : 0
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 2 | 0.67 | 2
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.5 |


_mm256_cmpgt_epi16

__m256i _mm256_cmpgt_epi16( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: vpcmpgtw
CPUID Flag: AVX2
Category: Compare

Description

Compare packed 16-bit integers in "a" and "b" for greater-than, and store the results in "dst".

Operation

FOR j := 0 to 15
    i := j*16
    dst[i+15:i] := ( a[i+15:i] > b[i+15:i] ) ? 0xFFFF : 0
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 2 | 0.67 | 2
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1


_mm256_cmpgt_epi32

__m256i _mm256_cmpgt_epi32( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: vpcmpgtd
CPUID Flag: AVX2
Category: Compare

Description

Compare packed 32-bit integers in "a" and "b" for greater-than, and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*32
    dst[i+31:i] := ( a[i+31:i] > b[i+31:i] ) ? 0xFFFFFFFF : 0
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 2 | 0.67 | 2
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1


_mm256_cmpgt_epi64

__m256i _mm256_cmpgt_epi64( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: vpcmpgtq
CPUID Flag: AVX2
Category: Compare

Description

Compare packed 64-bit integers in "a" and "b" for greater-than, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*64
    dst[i+63:i] := ( a[i+63:i] > b[i+63:i] ) ? 0xFFFFFFFFFFFFFFFF : 0
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen |  | 2 | 2
Haswell | 5 | 1 | 1
Broadwell | 5 | 1 | 1
Skylake | 3 | 1 | 1
Haswell | 5 | 1 |
Broadwell | 5 | 1 |
Skylake | 3 | 1 |


_mm256_cmpgt_epi8

__m256i _mm256_cmpgt_epi8( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: vpcmpgtb
CPUID Flag: AVX2
Category: Compare

Description

Compare packed 8-bit integers in "a" and "b" for greater-than, and store the results in "dst".

Operation

FOR j := 0 to 31
    i := j*8
    dst[i+7:i] := ( a[i+7:i] > b[i+7:i] ) ? 0xFF : 0
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 2 | 0.67 | 2
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1


_mm256_cos_pd

__m256d _mm256_cos_pd( __m256d a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Trigonometry

Description

Compute the cosine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*64
    dst[i+63:i] := COS(a[i+63:i])
ENDFOR
dst[MAX:256] := 0


_mm256_cos_ps

__m256 _mm256_cos_ps( __m256 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Trigonometry

Description

Compute the cosine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*32
    dst[i+31:i] := COS(a[i+31:i])
ENDFOR
dst[MAX:256] := 0


_mm256_cosd_pd

__m256d _mm256_cosd_pd( __m256d a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Trigonometry

Description

Compute the cosine of packed double-precision (64-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*64
    dst[i+63:i] := COSD(a[i+63:i])
ENDFOR
dst[MAX:256] := 0


_mm256_cosd_ps

__m256 _mm256_cosd_ps( __m256 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Trigonometry

Description

Compute the cosine of packed single-precision (32-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*32
    dst[i+31:i] := COSD(a[i+31:i])
ENDFOR
dst[MAX:256] := 0


_mm256_cosh_pd

__m256d _mm256_cosh_pd( __m256d a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Trigonometry

Description

Compute the hyperbolic cosine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*64
    dst[i+63:i] := COSH(a[i+63:i])
ENDFOR
dst[MAX:256] := 0


_mm256_cosh_ps

__m256 _mm256_cosh_ps( __m256 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Trigonometry

Description

Compute the hyperbolic cosine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*32
    dst[i+31:i] := COSH(a[i+31:i])
ENDFOR
dst[MAX:256] := 0


_mm256_csqrt_ps

__m256 _mm256_csqrt_ps( __m256 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Elementary Math Functions

Description

Compute the square root of packed complex single-precision (32-bit) floating-point elements in "a", and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*32
    dst[i+31:i] := SQRT(a[i+31:i])
ENDFOR
dst[MAX:256] := 0


_mm256_cvtepi16_epi32

__m256i _mm256_cvtepi16_epi32( __m128i a )

Synopsis

#include "immintrin.h"
Instruction: vpmovsxwd
CPUID Flag: AVX2
Category: Convert

Description

Sign extend packed 16-bit integers in "a" to packed 32-bit integers, and store the results in "dst".

Operation

FOR j:= 0 to 7
    i := 32*j
    k := 16*j
    dst[i+31:i] := SignExtend(a[k+15:k])
ENDFOR
dst[MAX:256] := 0


_mm256_cvtepi16_epi64

__m256i _mm256_cvtepi16_epi64( __m128i a )

Synopsis

#include "immintrin.h"
Instruction: vpmovsxwq
CPUID Flag: AVX2
Category: Convert

Description

Sign extend packed 16-bit integers in "a" to packed 64-bit integers, and store the results in "dst".

Operation

FOR j:= 0 to 3
    i := 64*j
    k := 16*j
    dst[i+63:i] := SignExtend(a[k+15:k])
ENDFOR
dst[MAX:256] := 0


_mm256_cvtepi32_epi64

__m256i _mm256_cvtepi32_epi64( __m128i a )

Synopsis

#include "immintrin.h"
Instruction: vpmovsxdq
CPUID Flag: AVX2
Category: Convert

Description

Sign extend packed 32-bit integers in "a" to packed 64-bit integers, and store the results in "dst".

Operation

FOR j:= 0 to 3
    i := 64*j
    k := 32*j
    dst[i+63:i] := SignExtend(a[k+31:k])
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Haswell |  | 1 | 2
Broadwell |  | 1 | 2
Skylake |  | 1 | 2
Knights Landing | 8 | 7-8 | 2


_mm256_cvtepi32_pd

__m256d _mm256_cvtepi32_pd( __m128i a )

Synopsis

#include "immintrin.h"
Instruction: vcvtdq2pd
CPUID Flag: AVX
Category: Convert

Description

Convert packed 32-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*32
    m := j*64
    dst[m+63:m] := Convert_Int32_To_FP64(a[i+31:i])
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 6 | 2 | 4
Jaguar | 4 | 2 | 2
Sandy Bridge | 5 | 1 | 2
Ivy Bridge | 5 | 1 | 2
Haswell | 6 | 1 | 2
Broadwell | 6 | 1 | 2
Skylake | 7 | 1 | 2
Knights Landing | 7 | 7 | 2
Ivy Bridge | 4 | 1 |
Haswell | 6 | 1 |
Broadwell | 6 | 1 |
Skylake | 7 | 1 |


_mm256_cvtepi32_ps

__m256 _mm256_cvtepi32_ps( __m256i a )

Synopsis

#include "immintrin.h"
Instruction: vcvtdq2ps
CPUID Flag: AVX
Category: Convert

Description

Convert packed 32-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".

Operation

FOR j := 0 to 7
    i := 32*j
    dst[i+31:i] := Convert_Int32_To_FP32(a[i+31:i])
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 4 | 2 | 2
Jaguar | 4 | 2 | 2
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 4 | 0.5 | 1
Knights Landing | 2 | 1 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 4 | 0.5 |


_mm256_cvtepi8_epi16

__m256i _mm256_cvtepi8_epi16( __m128i a )

Synopsis

#include "immintrin.h"
Instruction: vpmovsxbw
CPUID Flag: AVX2
Category: Convert

Description

Sign extend packed 8-bit integers in "a" to packed 16-bit integers, and store the results in "dst".

Operation

FOR j := 0 to 15
    i := j*8
    l := j*16
    dst[l+15:l] := SignExtend(a[i+7:i])
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Haswell |  | 1 | 2
Broadwell |  | 1 | 2
Skylake |  | 1 | 2
Knights Landing | 8 | 7-8 | 2


_mm256_cvtepi8_epi32

__m256i _mm256_cvtepi8_epi32( __m128i a )

Synopsis

#include "immintrin.h"
Instruction: vpmovsxbd
CPUID Flag: AVX2
Category: Convert

Description

Sign extend packed 8-bit integers in "a" to packed 32-bit integers, and store the results in "dst".

Operation

FOR j := 0 to 7
    i := 32*j
    k := 8*j
    dst[i+31:i] := SignExtend(a[k+7:k])
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Haswell |  | 1 | 2
Broadwell |  | 1 | 2
Skylake |  | 1 | 2
Knights Landing | 8 | 7-8 | 2


_mm256_cvtepi8_epi64

__m256i _mm256_cvtepi8_epi64( __m128i a )

Synopsis

#include "immintrin.h"
Instruction: vpmovsxbq
CPUID Flag: AVX2
Category: Convert

Description

Sign extend packed 8-bit integers in the low 8 bytes of "a" to packed 64-bit integers, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := 64*j
    k := 8*j
    dst[i+63:i] := SignExtend(a[k+7:k])
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Haswell |  | 1 | 2
Broadwell |  | 1 | 2
Skylake |  | 1 | 2
Knights Landing | 8 | 7-8 | 2


_mm256_cvtepu16_epi32

__m256i _mm256_cvtepu16_epi32( __m128i a )

Synopsis

#include "immintrin.h"
Instruction: vpmovzxwd
CPUID Flag: AVX2
Category: Convert

Description

Zero extend packed unsigned 16-bit integers in "a" to packed 32-bit integers, and store the results in "dst".

Operation

FOR j := 0 to 7
    i := 32*j
    k := 16*j
    dst[i+31:i] := ZeroExtend(a[k+15:k])
ENDFOR
dst[MAX:256] := 0


_mm256_cvtepu16_epi64

__m256i _mm256_cvtepu16_epi64( __m128i a )

Synopsis

#include "immintrin.h"
Instruction: vpmovzxwq
CPUID Flag: AVX2
Category: Convert

Description

Zero extend packed unsigned 16-bit integers in "a" to packed 64-bit integers, and store the results in "dst".

Operation

FOR j:= 0 to 3
    i := 64*j
    k := 16*j
    dst[i+63:i] := ZeroExtend(a[k+15:k])
ENDFOR
dst[MAX:256] := 0


_mm256_cvtepu32_epi64

__m256i _mm256_cvtepu32_epi64( __m128i a )

Synopsis

#include "immintrin.h"
Instruction: vpmovzxdq
CPUID Flag: AVX2
Category: Convert

Description

Zero extend packed unsigned 32-bit integers in "a" to packed 64-bit integers, and store the results in "dst".

Operation

FOR j:= 0 to 3
    i := 64*j
    k := 32*j
    dst[i+63:i] := ZeroExtend(a[k+31:k])
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Haswell |  | 1 | 2
Broadwell |  | 1 | 2
Skylake |  | 1 | 2
Knights Landing | 3 | 2 | 1


_mm256_cvtepu8_epi16

__m256i _mm256_cvtepu8_epi16( __m128i a )

Synopsis

#include "immintrin.h"
Instruction: vpmovzxbw
CPUID Flag: AVX2
Category: Convert

Description

Zero extend packed unsigned 8-bit integers in "a" to packed 16-bit integers, and store the results in "dst".

Operation

FOR j := 0 to 15
    i := j*8
    l := j*16
    dst[l+15:l] := ZeroExtend(a[i+7:i])
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Haswell |  | 1 | 2
Broadwell |  | 1 | 2
Skylake |  | 1 | 2
Knights Landing | 3 | 2 | 1


_mm256_cvtepu8_epi32

__m256i _mm256_cvtepu8_epi32( __m128i a )

Synopsis

#include "immintrin.h"
Instruction: vpmovzxbd
CPUID Flag: AVX2
Category: Convert

Description

Zero extend packed unsigned 8-bit integers in "a" to packed 32-bit integers, and store the results in "dst".

Operation

FOR j := 0 to 7
    i := 32*j
    k := 8*j
    dst[i+31:i] := ZeroExtend(a[k+7:k])
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Haswell |  | 1 | 2
Broadwell |  | 1 | 2
Skylake |  | 1 | 2
Knights Landing | 3 | 2 | 1


_mm256_cvtepu8_epi64

__m256i _mm256_cvtepu8_epi64( __m128i a )

Synopsis

#include "immintrin.h"
Instruction: vpmovzxbq
CPUID Flag: AVX2
Category: Convert

Description

Zero extend packed unsigned 8-bit integers in the low 8 byte sof "a" to packed 64-bit integers, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := 64*j
    k := 8*j
    dst[i+63:i] := ZeroExtend(a[k+7:k])
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Haswell |  | 1 | 2
Broadwell |  | 1 | 2
Skylake |  | 1 | 2
Knights Landing | 3 | 2 | 1


_mm256_cvtpd_epi32

__m128i _mm256_cvtpd_epi32( __m256d a )

Synopsis

#include "immintrin.h"
Instruction: vcvtpd2dq
CPUID Flag: AVX
Category: Convert

Description

Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := 32*j
    k := 64*j
    dst[i+31:i] := Convert_FP64_To_Int32(a[k+63:k])
ENDFOR
dst[MAX:128] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 6 | 2 | 4
Jaguar | 7 | 2 | 3
Sandy Bridge | 5 | 1 | 2
Ivy Bridge | 5 | 1 | 2
Haswell | 6 | 1 | 2
Broadwell | 6 | 1 | 2
Skylake | 7 | 1 | 2
Knights Landing | 7 | 7 | 2
Ivy Bridge | 4 | 1 |
Haswell | 6 | 1 |
Broadwell | 6 | 1 |
Skylake | 7 | 1 |


_mm256_cvtpd_ps

__m128 _mm256_cvtpd_ps( __m256d a )

Synopsis

#include "immintrin.h"
Instruction: vcvtpd2ps
CPUID Flag: AVX
Category: Convert

Description

Convert packed double-precision (64-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := 32*j
    k := 64*j
    dst[i+31:i] := Convert_FP64_To_FP32(a[k+63:k])
ENDFOR
dst[MAX:128] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 5 | 2 | 2
Jaguar | 6 | 2 | 3
Sandy Bridge | 4 | 1 | 2
Ivy Bridge | 4 | 1 | 2
Haswell | 5 | 1 | 2
Broadwell | 5 | 1 | 2
Skylake | 7 | 1 | 2
Knights Landing | 7 | 7 | 2
Ivy Bridge | 4 | 1 |
Haswell | 6 | 1 |
Broadwell | 6 | 1 |
Skylake | 7 | 1 |


_mm256_cvtph_ps

__m256 _mm256_cvtph_ps( __m128i a )

Synopsis

#include "immintrin.h"
Instruction: vcvtph2ps
CPUID Flag: FP16C
Category: Convert

Description

Convert packed half-precision (16-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*32
    m := j*16
    dst[i+31:i] := Convert_FP16_To_FP32(a[m+15:m])
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 6 | 2 | 2
Jaguar | 5 | 2 | 2
Ivy Bridge | 6 | 1 | 2
Haswell | 4 | 1 | 2
Broadwell | 4-6 | 1 | 2
Skylake | 5-7 | 1 | 2
Knights Landing | 7 | 7 | 2
Ivy Bridge | 7 | 1 |
Haswell | 6 | 1 |
Broadwell | 6 | 1 |
Skylake | 7 | 1 |


_mm256_cvtps_epi32

__m256i _mm256_cvtps_epi32( __m256 a )

Synopsis

#include "immintrin.h"
Instruction: vcvtps2dq
CPUID Flag: AVX
Category: Convert

Description

Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst".

Operation

FOR j := 0 to 7
    i := 32*j
    dst[i+31:i] := Convert_FP32_To_Int32(a[i+31:i])
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Jaguar | 4 | 2 | 2
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 4 | 1 |


_mm256_cvtps_pd

__m256d _mm256_cvtps_pd( __m128 a )

Synopsis

#include "immintrin.h"
Instruction: vcvtps2pd
CPUID Flag: AVX
Category: Convert

Description

Convert packed single-precision (32-bit) floating-point elements in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := 64*j
    k := 32*j
    dst[i+63:i] := Convert_FP32_To_FP64(a[k+31:k])
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 5 | 2 | 2
Jaguar | 4 | 2 | 2
Sandy Bridge | 4 | 1 | 2
Ivy Bridge | 4 | 1 | 2
Haswell | 5 | 1 | 2
Broadwell | 5 | 1 | 2
Skylake | 7 | 1 | 2
Knights Landing | 7 | 7 | 2
Ivy Bridge | 2 | 1 |
Haswell | 4 | 1 |
Broadwell | 4 | 1 |
Skylake | 7 | 1 |


_mm256_cvtps_ph

__m128i _mm256_cvtps_ph( __m256 a, int rounding )

Synopsis

#include "immintrin.h"
Instruction: vcvtps2ph
CPUID Flag: FP16C
Category: Convert

Description

Convert packed single-precision (32-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst". [round_note]

Operation

FOR j := 0 to 7
    i := 16*j
    l := 32*j
    dst[i+15:i] := Convert_FP32_To_FP16(a[l+31:l])
ENDFOR
dst[MAX:128] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 6 | 2 | 2
Jaguar | 6 | 2 | 3
Ivy Bridge | 10 | 1 | 3
Haswell | 4 | 1 | 2
Broadwell | 4-6 | 1 | 2
Skylake | 5-7 | 1 | 2
Knights Landing | 7 | 7 | 2
Ivy Bridge | 9 | 1 |
Haswell | 4 | 1 |
Broadwell | 4 | 1 |
Skylake | 5 | 1 |


_mm256_cvtsd_f64

double _mm256_cvtsd_f64( __m256d a )

Synopsis

#include "immintrin.h"
Instruction: movsd
CPUID Flag: AVX2
Category: Convert

Description

Copy the lower double-precision (64-bit) floating-point element of "a" to "dst".

Operation

dst[63:0] := a[63:0]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 4 | 0.5 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 3 | 0.5 | 1
Ivy Bridge | 3 | 0.5 | 1
Haswell | 3 | 0.5 | 1
Broadwell | 3 | 0.5 | 1
Skylake | 3 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1


_mm256_cvtsi256_si32

int _mm256_cvtsi256_si32( __m256i a )

Synopsis

#include "immintrin.h"
Instruction: movd
CPUID Flag: AVX2
Category: Convert

Description

Copy the lower 32-bit integer in "a" to "dst".

Operation

dst[31:0] := a[31:0]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 1 | 1
Jaguar | 4 | 1 | 1
Sandy Bridge | 1 |  | 1
Ivy Bridge | 1 | 1 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 2 | 1 | 1
Knights Landing | 4 | 1 | 1


_mm256_cvtss_f32

float _mm256_cvtss_f32( __m256 a )

Synopsis

#include "immintrin.h"
Instruction: movss
CPUID Flag: AVX
Category: Convert

Description

Copy the lower single-precision (32-bit) floating-point element of "a" to "dst".

Operation

dst[31:0] := a[31:0]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 4 | 0.5 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 3 | 0.5 | 1
Ivy Bridge | 3 | 0.5 | 1
Haswell | 3 | 0.5 | 1
Broadwell | 3 | 0.5 | 1
Skylake | 3 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1


_mm256_cvttpd_epi32

__m128i _mm256_cvttpd_epi32( __m256d a )

Synopsis

#include "immintrin.h"
Instruction: vcvttpd2dq
CPUID Flag: AVX
Category: Convert

Description

Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := 32*j
    k := 64*j
    dst[i+31:i] := Convert_FP64_To_Int32_Truncate(a[k+63:k])
ENDFOR
dst[MAX:128] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 6 | 2 | 4
Jaguar | 7 | 2 | 3
Sandy Bridge | 5 | 1 | 2
Ivy Bridge | 5 | 1 | 2
Haswell | 6 | 1 | 2
Broadwell | 6 | 1 | 2
Skylake | 7 | 1 | 2
Knights Landing | 7 | 7 | 2
Ivy Bridge | 4 | 1 |
Haswell | 6 | 1 |
Broadwell | 6 | 1 |
Skylake | 7 | 1 |


_mm256_cvttps_epi32

__m256i _mm256_cvttps_epi32( __m256 a )

Synopsis

#include "immintrin.h"
Instruction: vcvttps2dq
CPUID Flag: AVX
Category: Convert

Description

Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst".

Operation

FOR j := 0 to 7
    i := 32*j
    dst[i+31:i] := Convert_FP32_To_Int32_Truncate(a[i+31:i])
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Jaguar | 4 | 2 | 2
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 4 | 1 |


_mm256_div_epi16

__m256i _mm256_div_epi16( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Arithmetic

Description

Divide packed 16-bit integers in "a" by packed elements in "b", and store the truncated results in "dst".

Operation

FOR j := 0 to 15
    i := 16*j
    dst[i+15:i] := TRUNCATE(a[i+15:i] / b[i+15:i])
ENDFOR
dst[MAX:256] := 0


_mm256_div_epi32

__m256i _mm256_div_epi32( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Arithmetic

Description

Divide packed 32-bit integers in "a" by packed elements in "b", and store the truncated results in "dst".

Operation

FOR j := 0 to 7
    i := 32*j
    dst[i+31:i] := TRUNCATE(a[i+31:i] / b[i+31:i])
ENDFOR
dst[MAX:256] := 0


_mm256_div_epi64

__m256i _mm256_div_epi64( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Arithmetic

Description

Divide packed 64-bit integers in "a" by packed elements in "b", and store the truncated results in "dst".

Operation

FOR j := 0 to 3
    i := 64*j
    dst[i+63:i] := TRUNCATE(a[i+63:i] / b[i+63:i])
ENDFOR
dst[MAX:256] := 0


_mm256_div_epi8

__m256i _mm256_div_epi8( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Arithmetic

Description

Divide packed 8-bit integers in "a" by packed elements in "b", and store the truncated results in "dst".

Operation

FOR j := 0 to 31
    i := 8*j
    dst[i+7:i] := TRUNCATE(a[i+7:i] / b[i+7:i])
ENDFOR
dst[MAX:256] := 0


_mm256_div_epu16

__m256i _mm256_div_epu16( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Arithmetic

Description

Divide packed unsigned 16-bit integers in "a" by packed elements in "b", and store the truncated results in "dst".

Operation

FOR j := 0 to 15
    i := 16*j
    dst[i+15:i] := TRUNCATE(a[i+15:i] / b[i+15:i])
ENDFOR
dst[MAX:256] := 0


_mm256_div_epu32

__m256i _mm256_div_epu32( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Arithmetic

Description

Divide packed unsigned 32-bit integers in "a" by packed elements in "b", and store the truncated results in "dst".

Operation

FOR j := 0 to 7
    i := 32*j
    dst[i+31:i] := TRUNCATE(a[i+31:i] / b[i+31:i])
ENDFOR
dst[MAX:256] := 0


_mm256_div_epu64

__m256i _mm256_div_epu64( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Arithmetic

Description

Divide packed unsigned 64-bit integers in "a" by packed elements in "b", and store the truncated results in "dst".

Operation

FOR j := 0 to 3
    i := 64*j
    dst[i+63:i] := TRUNCATE(a[i+63:i] / b[i+63:i])
ENDFOR
dst[MAX:256] := 0


_mm256_div_epu8

__m256i _mm256_div_epu8( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Arithmetic

Description

Divide packed unsigned 8-bit integers in "a" by packed elements in "b", and store the truncated results in "dst".

Operation

FOR j := 0 to 31
    i := 8*j
    dst[i+7:i] := TRUNCATE(a[i+7:i] / b[i+7:i])
ENDFOR
dst[MAX:256] := 0


_mm256_div_pd

__m256d _mm256_div_pd( __m256d a, __m256d b )

Synopsis

#include "immintrin.h"
Instruction: vdivpd
CPUID Flag: AVX
Category: Arithmetic

Description

Divide packed double-precision (64-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst".

Operation

FOR j := 0 to 3
    i := 64*j
    dst[i+63:i] := a[i+63:i] / b[i+63:i]
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 8-13 | 8-9 | 2
Jaguar | 38 | 38 | 2
Sandy Bridge | 21-45 | 20-44 | 3
Ivy Bridge | 20-35 | 16-28 | 3
Haswell | 19-35 | 16-28 | 3
Broadwell | 19-23 | 16 | 3
Skylake | 13-14 | 8 | 1
Knights Landing | 32 | 32 | 18
Ivy Bridge | 27-35 | 28 |
Haswell | 25-35 | 27 |
Broadwell | 16-23 | 16 |
Skylake | 14 | 8 |
Knights Landing | 38 | ~10 |


_mm256_div_ps

__m256 _mm256_div_ps( __m256 a, __m256 b )

Synopsis

#include "immintrin.h"
Instruction: vdivps
CPUID Flag: AVX
Category: Arithmetic

Description

Divide packed single-precision (32-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst".

Operation

FOR j := 0 to 7
    i := 32*j
    dst[i+31:i] := a[i+31:i] / b[i+31:i]
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 10 | 6 | 2
Jaguar | 38 | 38 | 2
Sandy Bridge | 21-29 | 20-28 | 3
Ivy Bridge | 19-21 | 14 | 3
Haswell | 18-21 | 14 | 3
Broadwell | 17 | 10 | 3
Skylake | 11 | 5 | 1
Knights Landing | 32 | 32 | 18
Ivy Bridge | 18-21 | 14 |
Haswell | 17-21 | 13 |
Broadwell | 13-17 | 10 |
Skylake | 11 | 5 |
Knights Landing | 38 | ~10 |


_mm256_dp_ps

__m256 _mm256_dp_ps( __m256 a, __m256 b, const int imm8 )

Synopsis

#include "immintrin.h"
Instruction: vdpps
CPUID Flag: AVX
Category: Arithmetic

Description

Conditionally multiply the packed single-precision (32-bit) floating-point elements in "a" and "b" using the high 4 bits in "imm8", sum the four products, and conditionally store the sum in "dst" using the low 4 bits of "imm8".

Operation

DEFINE DP(a[127:0], b[127:0], imm8[7:0]) {
    FOR j := 0 to 3
        i := j*32
        IF imm8[(4+j)%8]
            temp[i+31:i] := a[i+31:i] * b[i+31:i]
        ELSE
            temp[i+31:i] := 0
        FI
    ENDFOR

    sum[31:0] := (temp[127:96] + temp[95:64]) + (temp[63:32] + temp[31:0])

    FOR j := 0 to 3
        i := j*32
        IF imm8[j%8]
            tmpdst[i+31:i] := sum[31:0]
        ELSE
            tmpdst[i+31:i] := 0
        FI
    ENDFOR
    RETURN tmpdst[127:0]
}
dst[127:0] := DP(a[127:0], b[127:0], imm8[7:0])
dst[255:128] := DP(a[255:128], b[255:128], imm8[7:0])
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 16 | 5 | 13
Jaguar | 12 | 7 | 10
Sandy Bridge | 12 | 2 | 4
Ivy Bridge | 12 | 2 | 4
Haswell | 14 | 2 | 4
Broadwell | 12 | 2 | 4
Skylake | 13 | 1.5 | 4
Knights Landing | 36 | 13 | 14
Ivy Bridge | 12 | 2 |
Haswell | 14 | 2 |
Broadwell | 12 | 2 |
Skylake | 13 | 1.5 |


_mm256_erf_pd

__m256d _mm256_erf_pd( __m256d a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Probability/Statistics

Description

Compute the error function of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*64
    dst[i+63:i] := ERF(a[i+63:i])
ENDFOR
dst[MAX:256] := 0


_mm256_erf_ps

__m256 _mm256_erf_ps( __m256 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Probability/Statistics

Description

Compute the error function of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*32
    dst[i+31:i] := ERF(a[i+31:i])
ENDFOR
dst[MAX:256] := 0


_mm256_erfc_pd

__m256d _mm256_erfc_pd( __m256d a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Probability/Statistics

Description

Compute the complementary error function of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*64
    dst[i+63:i] := 1.0 - ERF(a[i+63:i])
ENDFOR
dst[MAX:256] := 0


_mm256_erfc_ps

__m256 _mm256_erfc_ps( __m256 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Probability/Statistics

Description

Compute the complementary error function of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*32
    dst[i+31:i] := 1.0 - ERF(a[i+31:i])
ENDFOR
dst[MAX:256] := 0


_mm256_erfcinv_pd

__m256d _mm256_erfcinv_pd( __m256d a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Probability/Statistics

Description

Compute the inverse complementary error function of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*64
    dst[i+63:i] := 1.0 / (1.0 - ERF(a[i+63:i]))
ENDFOR
dst[MAX:256] := 0


_mm256_erfcinv_ps

__m256 _mm256_erfcinv_ps( __m256 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Probability/Statistics

Description

Compute the inverse complementary error function of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*32
    dst[i+31:i] := 1.0 / (1.0 - ERF(a[i+31:i]))
ENDFOR
dst[MAX:256] := 0


_mm256_erfinv_pd

__m256d _mm256_erfinv_pd( __m256d a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Probability/Statistics

Description

Compute the inverse error function of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*64
    dst[i+63:i] := 1.0 / ERF(a[i+63:i])
ENDFOR
dst[MAX:256] := 0


_mm256_erfinv_ps

__m256 _mm256_erfinv_ps( __m256 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Probability/Statistics

Description

Compute the inverse error function of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*32
    dst[i+31:i] := 1.0 / ERF(a[i+31:i])
ENDFOR
dst[MAX:256] := 0


_mm256_exp_pd

__m256d _mm256_exp_pd( __m256d a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Elementary Math Functions

Description

Compute the exponential value of "e" raised to the power of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*64
    dst[i+63:i] := e^(a[i+63:i])
ENDFOR
dst[MAX:256] := 0


_mm256_exp_ps

__m256 _mm256_exp_ps( __m256 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Elementary Math Functions

Description

Compute the exponential value of "e" raised to the power of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*32
    dst[i+31:i] := e^(a[i+31:i])
ENDFOR
dst[MAX:256] := 0


_mm256_exp10_pd

__m256d _mm256_exp10_pd( __m256d a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Elementary Math Functions

Description

Compute the exponential value of 10 raised to the power of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*64
    dst[i+63:i] := 10^(a[i+63:i])
ENDFOR
dst[MAX:256] := 0


_mm256_exp10_ps

__m256 _mm256_exp10_ps( __m256 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Elementary Math Functions

Description

Compute the exponential value of 10 raised to the power of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*32
    dst[i+31:i] := 10^(a[i+31:i])
ENDFOR
dst[MAX:256] := 0


_mm256_exp2_pd

__m256d _mm256_exp2_pd( __m256d a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Elementary Math Functions

Description

Compute the exponential value of 2 raised to the power of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*64
    dst[i+63:i] := 2^(a[i+63:i])
ENDFOR
dst[MAX:256] := 0


_mm256_exp2_ps

__m256 _mm256_exp2_ps( __m256 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Elementary Math Functions

Description

Compute the exponential value of 2 raised to the power of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*32
    dst[i+31:i] := 2^(a[i+31:i])
ENDFOR
dst[MAX:256] := 0


_mm256_expm1_pd

__m256d _mm256_expm1_pd( __m256d a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Elementary Math Functions

Description

Compute the exponential value of "e" raised to the power of packed double-precision (64-bit) floating-point elements in "a", subtract one from each element, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*64
    dst[i+63:i] := e^(a[i+63:i]) - 1.0
ENDFOR
dst[MAX:256] := 0


_mm256_expm1_ps

__m256 _mm256_expm1_ps( __m256 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Elementary Math Functions

Description

Compute the exponential value of "e" raised to the power of packed single-precision (32-bit) floating-point elements in "a", subtract one from each element, and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*32
    dst[i+31:i] := e^(a[i+31:i]) - 1.0
ENDFOR
dst[MAX:256] := 0


_mm256_extract_epi16

int _mm256_extract_epi16( __m256i a, const int index )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX2
Category: Swizzle

Description

Extract a 16-bit integer from "a", selected with "index", and store the result in "dst".

Operation

dst[15:0] := (a[255:0] >> (index * 16))[15:0]


_mm256_extract_epi32

__int32 _mm256_extract_epi32( __m256i a, const int index )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Swizzle

Description

Extract a 32-bit integer from "a", selected with "index", and store the result in "dst".

Operation

dst[31:0] := (a[255:0] >> (index * 32))[31:0]


_mm256_extract_epi64

__int64 _mm256_extract_epi64( __m256i a, const int index )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Swizzle

Description

Extract a 64-bit integer from "a", selected with "index", and store the result in "dst".

Operation

dst[63:0] := (a[255:0] >> (index * 64))[63:0]


_mm256_extract_epi8

int _mm256_extract_epi8( __m256i a, const int index )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX2
Category: Swizzle

Description

Extract an 8-bit integer from "a", selected with "index", and store the result in "dst".

Operation

dst[7:0] := (a[255:0] >> (index * 8))[7:0]


_mm256_extractf128_pd

__m128d _mm256_extractf128_pd( __m256d a, const int imm8 )

Synopsis

#include "immintrin.h"
Instruction: vextractf128
CPUID Flag: AVX
Category: Swizzle

Description

Extract 128 bits (composed of 2 packed double-precision (64-bit) floating-point elements) from "a", selected with "imm8", and store the result in "dst".

Operation

CASE imm8[7:0] OF
0: dst[127:0] := a[127:0]
1: dst[127:0] := a[255:128]
ESAC
dst[MAX:128] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 2 | 1 | 1
Ivy Bridge | 2 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 3 | 1 | 1
Knights Landing | 3-6 | 1 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 3 | 1 |


_mm256_extractf128_ps

__m128 _mm256_extractf128_ps( __m256 a, const int imm8 )

Synopsis

#include "immintrin.h"
Instruction: vextractf128
CPUID Flag: AVX
Category: Swizzle

Description

Extract 128 bits (composed of 4 packed single-precision (32-bit) floating-point elements) from "a", selected with "imm8", and store the result in "dst".

Operation

CASE imm8[7:0] OF
0: dst[127:0] := a[127:0]
1: dst[127:0] := a[255:128]
ESAC
dst[MAX:128] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 2 | 1 | 1
Ivy Bridge | 2 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 3 | 1 | 1
Knights Landing | 3-6 | 1 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 3 | 1 |


_mm256_extractf128_si256

__m128i _mm256_extractf128_si256( __m256i a, const int imm8 )

Synopsis

#include "immintrin.h"
Instruction: vextractf128
CPUID Flag: AVX
Category: Swizzle

Description

Extract 128 bits (composed of integer data) from "a", selected with "imm8", and store the result in "dst".

Operation

CASE imm8[7:0] OF
0: dst[127:0] := a[127:0]
1: dst[127:0] := a[255:128]
ESAC
dst[MAX:128] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.33 | 1
Jaguar | 1 | 0.5 | 1
Sandy Bridge | 2 | 1 | 1
Ivy Bridge | 2 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 3 | 1 | 1
Knights Landing | 3-6 | 1 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 3 | 1 |


_mm256_extracti128_si256

__m128i _mm256_extracti128_si256( __m256i a, const int imm8 )

Synopsis

#include "immintrin.h"
Instruction: vextracti128
CPUID Flag: AVX2
Category: Swizzle

Description

Extract 128 bits (composed of integer data) from "a", selected with "imm8", and store the result in "dst".

Operation

CASE imm8[7:0] OF
0: dst[127:0] := a[127:0]
1: dst[127:0] := a[255:128]
ESAC
dst[MAX:128] := 0

Performance

Architecture | Latency | Throughput | μops
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 3 | 1 | 1
Knights Landing | 3-6 | 1 | 1
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm256_floor_pd

__m256d _mm256_floor_pd( __m256d a )

Synopsis

#include "immintrin.h"
Instruction: vroundpd
CPUID Flag: AVX
Category: Special Math Functions

Description

Round the packed double-precision (64-bit) floating-point elements in "a" down to an integer value, and store the results as packed double-precision floating-point elements in "dst".

Operation

FOR j := 0 to 3
    i := j*64
    dst[i+63:i] := FLOOR(a[i+63:i])
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 4 | 2 | 2
Jaguar | 4 | 2 | 2
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 6 | 2 | 2
Broadwell | 6 | 2 | 2
Skylake | 8 | 1 | 2
Knights Landing | 6 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 6 | 2 |
Broadwell | 6 | 2 |
Skylake | 8 | 1 |


_mm256_floor_ps

__m256 _mm256_floor_ps( __m256 a )

Synopsis

#include "immintrin.h"
Instruction: vroundps
CPUID Flag: AVX
Category: Special Math Functions

Description

Round the packed single-precision (32-bit) floating-point elements in "a" down to an integer value, and store the results as packed single-precision floating-point elements in "dst".

Operation

FOR j := 0 to 7
    i := j*32
    dst[i+31:i] := FLOOR(a[i+31:i])
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 4 | 2 | 2
Jaguar | 4 | 2 | 2
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 6 | 2 | 2
Broadwell | 6 | 2 | 2
Skylake | 8 | 1 | 2
Knights Landing | 6 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 6 | 2 |
Broadwell | 6 | 2 |
Skylake | 8 | 1 |


_mm256_fmadd_pd

__m256d _mm256_fmadd_pd( __m256d a, __m256d b, __m256d c )

Synopsis

#include "immintrin.h"
Instruction: vfmadd132pd
CPUID Flag: FMA
Category: Arithmetic

Description

Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*64
    dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 5 | 0.5 | 1
Haswell | 5 | 0.5 |
Broadwell | 5 | 0.5 |
Skylake | 4 | 0.5 |
Knights Landing | 6 | 0.5 |


_mm256_fmadd_ps

__m256 _mm256_fmadd_ps( __m256 a, __m256 b, __m256 c )

Synopsis

#include "immintrin.h"
Instruction: vfmadd132ps
CPUID Flag: FMA
Category: Arithmetic

Description

Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*32
    dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 5 | 0.5 | 1
Haswell | 5 | 0.5 |
Broadwell | 5 | 0.5 |
Skylake | 4 | 0.5 |
Knights Landing | 6 | 0.5 |


_mm256_fmaddsub_pd

__m256d _mm256_fmaddsub_pd( __m256d a, __m256d b, __m256d c )

Synopsis

#include "immintrin.h"
Instruction: vfmaddsub132pd
CPUID Flag: FMA
Category: Arithmetic

Description

Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*64
    IF (j % 1 == 0)
        dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
    ELSE
        dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
    FI
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Haswell | 5 | 0.5 |
Broadwell | 5 | 0.5 |
Skylake | 4 | 0.5 |
Knights Landing | 6 | 0.5 |


_mm256_fmaddsub_ps

__m256 _mm256_fmaddsub_ps( __m256 a, __m256 b, __m256 c )

Synopsis

#include "immintrin.h"
Instruction: vfmaddsub132ps
CPUID Flag: FMA
Category: Arithmetic

Description

Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*32
    IF (j % 1 == 0)
        dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
    ELSE
        dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
    FI
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Haswell | 5 | 0.5 |
Broadwell | 5 | 0.5 |
Skylake | 4 | 0.5 |
Knights Landing | 6 | 0.5 |


_mm256_fmsub_pd

__m256d _mm256_fmsub_pd( __m256d a, __m256d b, __m256d c )

Synopsis

#include "immintrin.h"
Instruction: vfmsub132pd
CPUID Flag: FMA
Category: Arithmetic

Description

Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*64
    dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Haswell | 5 | 0.5 |
Broadwell | 5 | 0.5 |
Skylake | 4 | 0.5 |
Knights Landing | 6 | 0.5 |


_mm256_fmsub_ps

__m256 _mm256_fmsub_ps( __m256 a, __m256 b, __m256 c )

Synopsis

#include "immintrin.h"
Instruction: vfmsub132ps
CPUID Flag: FMA
Category: Arithmetic

Description

Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*32
    dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Haswell | 5 | 0.5 |
Broadwell | 5 | 0.5 |
Skylake | 4 | 0.5 |
Knights Landing | 6 | 0.5 |


_mm256_fmsubadd_pd

__m256d _mm256_fmsubadd_pd( __m256d a, __m256d b, __m256d c )

Synopsis

#include "immintrin.h"
Instruction: vfmsubadd132pd
CPUID Flag: FMA
Category: Arithmetic

Description

Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*64
    IF (j % 1 == 0)
        dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
    ELSE
        dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
    FI
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Haswell | 5 | 0.5 |
Broadwell | 5 | 0.5 |
Skylake | 4 | 0.5 |
Knights Landing | 6 | 0.5 |


_mm256_fmsubadd_ps

__m256 _mm256_fmsubadd_ps( __m256 a, __m256 b, __m256 c )

Synopsis

#include "immintrin.h"
Instruction: vfmsubadd132ps
CPUID Flag: FMA
Category: Arithmetic

Description

Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*32
    IF (j % 1 == 0)
        dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
    ELSE
        dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
    FI
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Haswell | 5 | 0.5 |
Broadwell | 5 | 0.5 |
Skylake | 4 | 0.5 |
Knights Landing | 6 | 0.5 |


_mm256_fnmadd_pd

__m256d _mm256_fnmadd_pd( __m256d a, __m256d b, __m256d c )

Synopsis

#include "immintrin.h"
Instruction: vfnmadd132pd
CPUID Flag: FMA
Category: Arithmetic

Description

Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*64
    dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) + c[i+63:i]
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Haswell | 5 | 0.5 |
Broadwell | 5 | 0.5 |
Skylake | 4 | 0.5 |
Knights Landing | 6 | 0.5 |


_mm256_fnmadd_ps

__m256 _mm256_fnmadd_ps( __m256 a, __m256 b, __m256 c )

Synopsis

#include "immintrin.h"
Instruction: vfnmadd132ps
CPUID Flag: FMA
Category: Arithmetic

Description

Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*32
    a[i+31:i] := -(a[i+31:i] * b[i+31:i]) + c[i+31:i]
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Haswell | 5 | 0.5 |
Broadwell | 5 | 0.5 |
Skylake | 4 | 0.5 |
Knights Landing | 6 | 0.5 |


_mm256_fnmsub_pd

__m256d _mm256_fnmsub_pd( __m256d a, __m256d b, __m256d c )

Synopsis

#include "immintrin.h"
Instruction: vfnmsub132pd
CPUID Flag: FMA
Category: Arithmetic

Description

Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*64
    dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) - c[i+63:i]
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Haswell | 5 | 0.5 |
Broadwell | 5 | 0.5 |
Skylake | 4 | 0.5 |
Knights Landing | 6 | 0.5 |


_mm256_fnmsub_ps

__m256 _mm256_fnmsub_ps( __m256 a, __m256 b, __m256 c )

Synopsis

#include "immintrin.h"
Instruction: vfnmsub132ps
CPUID Flag: FMA
Category: Arithmetic

Description

Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*32
    dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) - c[i+31:i]
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Haswell | 5 | 0.5 |
Broadwell | 5 | 0.5 |
Skylake | 4 | 0.5 |
Knights Landing | 6 | 0.5 |


_mm256_hadd_epi16

__m256i _mm256_hadd_epi16( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: vphaddw
CPUID Flag: AVX2
Category: Arithmetic

Description

Horizontally add adjacent pairs of 16-bit integers in "a" and "b", and pack the signed 16-bit results in "dst".

Operation

dst[15:0] := a[31:16] + a[15:0]
dst[31:16] := a[63:48] + a[47:32]
dst[47:32] := a[95:80] + a[79:64]
dst[63:48] := a[127:112] + a[111:96]
dst[79:64] := b[31:16] + b[15:0]
dst[95:80] := b[63:48] + b[47:32]
dst[111:96] := b[95:80] + b[79:64]
dst[127:112] := b[127:112] + b[111:96]
dst[143:128] := a[159:144] + a[143:128]
dst[159:144] := a[191:176] + a[175:160]
dst[175:160] := a[223:208] + a[207:192]
dst[191:176] := a[255:240] + a[239:224]
dst[207:192] := b[127:112] + b[143:128]
dst[223:208] := b[159:144] + b[175:160]
dst[239:224] := b[191:176] + b[207:192]
dst[255:240] := b[223:208] + b[239:224]
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 3 | 8
Haswell | 3 | 2 | 3
Broadwell | 3 | 2 | 3
Skylake | 3 | 2 | 3
Haswell | 3 | 2 |
Broadwell | 3 | 2 |
Skylake | 3 | 2 |


_mm256_hadd_epi32

__m256i _mm256_hadd_epi32( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: vphaddd
CPUID Flag: AVX2
Category: Arithmetic

Description

Horizontally add adjacent pairs of 32-bit integers in "a" and "b", and pack the signed 32-bit results in "dst".

Operation

dst[31:0] := a[63:32] + a[31:0]
dst[63:32] := a[127:96] + a[95:64]
dst[95:64] := b[63:32] + b[31:0]
dst[127:96] := b[127:96] + b[95:64]
dst[159:128] := a[191:160] + a[159:128]
dst[191:160] := a[255:224] + a[223:192]
dst[223:192] := b[191:160] + b[159:128]
dst[255:224] := b[255:224] + b[223:192]
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 3 | 8
Haswell | 3 | 2 | 3
Broadwell | 3 | 2 | 3
Skylake | 3 | 2 | 3
Knights Landing | 11 | 8 | 3
Haswell | 3 | 2 |
Broadwell | 3 | 2 |
Skylake | 3 | 2 |


_mm256_hadd_pd

__m256d _mm256_hadd_pd( __m256d a, __m256d b )

Synopsis

#include "immintrin.h"
Instruction: vhaddpd
CPUID Flag: AVX
Category: Arithmetic

Description

Horizontally add adjacent pairs of double-precision (64-bit) floating-point elements in "a" and "b", and pack the results in "dst".

Operation

dst[63:0] := a[127:64] + a[63:0]
dst[127:64] := b[127:64] + b[63:0]
dst[191:128] := a[255:192] + a[191:128]
dst[255:192] := b[255:192] + b[191:128]
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 7 | 3 | 8
Jaguar | 4 | 2 | 2
Sandy Bridge | 5 | 2 | 3
Ivy Bridge | 5 | 2 | 3
Haswell | 5 | 2 | 3
Broadwell | 5 | 2 | 3
Skylake | 6 | 2 | 3
Knights Landing | 15 | 8 | 3


_mm256_hadd_ps

__m256 _mm256_hadd_ps( __m256 a, __m256 b )

Synopsis

#include "immintrin.h"
Instruction: vhaddps
CPUID Flag: AVX
Category: Arithmetic

Description

Horizontally add adjacent pairs of single-precision (32-bit) floating-point elements in "a" and "b", and pack the results in "dst".

Operation

dst[31:0] := a[63:32] + a[31:0]
dst[63:32] := a[127:96] + a[95:64]
dst[95:64] := b[63:32] + b[31:0]
dst[127:96] := b[127:96] + b[95:64]
dst[159:128] := a[191:160] + a[159:128]
dst[191:160] := a[255:224] + a[223:192]
dst[223:192] := b[191:160] + b[159:128]
dst[255:224] := b[255:224] + b[223:192]
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 7 | 3 | 8
Jaguar | 4 | 2 | 2
Sandy Bridge | 5 | 2 | 3
Ivy Bridge | 5 | 2 | 3
Haswell | 5 | 2 | 3
Broadwell | 5 | 2 | 3
Skylake | 6 | 2 | 3
Knights Landing | 15 | 8 | 3


_mm256_hadds_epi16

__m256i _mm256_hadds_epi16( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: vphaddsw
CPUID Flag: AVX2
Category: Arithmetic

Description

Horizontally add adjacent pairs of 16-bit integers in "a" and "b" using saturation, and pack the signed 16-bit results in "dst".

Operation

dst[15:0] := Saturate_To_Int16(a[31:16] + a[15:0])
dst[31:16] := Saturate_To_Int16(a[63:48] + a[47:32])
dst[47:32] := Saturate_To_Int16(a[95:80] + a[79:64])
dst[63:48] := Saturate_To_Int16(a[127:112] + a[111:96])
dst[79:64] := Saturate_To_Int16(b[31:16] + b[15:0])
dst[95:80] := Saturate_To_Int16(b[63:48] + b[47:32])
dst[111:96] := Saturate_To_Int16(b[95:80] + b[79:64])
dst[127:112] := Saturate_To_Int16(b[127:112] + b[111:96])
dst[143:128] := Saturate_To_Int16(a[159:144] + a[143:128])
dst[159:144] := Saturate_To_Int16(a[191:176] + a[175:160])
dst[175:160] := Saturate_To_Int16(a[223:208] + a[207:192])
dst[191:176] := Saturate_To_Int16(a[255:240] + a[239:224])
dst[207:192] := Saturate_To_Int16(b[127:112] + b[143:128])
dst[223:208] := Saturate_To_Int16(b[159:144] + b[175:160])
dst[239:224] := Saturate_To_Int16(b[191:160] + b[159:128])
dst[255:240] := Saturate_To_Int16(b[255:240] + b[239:224])
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 3 | 8
Haswell | 3 | 2 | 3
Broadwell | 3 | 2 | 3
Skylake | 3 | 2 | 3
Haswell | 3 | 2 |
Broadwell | 3 | 2 |
Skylake | 3 | 2 |


_mm256_hsub_epi16

__m256i _mm256_hsub_epi16( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: vphsubw
CPUID Flag: AVX2
Category: Arithmetic

Description

Horizontally subtract adjacent pairs of 16-bit integers in "a" and "b", and pack the signed 16-bit results in "dst".

Operation

dst[15:0] := a[15:0] - a[31:16]
dst[31:16] := a[47:32] - a[63:48]
dst[47:32] := a[79:64] - a[95:80]
dst[63:48] := a[111:96] - a[127:112]
dst[79:64] := b[15:0] - b[31:16]
dst[95:80] := b[47:32] - b[63:48]
dst[111:96] := b[79:64] - b[95:80]
dst[127:112] := b[111:96] - b[127:112]
dst[143:128] := a[143:128] - a[159:144]
dst[159:144] := a[175:160] - a[191:176]
dst[175:160] := a[207:192] - a[223:208]
dst[191:176] := a[239:224] - a[255:240]
dst[207:192] := b[143:128] - b[159:144]
dst[223:208] := b[175:160] - b[191:176]
dst[239:224] := b[207:192] - b[223:208]
dst[255:240] := b[239:224] - b[255:240]
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 3 | 8
Haswell | 3 | 2 | 3
Broadwell | 3 | 2 | 3
Skylake | 3 | 2 | 3


_mm256_hsub_epi32

__m256i _mm256_hsub_epi32( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: vphsubd
CPUID Flag: AVX2
Category: Arithmetic

Description

Horizontally subtract adjacent pairs of 32-bit integers in "a" and "b", and pack the signed 32-bit results in "dst".

Operation

dst[31:0] := a[31:0] - a[63:32]
dst[63:32] := a[95:64] - a[127:96]
dst[95:64] := b[31:0] - b[63:32]
dst[127:96] := b[95:64] - b[127:96]
dst[159:128] := a[159:128] - a[191:160]
dst[191:160] := a[223:192] - a[255:224]
dst[223:192] := b[159:128] - b[191:160]
dst[255:224] := b[223:192] - b[255:224]
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 3 | 8
Haswell | 3 | 2 | 3
Broadwell | 3 | 2 | 3
Skylake | 3 | 2 | 3
Knights Landing | 11 | 8 | 3


_mm256_hsub_pd

__m256d _mm256_hsub_pd( __m256d a, __m256d b )

Synopsis

#include "immintrin.h"
Instruction: vhsubpd
CPUID Flag: AVX
Category: Arithmetic

Description

Horizontally subtract adjacent pairs of double-precision (64-bit) floating-point elements in "a" and "b", and pack the results in "dst".

Operation

dst[63:0] := a[63:0] - a[127:64]
dst[127:64] := b[63:0] - b[127:64]
dst[191:128] := a[191:128] - a[255:192]
dst[255:192] := b[191:128] - b[255:192]
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 7 | 3 | 8
Jaguar | 4 | 2 | 2
Sandy Bridge | 5 | 2 | 3
Ivy Bridge | 5 | 2 | 3
Haswell | 5 | 2 | 3
Broadwell | 5 | 2 | 3
Skylake | 6 | 2 | 3
Knights Landing | 15 | 8 | 3


_mm256_hsub_ps

__m256 _mm256_hsub_ps( __m256 a, __m256 b )

Synopsis

#include "immintrin.h"
Instruction: vhsubps
CPUID Flag: AVX
Category: Arithmetic

Description

Horizontally add adjacent pairs of single-precision (32-bit) floating-point elements in "a" and "b", and pack the results in "dst".

Operation

dst[31:0] := a[31:0] - a[63:32]
dst[63:32] := a[95:64] - a[127:96]
dst[95:64] := b[31:0] - b[63:32]
dst[127:96] := b[95:64] - b[127:96]
dst[159:128] := a[159:128] - a[191:160]
dst[191:160] := a[223:192] - a[255:224]
dst[223:192] := b[159:128] - b[191:160]
dst[255:224] := b[223:192] - b[255:224]
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 7 | 3 | 8
Jaguar | 4 | 2 | 2
Sandy Bridge | 5 | 2 | 3
Ivy Bridge | 5 | 2 | 3
Haswell | 5 | 2 | 3
Broadwell | 5 | 2 | 3
Skylake | 6 | 2 | 3
Knights Landing | 15 | 8 | 3


_mm256_hsubs_epi16

__m256i _mm256_hsubs_epi16( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: vphsubsw
CPUID Flag: AVX2
Category: Arithmetic

Description

Horizontally subtract adjacent pairs of 16-bit integers in "a" and "b" using saturation, and pack the signed 16-bit results in "dst".

Operation

dst[15:0] := Saturate_To_Int16(a[15:0] - a[31:16])
dst[31:16] := Saturate_To_Int16(a[47:32] - a[63:48])
dst[47:32] := Saturate_To_Int16(a[79:64] - a[95:80])
dst[63:48] := Saturate_To_Int16(a[111:96] - a[127:112])
dst[79:64] := Saturate_To_Int16(b[15:0] - b[31:16])
dst[95:80] := Saturate_To_Int16(b[47:32] - b[63:48])
dst[111:96] := Saturate_To_Int16(b[79:64] - b[95:80])
dst[127:112] := Saturate_To_Int16(b[111:96] - b[127:112])
dst[143:128] := Saturate_To_Int16(a[143:128] - a[159:144])
dst[159:144] := Saturate_To_Int16(a[175:160] - a[191:176])
dst[175:160] := Saturate_To_Int16(a[207:192] - a[223:208])
dst[191:176] := Saturate_To_Int16(a[239:224] - a[255:240])
dst[207:192] := Saturate_To_Int16(b[143:128] - b[159:144])
dst[223:208] := Saturate_To_Int16(b[175:160] - b[191:176])
dst[239:224] := Saturate_To_Int16(b[207:192] - b[223:208])
dst[255:240] := Saturate_To_Int16(b[239:224] - b[255:240])
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 3 | 8
Haswell | 3 | 2 | 3
Broadwell | 3 | 2 | 3
Skylake | 3 | 2 | 3


_mm256_hypot_pd

__m256d _mm256_hypot_pd( __m256d a, __m256d b )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Trigonometry

Description

Compute the length of the hypotenous of a right triangle, with the lengths of the other two sides of the triangle stored as packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*64
    dst[i+63:i] := SQRT(a[i+63:i]^2 + b[i+63:i]^2)
ENDFOR
dst[MAX:256] := 0


_mm256_hypot_ps

__m256 _mm256_hypot_ps( __m256 a, __m256 b )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Trigonometry

Description

Compute the length of the hypotenous of a right triangle, with the lengths of the other two sides of the triangle stored as packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*32
    dst[i+31:i] := SQRT(a[i+31:i]^2 + b[i+31:i]^2)
ENDFOR
dst[MAX:256] := 0


_mm256_i32gather_epi32

__m256i _mm256_i32gather_epi32( int const* base_addr, __m256i vindex, const int scale )

Synopsis

#include "immintrin.h"
Instruction: vpgatherdd
CPUID Flag: AVX2
Category: Load

Description

Gather 32-bit integers from memory using 32-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.

Operation

FOR j := 0 to 7
    i := j*32
    dst[i+31:i] := MEM[base_addr + SignExtend(vindex[i+31:i])*scale]
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen |  | 13 | 38
Haswell |  | 9 | 20
Broadwell |  | 6 | 10
Skylake |  | 4 | 4
Knights Landing |  | 12 | 6
Haswell | ~20 | ~10 |
Broadwell | ~19 | ~6 |
Skylake | ~22 | ~5 |


_mm256_i32gather_epi64

__m256i _mm256_i32gather_epi64( __int64 const* base_addr, __m128i vindex, const int scale )

Synopsis

#include "immintrin.h"
Instruction: vpgatherdq
CPUID Flag: AVX2
Category: Load

Description

Gather 64-bit integers from memory using 32-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.

Operation

FOR j := 0 to 3
    i := j*64
    m := j*32
    dst[i+63:i] := MEM[base_addr + SignExtend(vindex[m+31:m])*scale]
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen |  | 9 | 23
Haswell |  | 7 | 12
Broadwell |  | 5 | 7
Skylake |  | 2 | 5
Knights Landing |  | 12 | 6


_mm256_i32gather_pd

__m256d _mm256_i32gather_pd( double const* base_addr, __m128i vindex, const int scale )

Synopsis

#include "immintrin.h"
Instruction: vgatherdpd
CPUID Flag: AVX2
Category: Load

Description

Gather double-precision (64-bit) floating-point elements from memory using 32-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.

Operation

FOR j := 0 to 3
    i := j*64
    m := j*32
    dst[i+63:i] := MEM[base_addr + SignExtend(vindex[m+31:m])*scale]
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen |  | 9 | 23
Haswell |  | 7 | 12
Broadwell |  | 5 | 7
Skylake |  | 2 | 5


_mm256_i32gather_ps

__m256 _mm256_i32gather_ps( float const* base_addr, __m256i vindex, const int scale )

Synopsis

#include "immintrin.h"
Instruction: vgatherdps
CPUID Flag: AVX2
Category: Load

Description

Gather single-precision (32-bit) floating-point elements from memory using 32-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.

Operation

FOR j := 0 to 7
    i := j*32
    dst[i+31:i] := MEM[base_addr + SignExtend(vindex[i+31:i])*scale]
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen |  | 13 | 38
Haswell |  | 9 | 20
Broadwell |  | 6 | 10
Skylake | 13 | 5 | 4


_mm256_i64gather_epi32

__m128i _mm256_i64gather_epi32( int const* base_addr, __m256i vindex, const int scale )

Synopsis

#include "immintrin.h"
Instruction: vpgatherqd
CPUID Flag: AVX2
Category: Load

Description

Gather 32-bit integers from memory using 64-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.

Operation

FOR j := 0 to 3
    i := j*32
    m := j*64
    dst[i+31:i] := MEM[base_addr + SignExtend(vindex[m+63:m])*scale]
ENDFOR
dst[MAX:128] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen |  | 9 | 24
Haswell |  | 8 | 15
Broadwell |  | 6 | 9
Skylake |  | 2 | 5
Knights Landing |  | 12 | 6


_mm256_i64gather_epi64

__m256i _mm256_i64gather_epi64( __int64 const* base_addr, __m256i vindex, const int scale )

Synopsis

#include "immintrin.h"
Instruction: vpgatherqq
CPUID Flag: AVX2
Category: Load

Description

Gather 64-bit integers from memory using 64-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.

Operation

FOR j := 0 to 3
    i := j*64
    m := j*64
    dst[i+63:i] := MEM[base_addr + SignExtend(vindex[m+63:m])*scale]
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen |  | 9 | 23
Haswell |  | 7 | 14
Broadwell |  | 5 | 7
Skylake |  | 2 | 5
Knights Landing |  | 12 | 6
Haswell | ~15 | ~7 |
Broadwell | ~16 | ~5 |
Skylake | ~20 | ~4 |


_mm256_i64gather_pd

__m256d _mm256_i64gather_pd( double const* base_addr, __m256i vindex, const int scale )

Synopsis

#include "immintrin.h"
Instruction: vgatherqpd
CPUID Flag: AVX2
Category: Load

Description

Gather double-precision (64-bit) floating-point elements from memory using 64-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.

Operation

FOR j := 0 to 3
    i := j*64
    m := j*64
    dst[i+63:i] := MEM[base_addr + SignExtend(vindex[m+63:m])*scale]
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen |  | 9 | 23
Haswell |  | 7 | 14
Broadwell |  | 5 | 7
Skylake |  | 2 | 5


_mm256_i64gather_ps

__m128 _mm256_i64gather_ps( float const* base_addr, __m256i vindex, const int scale )

Synopsis

#include "immintrin.h"
Instruction: vgatherqps
CPUID Flag: AVX2
Category: Load

Description

Gather single-precision (32-bit) floating-point elements from memory using 64-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.

Operation

FOR j := 0 to 3
    i := j*32
    m := j*64
    dst[i+31:i] := MEM[base_addr + SignExtend(vindex[m+63:m])*scale]
ENDFOR
dst[MAX:128] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen |  | 9 | 24
Haswell |  | 8 | 15
Broadwell |  | 6 | 9
Skylake |  | 2 | 5


_mm256_idiv_epi32

__m256i _mm256_idiv_epi32( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Arithmetic

Description

Divide packed 32-bit integers in "a" by packed elements in "b", and store the truncated results in "dst".

Operation

FOR j := 0 to 7
    i := 32*j
    dst[i+31:i] := TRUNCATE(a[i+31:i] / b[i+31:i])
ENDFOR
dst[MAX:256] := 0


_mm256_idivrem_epi32

__m256i _mm256_idivrem_epi32( __m256i * mem_addr, __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Arithmetic

Description

Divide packed 32-bit integers in "a" by packed elements in "b", store the truncated results in "dst", and store the remainders as packed 32-bit integers into memory at "mem_addr".

Operation

FOR j := 0 to 7
    i := 32*j
    dst[i+31:i] := TRUNCATE(a[i+31:i] / b[i+31:i])
    MEM[mem_addr+i+31:mem_addr+i] := REMAINDER(a[i+31:i] / b[i+31:i])
ENDFOR
dst[MAX:256] := 0


_mm256_insert_epi16

__m256i _mm256_insert_epi16( __m256i a, __int16 i, const int index )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Swizzle

Description

Copy "a" to "dst", and insert the 16-bit integer "i" into "dst" at the location specified by "index".

Operation

dst[255:0] := a[255:0]
sel := index*16
dst[sel+15:sel] := i[15:0]


_mm256_insert_epi32

__m256i _mm256_insert_epi32( __m256i a, __int32 i, const int index )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Swizzle

Description

Copy "a" to "dst", and insert the 32-bit integer "i" into "dst" at the location specified by "index".

Operation

dst[255:0] := a[255:0]
sel := index*32
dst[sel+31:sel] := i[31:0]


_mm256_insert_epi64

__m256i _mm256_insert_epi64( __m256i a, __int64 i, const int index )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Swizzle

Description

Copy "a" to "dst", and insert the 64-bit integer "i" into "dst" at the location specified by "index".

Operation

dst[255:0] := a[255:0]
sel := index*64
dst[sel+63:sel] := i[63:0]


_mm256_insert_epi8

__m256i _mm256_insert_epi8( __m256i a, __int8 i, const int index )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Swizzle

Description

Copy "a" to "dst", and insert the 8-bit integer "i" into "dst" at the location specified by "index".

Operation

dst[255:0] := a[255:0]
sel := index*8
dst[sel+7:sel] := i[7:0]


_mm256_insertf128_pd

__m256d _mm256_insertf128_pd( __m256d a, __m128d b, int imm8 )

Synopsis

#include "immintrin.h"
Instruction: vinsertf128
CPUID Flag: AVX
Category: Swizzle

Description

Copy "a" to "dst", then insert 128 bits (composed of 2 packed double-precision (64-bit) floating-point elements) from "b" into "dst" at the location specified by "imm8".

Operation

dst[255:0] := a[255:0]
CASE imm8[7:0] OF
0: dst[127:0] := b[127:0]
1: dst[255:128] := b[127:0]
ESAC
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 2
Jaguar | 1 | 1 | 2
Sandy Bridge | 2 | 1 | 1
Ivy Bridge | 2 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 3 | 1 | 1
Knights Landing | 3-6 | 1 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 3 | 1 |


_mm256_insertf128_ps

__m256 _mm256_insertf128_ps( __m256 a, __m128 b, int imm8 )

Synopsis

#include "immintrin.h"
Instruction: vinsertf128
CPUID Flag: AVX
Category: Swizzle

Description

Copy "a" to "dst", then insert 128 bits (composed of 4 packed single-precision (32-bit) floating-point elements) from "b" into "dst" at the location specified by "imm8".

Operation

dst[255:0] := a[255:0]
CASE (imm8[1:0]) OF
0: dst[127:0] := b[127:0]
1: dst[255:128] := b[127:0]
ESAC
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 2
Jaguar | 1 | 1 | 2
Sandy Bridge | 2 | 1 | 1
Ivy Bridge | 2 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 3 | 1 | 1
Knights Landing | 3-6 | 1 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 3 | 1 |


_mm256_insertf128_si256

__m256i _mm256_insertf128_si256( __m256i a, __m128i b, int imm8 )

Synopsis

#include "immintrin.h"
Instruction: vinsertf128
CPUID Flag: AVX
Category: Swizzle

Description

Copy "a" to "dst", then insert 128 bits from "b" into "dst" at the location specified by "imm8".

Operation

dst[255:0] := a[255:0]
CASE (imm8[1:0]) OF
0: dst[127:0] := b[127:0]
1: dst[255:128] := b[127:0]
ESAC
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 2
Jaguar | 1 | 1 | 2
Sandy Bridge | 2 | 1 | 1
Ivy Bridge | 2 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 3 | 1 | 1
Knights Landing | 3-6 | 1 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 3 | 1 |


_mm256_inserti128_si256

__m256i _mm256_inserti128_si256( __m256i a, __m128i b, const int imm8 )

Synopsis

#include "immintrin.h"
Instruction: vinserti128
CPUID Flag: AVX2
Category: Swizzle

Description

Copy "a" to "dst", then insert 128 bits (composed of integer data) from "b" into "dst" at the location specified by "imm8".

Operation

dst[255:0] := a[255:0]
CASE (imm8[1:0]) OF
0: dst[127:0] := b[127:0]
1: dst[255:128] := b[127:0]
ESAC
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | .67 | 2
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 3 | 1 | 1
Knights Landing | 3-6 | 1 | 1
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 3 | 1 |


_mm256_invcbrt_pd

__m256d _mm256_invcbrt_pd( __m256d a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Elementary Math Functions

Description

Compute the inverse cube root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*64
    dst[i+63:i] := InvCubeRoot(a[i+63:i])
ENDFOR
dst[MAX:256] := 0


_mm256_invcbrt_ps

__m256 _mm256_invcbrt_ps( __m256 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Elementary Math Functions

Description

Compute the inverse cube root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*32
    dst[i+31:i] := InvCubeRoot(a[i+31:i])
ENDFOR
dst[MAX:256] := 0


_mm256_invsqrt_pd

__m256d _mm256_invsqrt_pd( __m256d a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Elementary Math Functions

Description

Compute the inverse square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*64
    dst[i+63:i] := InvSQRT(a[i+63:i])
ENDFOR
dst[MAX:256] := 0


_mm256_invsqrt_ps

__m256 _mm256_invsqrt_ps( __m256 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Elementary Math Functions

Description

Compute the inverse square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*32
    dst[i+31:i] := InvSQRT(a[i+31:i])
ENDFOR
dst[MAX:256] := 0


_mm256_irem_epi32

__m256i _mm256_irem_epi32( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Arithmetic

Description

Divide packed 32-bit integers in "a" by packed elements in "b", and store the remainders as packed 32-bit integers in "dst".

Operation

FOR j := 0 to 7
    i := 32*j
    dst[i+31:i] := REMAINDER(a[i+31:i] / b[i+31:i])
ENDFOR
dst[MAX:256] := 0


_mm256_lddqu_si256

__m256i _mm256_lddqu_si256( __m256i const * mem_addr )

Synopsis

#include "immintrin.h"
Instruction: vlddqu
CPUID Flag: AVX
Category: Load

Description

Load 256-bits of integer data from unaligned memory into "dst". This intrinsic may perform better than "_mm256_loadu_si256" when the data crosses a cache line boundary.

Operation

dst[255:0] := MEM[mem_addr+255:mem_addr]
dst[MAX:256] := 0


_mm256_load_pd

__m256d _mm256_load_pd( double const * mem_addr )

Synopsis

#include "immintrin.h"
Instruction: vmovapd
CPUID Flag: AVX
Category: Load

Description

Load 256-bits (composed of 4 packed double-precision (64-bit) floating-point elements) from memory into "dst". "mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.

Operation

dst[255:0] := MEM[mem_addr+255:mem_addr]
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 2
Jaguar | 1 | 1 | 2
Sandy Bridge | 1 | 1 | 1
Ivy Bridge | 0-1 | ≤1 | 1
Haswell | 0-1 | 1 | 1
Broadwell | 0-1 | 1 | 1
Skylake | 0-1 | 0.25 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 1 | 1 |
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.25 |


_mm256_load_ps

__m256 _mm256_load_ps( float const * mem_addr )

Synopsis

#include "immintrin.h"
Instruction: vmovaps
CPUID Flag: AVX
Category: Load

Description

Load 256-bits (composed of 8 packed single-precision (32-bit) floating-point elements) from memory into "dst". "mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.

Operation

dst[255:0] := MEM[mem_addr+255:mem_addr]
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 2
Jaguar | 1 | 1 | 2
Sandy Bridge | 1 | 1 | 1
Ivy Bridge | 0-1 | ≤1 | 1
Haswell | 0-1 | 1 | 1
Broadwell | 0-1 | 1 | 1
Skylake | 0-1 | 0.25 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 1 | 1 |
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.25 |


_mm256_load_si256

__m256i _mm256_load_si256( __m256i const * mem_addr )

Synopsis

#include "immintrin.h"
Instruction: vmovdqa
CPUID Flag: AVX
Category: Load

Description

Load 256-bits of integer data from memory into "dst". "mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.

Operation

dst[255:0] := MEM[mem_addr+255:mem_addr]
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 2
Jaguar | 1 | 1 | 2
Haswell | 0-1 | 0.33 | 1
Broadwell | 0-1 | 0.25 | 1
Skylake | 0-1 | 0.25 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 0.25 |
Broadwell | 1 | 0.25 |
Skylake | 1 | 0.25 |


_mm256_loadu_pd

__m256d _mm256_loadu_pd( double const * mem_addr )

Synopsis

#include "immintrin.h"
Instruction: vmovupd
CPUID Flag: AVX
Category: Load

Description

Load 256-bits (composed of 4 packed double-precision (64-bit) floating-point elements) from memory into "dst". "mem_addr" does not need to be aligned on any particular boundary.

Operation

dst[255:0] := MEM[mem_addr+255:mem_addr]
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 5 | 1 | 2
Jaguar | 1 | 1 | 2
Sandy Bridge | 4 | 1 | 1
Ivy Bridge | 4 | 1 | 1
Haswell | 3 | 0.5 | 1
Broadwell | 3 | 0.5 | 1
Skylake | 3 | 0.5 | 1
Knights Landing | 5 | 0.5 | 1
Ivy Bridge | 1 | 1 |
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.25 |


_mm256_loadu_ps

__m256 _mm256_loadu_ps( float const * mem_addr )

Synopsis

#include "immintrin.h"
Instruction: vmovups
CPUID Flag: AVX
Category: Load

Description

Load 256-bits (composed of 8 packed single-precision (32-bit) floating-point elements) from memory into "dst". "mem_addr" does not need to be aligned on any particular boundary.

Operation

dst[255:0] := MEM[mem_addr+255:mem_addr]
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 5 | 1 | 2
Jaguar | 1 | 1 | 2
Sandy Bridge | 4 | 1 | 1
Ivy Bridge | 4 | 1 | 1
Haswell | 3 | 0.5 | 1
Broadwell | 3 | 0.5 | 1
Skylake | 3 | 0.5 | 1
Knights Landing | 5 | 0.5 | 1
Ivy Bridge | 1 | 1 |
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.25 |


_mm256_loadu_si256

__m256i _mm256_loadu_si256( __m256i const * mem_addr )

Synopsis

#include "immintrin.h"
Instruction: vmovdqu
CPUID Flag: AVX
Category: Load

Description

Load 256-bits of integer data from memory into "dst". "mem_addr" does not need to be aligned on any particular boundary.

Operation

dst[255:0] := MEM[mem_addr+255:mem_addr]
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 1 | 2
Haswell | 0-1 | 0.33 | 1
Broadwell | 0-1 | 0.25 | 1
Skylake | 0-1 | 0.25 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 0.25 |
Broadwell | 1 | 0.25 |
Skylake | 1 | 0.25 |


_mm256_loadu2_m128

__m256 _mm256_loadu2_m128( float const* hiaddr, float const* loaddr )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Load

Description

Load two 128-bit values (composed of 4 packed single-precision (32-bit) floating-point elements) from memory, and combine them into a 256-bit value in "dst". "hiaddr" and "loaddr" do not need to be aligned on any particular boundary.

Operation

dst[127:0] := MEM[loaddr+127:loaddr]
dst[255:128] := MEM[hiaddr+127:hiaddr]
dst[MAX:256] := 0


_mm256_loadu2_m128d

__m256d _mm256_loadu2_m128d( double const* hiaddr, double const* loaddr )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Load

Description

Load two 128-bit values (composed of 2 packed double-precision (64-bit) floating-point elements) from memory, and combine them into a 256-bit value in "dst". "hiaddr" and "loaddr" do not need to be aligned on any particular boundary.

Operation

dst[127:0] := MEM[loaddr+127:loaddr]
dst[255:128] := MEM[hiaddr+127:hiaddr]
dst[MAX:256] := 0


_mm256_loadu2_m128i

__m256i _mm256_loadu2_m128i( __m128i const* hiaddr, __m128i const* loaddr )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Load

Description

Load two 128-bit values (composed of integer data) from memory, and combine them into a 256-bit value in "dst". "hiaddr" and "loaddr" do not need to be aligned on any particular boundary.

Operation

dst[127:0] := MEM[loaddr+127:loaddr]
dst[255:128] := MEM[hiaddr+127:hiaddr]
dst[MAX:256] := 0


_mm256_log_pd

__m256d _mm256_log_pd( __m256d a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Elementary Math Functions

Description

Compute the natural logarithm of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*64
    dst[i+63:i] := ln(a[i+63:i])
ENDFOR
dst[MAX:256] := 0


_mm256_log_ps

__m256 _mm256_log_ps( __m256 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Elementary Math Functions

Description

Compute the natural logarithm of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*32
    dst[i+31:i] := ln(a[i+31:i])
ENDFOR
dst[MAX:256] := 0


_mm256_log10_pd

__m256d _mm256_log10_pd( __m256d a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Elementary Math Functions

Description

Compute the base-10 logarithm of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*64
    dst[i+63:i] := log10(a[i+63:i])
ENDFOR
dst[MAX:256] := 0


_mm256_log10_ps

__m256 _mm256_log10_ps( __m256 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Elementary Math Functions

Description

Compute the base-10 logarithm of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*32
    dst[i+31:i] := log10(a[i+31:i])
ENDFOR
dst[MAX:256] := 0


_mm256_log1p_pd

__m256d _mm256_log1p_pd( __m256d a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Elementary Math Functions

Description

Compute the natural logarithm of one plus packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*64
    dst[i+63:i] := ln(1.0 + a[i+63:i])
ENDFOR
dst[MAX:256] := 0


_mm256_log1p_ps

__m256 _mm256_log1p_ps( __m256 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Elementary Math Functions

Description

Compute the natural logarithm of one plus packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*32
    dst[i+31:i] := ln(1.0 + a[i+31:i])
ENDFOR
dst[MAX:256] := 0


_mm256_log2_pd

__m256d _mm256_log2_pd( __m256d a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Elementary Math Functions

Description

Compute the base-2 logarithm of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*64
    dst[i+63:i] := log2(a[i+63:i])
ENDFOR
dst[MAX:256] := 0


_mm256_log2_ps

__m256 _mm256_log2_ps( __m256 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Elementary Math Functions

Description

Compute the base-2 logarithm of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*32
    dst[i+31:i] := log2(a[i+31:i])
ENDFOR
dst[MAX:256] := 0


_mm256_logb_pd

__m256d _mm256_logb_pd( __m256d a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Elementary Math Functions

Description

Convert the exponent of each packed double-precision (64-bit) floating-point element in "a" to a double-precision floating-point number representing the integer exponent, and store the results in "dst". This intrinsic essentially calculates "floor(log2(x))" for each element.

Operation

FOR j := 0 to 3
    i := j*64
    dst[i+63:i] := ConvertExpFP64(a[i+63:i])
ENDFOR
dst[MAX:256] := 0


_mm256_logb_ps

__m256 _mm256_logb_ps( __m256 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Elementary Math Functions

Description

Convert the exponent of each packed single-precision (32-bit) floating-point element in "a" to a single-precision floating-point number representing the integer exponent, and store the results in "dst". This intrinsic essentially calculates "floor(log2(x))" for each element.

Operation

FOR j := 0 to 7
    i := j*32
    dst[i+31:i] := ConvertExpFP32(a[i+31:i])
ENDFOR
dst[MAX:256] := 0


_mm256_madd_epi16

__m256i _mm256_madd_epi16( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: vpmaddwd
CPUID Flag: AVX2
Category: Arithmetic

Description

Multiply packed signed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers. Horizontally add adjacent pairs of intermediate 32-bit integers, and pack the results in "dst".

Operation

FOR j := 0 to 7
    i := j*32
    dst[i+31:i] := a[i+31:i+16]*b[i+31:i+16] + a[i+15:i]*b[i+15:i]
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 2 | 2
Haswell | 5 | 1 | 1
Broadwell | 5 | 1 | 1
Skylake | 5 | 0.5 | 1
Haswell | 5 | 1 |
Broadwell | 5 | 1 |
Skylake | 5 | 0.5 |


_mm256_maddubs_epi16

__m256i _mm256_maddubs_epi16( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: vpmaddubsw
CPUID Flag: AVX2
Category: Arithmetic

Description

Vertically multiply each unsigned 8-bit integer from "a" with the corresponding signed 8-bit integer from "b", producing intermediate signed 16-bit integers. Horizontally add adjacent pairs of intermediate signed 16-bit integers, and pack the saturated results in "dst".

Operation

FOR j := 0 to 15
    i := j*16
    dst[i+15:i] := Saturate_To_Int16( a[i+15:i+8]*b[i+15:i+8] + a[i+7:i]*b[i+7:i] )
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 4 | 2 | 2
Haswell | 5 | 1 | 1
Broadwell | 5 | 1 | 1
Skylake | 5 | 0.5 | 1
Knights Landing | 16 | 9 | 5
Haswell | 5 | 1 |
Broadwell | 5 | 1 |
Skylake | 5 | 0.5 |


_mm256_mask_i32gather_epi32

__m256i _mm256_mask_i32gather_epi32( __m256i src, int const* base_addr, __m256i vindex, __m256i mask, const int scale )

Synopsis

#include "immintrin.h"
Instruction: vpgatherdd
CPUID Flag: AVX2
Category: Load

Description

Gather 32-bit integers from memory using 32-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8.

Operation

FOR j := 0 to 7
    i := j*32
    IF mask[i+31]
        dst[i+31:i] := MEM[base_addr + SignExtend(vindex[i+31:i])*scale]
        mask[i+31] := 0
    ELSE
        dst[i+31:i] := src[i+31:i]
    FI
ENDFOR
mask[MAX:256] := 0
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen |  | 13 | 38
Haswell |  | 9 | 20
Broadwell |  | 6 | 10
Skylake |  | 4 | 4
Knights Landing |  | 12 | 6
Haswell | ~20 | ~10 |
Broadwell | ~19 | ~6 |
Skylake | ~22 | ~5 |


_mm256_mask_i32gather_epi64

__m256i _mm256_mask_i32gather_epi64( __m256i src, __int64 const* base_addr, __m128i vindex, __m256i mask, const int scale )

Synopsis

#include "immintrin.h"
Instruction: vpgatherdq
CPUID Flag: AVX2
Category: Load

Description

Gather 64-bit integers from memory using 32-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8.

Operation

FOR j := 0 to 3
    i := j*64
    m := j*32
    IF mask[i+63]
        dst[i+63:i] := MEM[base_addr + SignExtend(vindex[m+31:m])*scale]
        mask[i+63] := 0
    ELSE
        dst[i+63:i] := src[i+63:i]
    FI
ENDFOR
mask[MAX:256] := 0
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen |  | 9 | 23
Haswell |  | 7 | 12
Broadwell |  | 5 | 7
Skylake |  | 2 | 5
Knights Landing |  | 12 | 6


_mm256_mask_i32gather_pd

__m256d _mm256_mask_i32gather_pd( __m256d src, double const* base_addr, __m128i vindex, __m256d mask, const int scale )

Synopsis

#include "immintrin.h"
Instruction: vgatherdpd
CPUID Flag: AVX2
Category: Load

Description

Gather double-precision (64-bit) floating-point elements from memory using 32-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8.

Operation

FOR j := 0 to 3
    i := j*64
    m := j*32
    IF mask[i+63]
        dst[i+63:i] := MEM[base_addr + SignExtend(vindex[m+31:m])*scale]
        mask[i+63] := 0
    ELSE
        dst[i+63:i] := src[i+63:i]
    FI
ENDFOR
mask[MAX:256] := 0
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen |  | 9 | 23
Haswell |  | 7 | 12
Broadwell |  | 5 | 7
Skylake |  | 2 | 5


_mm256_mask_i32gather_ps

__m256 _mm256_mask_i32gather_ps( __m256 src, float const* base_addr, __m256i vindex, __m256 mask, const int scale )

Synopsis

#include "immintrin.h"
Instruction: vgatherdps
CPUID Flag: AVX2
Category: Load

Description

Gather single-precision (32-bit) floating-point elements from memory using 32-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8.

Operation

FOR j := 0 to 7
    i := j*32
    IF mask[i+31]
        dst[i+31:i] := MEM[base_addr + SignExtend(vindex[i+31:i])*scale]
        mask[i+31] := 0
    ELSE
        dst[i+31:i] := src[i+31:i]
    FI
ENDFOR
mask[MAX:256] := 0
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen |  | 13 | 38
Haswell |  | 9 | 20
Broadwell |  | 6 | 10
Skylake | 13 | 5 | 4


_mm256_mask_i64gather_epi32

__m128i _mm256_mask_i64gather_epi32( __m128i src, int const* base_addr, __m256i vindex, __m128i mask, const int scale )

Synopsis

#include "immintrin.h"
Instruction: vpgatherqd
CPUID Flag: AVX2
Category: Load

Description

Gather 32-bit integers from memory using 64-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8.

Operation

FOR j := 0 to 3
    i := j*32
    m := j*64
    IF mask[i+31]
        dst[i+31:i] := MEM[base_addr + SignExtend(vindex[m+63:m])*scale]
        mask[i+31] := 0
    ELSE
        dst[i+31:i] := src[i+31:i]
    FI
ENDFOR
mask[MAX:128] := 0
dst[MAX:128] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen |  | 9 | 24
Haswell |  | 8 | 15
Broadwell |  | 6 | 9
Skylake |  | 2 | 5
Knights Landing |  | 12 | 6


_mm256_mask_i64gather_epi64

__m256i _mm256_mask_i64gather_epi64( __m256i src, __int64 const* base_addr, __m256i vindex, __m256i mask, const int scale )

Synopsis

#include "immintrin.h"
Instruction: vpgatherqq
CPUID Flag: AVX2
Category: Load

Description

Gather 64-bit integers from memory using 64-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8.

Operation

FOR j := 0 to 3
    i := j*64
    m := j*64
    IF mask[i+63]
        dst[i+63:i] := MEM[base_addr + SignExtend(vindex[m+63:m])*scale]
        mask[i+63] := 0
    ELSE
        dst[i+63:i] := src[i+63:i]
    FI
ENDFOR
mask[MAX:256] := 0
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen |  | 9 | 23
Haswell |  | 7 | 14
Broadwell |  | 5 | 7
Skylake |  | 2 | 5
Knights Landing |  | 12 | 6
Haswell | ~15 | ~7 |
Broadwell | ~16 | ~5 |
Skylake | ~20 | ~4 |


_mm256_mask_i64gather_pd

__m256d _mm256_mask_i64gather_pd( __m256d src, double const* base_addr, __m256i vindex, __m256d mask, const int scale )

Synopsis

#include "immintrin.h"
Instruction: vgatherqpd
CPUID Flag: AVX2
Category: Load

Description

Gather double-precision (64-bit) floating-point elements from memory using 64-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8.

Operation

FOR j := 0 to 3
    i := j*64
    m := j*64
    IF mask[i+63]
        dst[i+63:i] := MEM[base_addr + SignExtend(vindex[m+63:m])*scale]
        mask[i+63] := 0
    ELSE
        dst[i+63:i] := src[i+63:i]
    FI
ENDFOR
mask[MAX:256] := 0
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen |  | 9 | 23
Haswell |  | 7 | 14
Broadwell |  | 5 | 7
Skylake |  | 2 | 5


_mm256_mask_i64gather_ps

__m128 _mm256_mask_i64gather_ps( __m128 src, float const* base_addr, __m256i vindex, __m128 mask, const int scale )

Synopsis

#include "immintrin.h"
Instruction: vgatherqps
CPUID Flag: AVX2
Category: Load

Description

Gather single-precision (32-bit) floating-point elements from memory using 64-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8.

Operation

FOR j := 0 to 3
    i := j*32
    m := j*64
    IF mask[i+31]
        dst[i+31:i] := MEM[base_addr + SignExtend(vindex[m+63:m])*scale]
        mask[i+31] := 0
    ELSE
        dst[i+31:i] := src[i+31:i]
    FI
ENDFOR
mask[MAX:128] := 0
dst[MAX:128] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen |  | 9 | 24
Haswell |  | 8 | 15
Broadwell |  | 6 | 9
Skylake |  | 2 | 5


_mm256_maskload_epi32

__m256i _mm256_maskload_epi32( int const* mem_addr, __m256i mask )

Synopsis

#include "immintrin.h"
Instruction: vpmaskmovd
CPUID Flag: AVX2
Category: Load

Description

Load packed 32-bit integers from memory into "dst" using "mask" (elements are zeroed out when the highest bit is not set in the corresponding element).

Operation

FOR j := 0 to 7
    i := j*32
    IF mask[i+31]
        dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i]
    ELSE
        dst[i+31:i] := 0
    FI
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Haswell | 13-14 | 1 | 4
Broadwell | 15 | 1 | 4
Skylake | 14 | 1 | 3
Knights Landing | 7 | 9 | 5
Haswell | 8 | 2 |
Broadwell | 8 | 2 |
Skylake | 11 | 1 |


_mm256_maskload_epi64

__m256i _mm256_maskload_epi64( __int64 const* mem_addr, __m256i mask )

Synopsis

#include "immintrin.h"
Instruction: vpmaskmovq
CPUID Flag: AVX2
Category: Load

Description

Load packed 64-bit integers from memory into "dst" using "mask" (elements are zeroed out when the highest bit is not set in the corresponding element).

Operation

FOR j := 0 to 3
    i := j*64
    IF mask[i+63]
        dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i]
    ELSE
        dst[i+63:i] := 0
    FI
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Haswell | 13-14 | 1 | 4
Broadwell | 15 | 1 | 4
Skylake | 14 | 1 | 3
Knights Landing | 7 | 9 | 5
Haswell | 8 | 2 |
Broadwell | 8 | 2 |
Skylake | 11 | 1 |


_mm256_maskload_pd

__m256d _mm256_maskload_pd( double const * mem_addr, __m256i mask )

Synopsis

#include "immintrin.h"
Instruction: vmaskmovpd
CPUID Flag: AVX
Category: Load

Description

Load packed double-precision (64-bit) floating-point elements from memory into "dst" using "mask" (elements are zeroed out when the high bit of the corresponding element is not set).

Operation

FOR j := 0 to 3
    i := j*64
    IF mask[i+63]
        dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i]
    ELSE
        dst[i+63:i] := 0
    FI
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | ~50 | 5 | 19
Jaguar | 32 | 22 | 36
Sandy Bridge |  | 1 | 3
Ivy Bridge | 5 | 1 | 3
Haswell | 14 | 2 | 4
Broadwell | 16 | 1 | 4
Skylake | 13 | 1 | 4
Ivy Bridge |  | 2 |
Haswell |  | 2 |
Broadwell |  | 2 |
Skylake |  | 1 |


_mm256_maskload_ps

__m256 _mm256_maskload_ps( float const * mem_addr, __m256i mask )

Synopsis

#include "immintrin.h"
Instruction: vmaskmovps
CPUID Flag: AVX
Category: Load

Description

Load packed single-precision (32-bit) floating-point elements from memory into "dst" using "mask" (elements are zeroed out when the high bit of the corresponding element is not set).

Operation

FOR j := 0 to 7
    i := j*32
    IF mask[i+31]
        dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i]
    ELSE
        dst[i+31:i] := 0
    FI
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | ~50 | 5 | 19
Jaguar | 32 | 22 | 36
Sandy Bridge |  | 1 | 3
Ivy Bridge | 5 | 1 | 3
Haswell | 14 | 2 | 4
Broadwell | 16 | 1 | 4
Skylake | 13 | 1 | 4
Ivy Bridge | 8 | 2 |
Haswell | 8 | 2 |
Broadwell | 8 | 2 |
Skylake | 11 | 1 |


_mm256_maskstore_epi32

void _mm256_maskstore_epi32( int* mem_addr, __m256i mask, __m256i a )

Synopsis

#include "immintrin.h"
Instruction: vpmaskmovd
CPUID Flag: AVX2
Category: Store

Description

Store packed 32-bit integers from "a" into memory using "mask" (elements are not stored when the highest bit is not set in the corresponding element).

Operation

FOR j := 0 to 7
    i := j*32
    IF mask[i+31]
        MEM[mem_addr+i+31:mem_addr+i] := a[i+31:i]
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Haswell | 13-14 | 1 | 4
Broadwell | 15 | 1 | 4
Skylake | 14 | 1 | 3
Knights Landing | 7 | 9 | 5
Haswell |  | 2 |
Broadwell |  | 2 |
Skylake |  | 1 |


_mm256_maskstore_epi64

void _mm256_maskstore_epi64( __int64* mem_addr, __m256i mask, __m256i a )

Synopsis

#include "immintrin.h"
Instruction: vpmaskmovq
CPUID Flag: AVX2
Category: Store

Description

Store packed 64-bit integers from "a" into memory using "mask" (elements are not stored when the highest bit is not set in the corresponding element).

Operation

FOR j := 0 to 3
    i := j*64
    IF mask[i+63]
        MEM[mem_addr+i+63:mem_addr+i] := a[i+63:i]
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Haswell | 13-14 | 1 | 4
Broadwell | 15 | 1 | 4
Skylake | 14 | 1 | 3
Knights Landing | 7 | 9 | 5
Haswell |  | 2 |
Broadwell |  | 2 |
Skylake |  | 1 |


_mm256_maskstore_pd

void _mm256_maskstore_pd( double * mem_addr, __m256i mask, __m256d a )

Synopsis

#include "immintrin.h"
Instruction: vmaskmovpd
CPUID Flag: AVX
Category: Store

Description

Store packed double-precision (64-bit) floating-point elements from "a" into memory using "mask".

Operation

FOR j := 0 to 3
    i := j*64
    IF mask[i+63]
        MEM[mem_addr+i+63:mem_addr+i] := a[i+63:i]
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | ~50 | 5 | 19
Jaguar | 32 | 22 | 36
Sandy Bridge |  | 1 | 3
Ivy Bridge | 5 | 1 | 3
Haswell | 14 | 2 | 4
Broadwell | 16 | 1 | 4
Skylake | 13 | 1 | 4
Ivy Bridge |  | 2 |
Haswell |  | 2 |
Broadwell |  | 2 |
Skylake |  | 1 |


_mm256_maskstore_ps

void _mm256_maskstore_ps( float * mem_addr, __m256i mask, __m256 a )

Synopsis

#include "immintrin.h"
Instruction: vmaskmovps
CPUID Flag: AVX
Category: Store

Description

Store packed single-precision (32-bit) floating-point elements from "a" into memory using "mask".

Operation

FOR j := 0 to 7
    i := j*32
    IF mask[i+31]
        MEM[mem_addr+i+31:mem_addr+i] := a[i+31:i]
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | ~50 | 5 | 19
Jaguar | 32 | 22 | 36
Sandy Bridge |  | 1 | 3
Ivy Bridge | 5 | 1 | 3
Haswell | 14 | 2 | 4
Broadwell | 16 | 1 | 4
Skylake | 13 | 1 | 4
Ivy Bridge |  | 2 |
Haswell |  | 2 |
Broadwell |  | 2 |
Skylake |  | 1 |


_mm256_max_epi16

__m256i _mm256_max_epi16( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: vpmaxsw
CPUID Flag: AVX2
Category: Special Math Functions

Description

Compare packed 16-bit integers in "a" and "b", and store packed maximum values in "dst".

Operation

FOR j := 0 to 15
    i := j*16
    IF a[i+15:i] > b[i+15:i]
        dst[i+15:i] := a[i+15:i]
    ELSE
        dst[i+15:i] := b[i+15:i]
    FI
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.67 | 2
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1


_mm256_max_epi32

__m256i _mm256_max_epi32( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: vpmaxsd
CPUID Flag: AVX2
Category: Special Math Functions

Description

Compare packed 32-bit integers in "a" and "b", and store packed maximum values in "dst".

Operation

FOR j := 0 to 7
    i := j*32
    IF a[i+31:i] > b[i+31:i]
        dst[i+31:i] := a[i+31:i]
    ELSE
        dst[i+31:i] := b[i+31:i]
    FI
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.67 | 2
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.5 |


_mm256_max_epi8

__m256i _mm256_max_epi8( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: vpmaxsb
CPUID Flag: AVX2
Category: Special Math Functions

Description

Compare packed 8-bit integers in "a" and "b", and store packed maximum values in "dst".

Operation

FOR j := 0 to 31
    i := j*8
    IF a[i+7:i] > b[i+7:i]
        dst[i+7:i] := a[i+7:i]
    ELSE
        dst[i+7:i] := b[i+7:i]
    FI
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.67 | 2
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.5 | 1


_mm256_max_epu16

__m256i _mm256_max_epu16( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: vpmaxuw
CPUID Flag: AVX2
Category: Special Math Functions

Description

Compare packed unsigned 16-bit integers in "a" and "b", and store packed maximum values in "dst".

Operation

FOR j := 0 to 15
    i := j*16
    IF a[i+15:i] > b[i+15:i]
        dst[i+15:i] := a[i+15:i]
    ELSE
        dst[i+15:i] := b[i+15:i]
    FI
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.67 | 2
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.5 | 1


_mm256_max_epu32

__m256i _mm256_max_epu32( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: vpmaxud
CPUID Flag: AVX2
Category: Special Math Functions

Description

Compare packed unsigned 32-bit integers in "a" and "b", and store packed maximum values in "dst".

Operation

FOR j := 0 to 7
    i := j*32
    IF a[i+31:i] > b[i+31:i]
        dst[i+31:i] := a[i+31:i]
    ELSE
        dst[i+31:i] := b[i+31:i]
    FI
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.67 | 2
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.5 | 1
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.5 |


_mm256_max_epu8

__m256i _mm256_max_epu8( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: vpmaxub
CPUID Flag: AVX2
Category: Special Math Functions

Description

Compare packed unsigned 8-bit integers in "a" and "b", and store packed maximum values in "dst".

Operation

FOR j := 0 to 31
    i := j*8
    IF a[i+7:i] > b[i+7:i]
        dst[i+7:i] := a[i+7:i]
    ELSE
        dst[i+7:i] := b[i+7:i]
    FI
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.67 | 2
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1


_mm256_max_pd

__m256d _mm256_max_pd( __m256d a, __m256d b )

Synopsis

#include "immintrin.h"
Instruction: vmaxpd
CPUID Flag: AVX
Category: Special Math Functions

Description

Compare packed double-precision (64-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst".

Operation

FOR j := 0 to 3
    i := j*64
    dst[i+63:i] := MAX(a[i+63:i], b[i+63:i])
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 1 | 2
Jaguar | 2 | 2 | 2
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 4 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 4 | 0.5 |


_mm256_max_ps

__m256 _mm256_max_ps( __m256 a, __m256 b )

Synopsis

#include "immintrin.h"
Instruction: vmaxps
CPUID Flag: AVX
Category: Special Math Functions

Description

Compare packed single-precision (32-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst".

Operation

FOR j := 0 to 7
    i := j*32
    dst[i+31:i] := MAX(a[i+31:i], b[i+31:i])
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 1 | 2
Jaguar | 2 | 2 | 2
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 4 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 4 | 0.5 |


_mm256_min_epi16

__m256i _mm256_min_epi16( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: vpminsw
CPUID Flag: AVX2
Category: Special Math Functions

Description

Compare packed 16-bit integers in "a" and "b", and store packed minimum values in "dst".

Operation

FOR j := 0 to 15
    i := j*16
    IF a[i+15:i] < b[i+15:i]
        dst[i+15:i] := a[i+15:i]
    ELSE
        dst[i+15:i] := b[i+15:i]
    FI
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.67 | 2
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1


_mm256_min_epi32

__m256i _mm256_min_epi32( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: vpminsd
CPUID Flag: AVX2
Category: Special Math Functions

Description

Compare packed 32-bit integers in "a" and "b", and store packed minimum values in "dst".

Operation

FOR j := 0 to 7
    i := j*32
    IF a[i+31:i] < b[i+31:i]
        dst[i+31:i] := a[i+31:i]
    ELSE
        dst[i+31:i] := b[i+31:i]
    FI
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.67 | 2
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1


_mm256_min_epi8

__m256i _mm256_min_epi8( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: vpminsb
CPUID Flag: AVX2
Category: Special Math Functions

Description

Compare packed 8-bit integers in "a" and "b", and store packed minimum values in "dst".

Operation

FOR j := 0 to 31
    i := j*8
    IF a[i+7:i] < b[i+7:i]
        dst[i+7:i] := a[i+7:i]
    ELSE
        dst[i+7:i] := b[i+7:i]
    FI
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.67 | 2
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.5 | 1


_mm256_min_epu16

__m256i _mm256_min_epu16( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: vpminuw
CPUID Flag: AVX2
Category: Special Math Functions

Description

Compare packed unsigned 16-bit integers in "a" and "b", and store packed minimum values in "dst".

Operation

FOR j := 0 to 15
    i := j*16
    IF a[i+15:i] < b[i+15:i]
        dst[i+15:i] := a[i+15:i]
    ELSE
        dst[i+15:i] := b[i+15:i]
    FI
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.67 | 2
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.5 | 1


_mm256_min_epu32

__m256i _mm256_min_epu32( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: vpminud
CPUID Flag: AVX2
Category: Special Math Functions

Description

Compare packed unsigned 32-bit integers in "a" and "b", and store packed minimum values in "dst".

Operation

FOR j := 0 to 7
    i := j*32
    IF a[i+31:i] < b[i+31:i]
        dst[i+31:i] := a[i+31:i]
    ELSE
        dst[i+31:i] := b[i+31:i]
    FI
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.67 | 2
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.5 | 1


_mm256_min_epu8

__m256i _mm256_min_epu8( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: vpminub
CPUID Flag: AVX2
Category: Special Math Functions

Description

Compare packed unsigned 8-bit integers in "a" and "b", and store packed minimum values in "dst".

Operation

FOR j := 0 to 31
    i := j*8
    IF a[i+7:i] < b[i+7:i]
        dst[i+7:i] := a[i+7:i]
    ELSE
        dst[i+7:i] := b[i+7:i]
    FI
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.67 | 2
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1


_mm256_min_pd

__m256d _mm256_min_pd( __m256d a, __m256d b )

Synopsis

#include "immintrin.h"
Instruction: vminpd
CPUID Flag: AVX
Category: Special Math Functions

Description

Compare packed double-precision (64-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst".

Operation

FOR j := 0 to 3
    i := j*64
    dst[i+63:i] := MIN(a[i+63:i], b[i+63:i])
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 1 | 2
Jaguar | 2 | 2 | 2
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 4 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 4 | 0.5 |


_mm256_min_ps

__m256 _mm256_min_ps( __m256 a, __m256 b )

Synopsis

#include "immintrin.h"
Instruction: vminps
CPUID Flag: AVX
Category: Special Math Functions

Description

Compare packed single-precision (32-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst".

Operation

FOR j := 0 to 7
    i := j*32
    dst[i+31:i] := MIN(a[i+31:i], b[i+31:i])
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 1 | 2
Jaguar | 2 | 2 | 2
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 4 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 4 | 0.5 |


_mm256_movedup_pd

__m256d _mm256_movedup_pd( __m256d a )

Synopsis

#include "immintrin.h"
Instruction: vmovddup
CPUID Flag: AVX
Category: Move

Description

Duplicate even-indexed double-precision (64-bit) floating-point elements from "a", and store the results in "dst".

Operation

dst[63:0] := a[63:0]
dst[127:64] := a[63:0]
dst[191:128] := a[191:128]
dst[255:192] := a[191:128]
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 1 | 2
Jaguar | 2 | 1 | 2
Sandy Bridge | 1 | 1 | 1
Ivy Bridge | 1 | 1 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 3-6 | 1 | 1
Ivy Bridge | 1 | 1 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm256_movehdup_ps

__m256 _mm256_movehdup_ps( __m256 a )

Synopsis

#include "immintrin.h"
Instruction: vmovshdup
CPUID Flag: AVX
Category: Move

Description

Duplicate odd-indexed single-precision (32-bit) floating-point elements from "a", and store the results in "dst".

Operation

dst[31:0] := a[63:32]
dst[63:32] := a[63:32]
dst[95:64] := a[127:96]
dst[127:96] := a[127:96]
dst[159:128] := a[191:160]
dst[191:160] := a[191:160]
dst[223:192] := a[255:224]
dst[255:224] := a[255:224]
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen |  | 1 | 2
Jaguar | 1 | 1 | 2
Sandy Bridge | 1 | 1 | 1
Ivy Bridge | 1 | 1 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 3-6 | 1 | 1
Ivy Bridge | 1 | 1 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm256_moveldup_ps

__m256 _mm256_moveldup_ps( __m256 a )

Synopsis

#include "immintrin.h"
Instruction: vmovsldup
CPUID Flag: AVX
Category: Move

Description

Duplicate even-indexed single-precision (32-bit) floating-point elements from "a", and store the results in "dst".

Operation

dst[31:0] := a[31:0]
dst[63:32] := a[31:0]
dst[95:64] := a[95:64]
dst[127:96] := a[95:64]
dst[159:128] := a[159:128]
dst[191:160] := a[159:128]
dst[223:192] := a[223:192]
dst[255:224] := a[223:192]
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen |  | 1 | 2
Jaguar | 1 | 1 | 2
Sandy Bridge | 1 | 1 | 1
Ivy Bridge | 1 | 1 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 3-6 | 1 | 1
Ivy Bridge | 1 | 1 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm256_movemask_epi8

int _mm256_movemask_epi8( __m256i a )

Synopsis

#include "immintrin.h"
Instruction: vpmovmskb
CPUID Flag: AVX2
Category: Miscellaneous

Description

Create mask from the most significant bit of each 8-bit element in "a", and store the result in "dst".

Operation

FOR j := 0 to 31
    i := j*8
    dst[j] := a[i+7]
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 2 | 2
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 2-3 | 1 | 1
Knights Landing | 26 | 12 | 12


_mm256_movemask_pd

int _mm256_movemask_pd( __m256d a )

Synopsis

#include "immintrin.h"
Instruction: vmovmskpd
CPUID Flag: AVX
Category: Miscellaneous

Description

Set each bit of mask "dst" based on the most significant bit of the corresponding packed double-precision (64-bit) floating-point element in "a".

Operation

FOR j := 0 to 3
    i := j*64
    IF a[i+63]
        dst[j] := 1
    ELSE
        dst[j] := 0
    FI
ENDFOR
dst[MAX:4] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 1 | 1
Jaguar | 3 | 1 | 1
Sandy Bridge | 2 | 1 | 1
Ivy Bridge | 2 | 1 | 1
Haswell | 2 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 3 | 1 | 1
Ivy Bridge | 1 | 1 |
Haswell | 2 | 1 |
Broadwell | 2 | 1 |
Skylake | 2 | 1 |


_mm256_movemask_ps

int _mm256_movemask_ps( __m256 a )

Synopsis

#include "immintrin.h"
Instruction: vmovmskps
CPUID Flag: AVX
Category: Miscellaneous

Description

Set each bit of mask "dst" based on the most significant bit of the corresponding packed single-precision (32-bit) floating-point element in "a".

Operation

FOR j := 0 to 7
    i := j*32
    IF a[i+31]
        dst[j] := 1
    ELSE
        dst[j] := 0
    FI
ENDFOR
dst[MAX:8] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 1 | 1
Jaguar | 3 | 1 | 1
Sandy Bridge | 2 | 1 | 1
Ivy Bridge | 2 | 1 | 1
Haswell | 2 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 3 | 1 | 1
Ivy Bridge | 1 | 1 |
Haswell | 2 | 1 |
Broadwell | 2 | 1 |
Skylake | 2 | 1 |


_mm256_mpsadbw_epu8

__m256i _mm256_mpsadbw_epu8( __m256i a, __m256i b, const int imm8 )

Synopsis

#include "immintrin.h"
Instruction: vmpsadbw
CPUID Flag: AVX2
Category: Miscellaneous

Description

Compute the sum of absolute differences (SADs) of quadruplets of unsigned 8-bit integers in "a" compared to those in "b", and store the 16-bit results in "dst". Eight SADs are performed for each 128-bit lane using one quadruplet from "b" and eight quadruplets from "a". One quadruplet is selected from "b" starting at on the offset specified in "imm8". Eight quadruplets are formed from sequential 8-bit integers selected from "a" starting at the offset specified in "imm8".

Operation

DEFINE MPSADBW(a[127:0], b[127:0], imm8[2:0]) {
    a_offset := imm8[2]*32
    b_offset := imm8[1:0]*32
    FOR j := 0 to 7
        i := j*8
        k := a_offset+i
        l := b_offset
        tmp[i+15:i] := ABS(a[k+7:k] - b[l+7:l]) + ABS(a[k+15:k+8] - b[l+15:l+8]) + ABS(a[k+23:k+16] - b[l+23:l+16]) + ABS(a[k+31:k+24] - b[l+31:l+24])
    ENDFOR
    RETURN tmp[127:0]
}
dst[127:0] := MPSADBW(a[127:0], b[127:0], imm8[2:0])
dst[255:128] := MPSADBW(a[255:128], b[255:128], imm8[5:3])
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 4 | 3 | 8
Haswell | 6 | 2 | 3
Broadwell | 6 | 2 | 3
Skylake | 4 | 2 | 2
Knights Landing | 19 | 13 | 9
Haswell | 6 | 2 |
Broadwell | 6 | 2 |
Skylake | 4 | 2 |


_mm256_mul_epi32

__m256i _mm256_mul_epi32( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: vpmuldq
CPUID Flag: AVX2
Category: Arithmetic

Description

Multiply the low 32-bit integers from each packed 64-bit element in "a" and "b", and store the signed 64-bit results in "dst".

Operation

FOR j := 0 to 3
    i := j*64
    dst[i+63:i] := a[i+31:i] * b[i+31:i]
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 2 | 2
Haswell | 5 | 1 | 1
Broadwell | 5 | 1 | 1
Skylake | 5 | 0.5 | 1
Knights Landing | 6 | 0.5 | 1
Haswell | 5 | 1 |
Broadwell | 5 | 1 |
Skylake | 5 | 0.5 |


_mm256_mul_epu32

__m256i _mm256_mul_epu32( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: vpmuludq
CPUID Flag: AVX2
Category: Arithmetic

Description

Multiply the low unsigned 32-bit integers from each packed 64-bit element in "a" and "b", and store the unsigned 64-bit results in "dst".

Operation

FOR j := 0 to 3
    i := j*64
    dst[i+63:i] := a[i+31:i] * b[i+31:i]
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 2 | 2
Haswell | 5 | 1 | 1
Broadwell | 5 | 1 | 1
Skylake | 5 | 0.5 | 1
Knights Landing | 6 | 0.5 | 1
Haswell | 5 | 1 |
Broadwell | 5 | 1 |
Skylake | 5 | 0.5 |


_mm256_mul_pd

__m256d _mm256_mul_pd( __m256d a, __m256d b )

Synopsis

#include "immintrin.h"
Instruction: vmulpd
CPUID Flag: AVX
Category: Arithmetic

Description

Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*64
    dst[i+63:i] := a[i+63:i] * b[i+63:i]
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 4 | 1 | 2
Jaguar | 4 | 2 | 2
Sandy Bridge | 5 | 1 | 1
Ivy Bridge | 5 | 1 | 1
Haswell | 5 | 0.5 | 1
Broadwell | 3 | 0.5 | 1
Skylake | 4 | 0.5 | 1
Knights Landing | 6 | 0.5 | 1
Ivy Bridge | 5 | 1 |
Haswell | 5 | 0.5 |
Broadwell | 3 | 0.5 |
Skylake | 4 | 0.5 |


_mm256_mul_ps

__m256 _mm256_mul_ps( __m256 a, __m256 b )

Synopsis

#include "immintrin.h"
Instruction: vmulps
CPUID Flag: AVX
Category: Arithmetic

Description

Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*32
    dst[i+31:i] := a[i+31:i] * b[i+31:i]
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 1 | 2
Jaguar | 2 | 2 | 2
Sandy Bridge | 5 | 1 | 1
Ivy Bridge | 5 | 1 | 1
Haswell | 5 | 0.5 | 1
Broadwell | 3 | 0.5 | 1
Skylake | 4 | 0.5 | 1
Knights Landing | 6 | 0.5 | 1
Ivy Bridge | 5 | 1 |
Haswell | 5 | 0.5 |
Broadwell | 3 | 0.5 |
Skylake | 4 | 0.5 |


_mm256_mulhi_epi16

__m256i _mm256_mulhi_epi16( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: vpmulhw
CPUID Flag: AVX2
Category: Arithmetic

Description

Multiply the packed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst".

Operation

FOR j := 0 to 15
    i := j*16
    tmp[31:0] := a[i+15:i] * b[i+15:i]
    dst[i+15:i] := tmp[31:16]
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 2 | 2
Haswell | 5 | 1 | 1
Broadwell | 5 | 1 | 1
Skylake | 5 | 0.5 | 1
Knights Landing | 16 | 9 | 5
Haswell | 5 | 1 |
Broadwell | 5 | 1 |
Skylake | 5 | 0.5 |


_mm256_mulhi_epu16

__m256i _mm256_mulhi_epu16( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: vpmulhuw
CPUID Flag: AVX2
Category: Arithmetic

Description

Multiply the packed unsigned 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst".

Operation

FOR j := 0 to 15
    i := j*16
    tmp[31:0] := a[i+15:i] * b[i+15:i]
    dst[i+15:i] := tmp[31:16]
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 2 | 2
Haswell | 5 | 1 | 1
Broadwell | 5 | 1 | 1
Skylake | 5 | 0.5 | 1
Knights Landing | 16 | 9 | 5


_mm256_mulhrs_epi16

__m256i _mm256_mulhrs_epi16( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: vpmulhrsw
CPUID Flag: AVX2
Category: Arithmetic

Description

Multiply packed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers. Truncate each intermediate integer to the 18 most significant bits, round by adding 1, and store bits [16:1] to "dst".

Operation

FOR j := 0 to 15
    i := j*16
    tmp[31:0] := ((a[i+15:i] * b[i+15:i]) >> 14) + 1
    dst[i+15:i] := tmp[16:1]
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 4 | 2 | 2
Haswell | 5 | 1 | 1
Broadwell | 5 | 1 | 1
Skylake | 5 | 0.5 | 1
Haswell | 5 | 1 |
Broadwell | 5 | 1 |
Skylake | 5 | 0.5 |


_mm256_mullo_epi16

__m256i _mm256_mullo_epi16( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: vpmullw
CPUID Flag: AVX2
Category: Arithmetic

Description

Multiply the packed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the low 16 bits of the intermediate integers in "dst".

Operation

FOR j := 0 to 15
    i := j*16
    tmp[31:0] := a[i+15:i] * b[i+15:i]
    dst[i+15:i] := tmp[15:0]
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 2 | 2
Haswell | 5 | 1 | 1
Broadwell | 5 | 1 | 1
Skylake | 5 | 0.5 | 1
Knights Landing | 16 | 9 | 5
Haswell | 5 | 1 |
Broadwell | 5 | 1 |
Skylake | 5 | 0.5 |


_mm256_mullo_epi32

__m256i _mm256_mullo_epi32( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: vpmulld
CPUID Flag: AVX2
Category: Arithmetic

Description

Multiply the packed 32-bit integers in "a" and "b", producing intermediate 64-bit integers, and store the low 32 bits of the intermediate integers in "dst".

Operation

FOR j := 0 to 7
    i := j*32
    tmp[63:0] := a[i+31:i] * b[i+31:i]
    dst[i+31:i] := tmp[31:0]
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 4 | 4 | 2
Haswell | 10 | 2 | 2
Broadwell | 10 | 2 | 2
Skylake | 10 | 1 | 2
Knights Landing | 7 | 1 | 1
Haswell | 10 | 2 |
Broadwell | 10 | 2 |
Skylake | 10 | 1 |


_mm256_or_pd

__m256d _mm256_or_pd( __m256d a, __m256d b )

Synopsis

#include "immintrin.h"
Instruction: vorpd
CPUID Flag: AVX
Category: Logical

Description

Compute the bitwise OR of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*64
    dst[i+63:i] := a[i+63:i] OR b[i+63:i]
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 2
Sandy Bridge | 1 | 1 | 1
Ivy Bridge | 1 | 1 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 0.33 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 1 | 1 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 0.33 |


_mm256_or_ps

__m256 _mm256_or_ps( __m256 a, __m256 b )

Synopsis

#include "immintrin.h"
Instruction: vorps
CPUID Flag: AVX
Category: Logical

Description

Compute the bitwise OR of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*32
    dst[i+31:i] := a[i+31:i] OR b[i+31:i]
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 2
Sandy Bridge | 1 | 1 | 1
Ivy Bridge | 1 | 1 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 0.33 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 1 | 1 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 0.33 |


_mm256_or_si256

__m256i _mm256_or_si256( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: vpor
CPUID Flag: AVX2
Category: Logical

Description

Compute the bitwise OR of 256 bits (representing integer data) in "a" and "b", and store the result in "dst".

Operation

dst[255:0] := (a[255:0] OR b[255:0])
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 2
Haswell | 1 | 0.33 | 1
Broadwell | 1 | 0.33 | 1
Skylake | 1 | 0.33 | 1
Knights Landing | 2 | 0.5 | 1
Haswell | 1 | 0.33 |
Broadwell | 1 | 0.33 |
Skylake | 1 | 0.33 |


_mm256_packs_epi16

__m256i _mm256_packs_epi16( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: vpacksswb
CPUID Flag: AVX2
Category: Miscellaneous

Description

Convert packed 16-bit integers from "a" and "b" to packed 8-bit integers using signed saturation, and store the results in "dst".

Operation

dst[7:0] := Saturate_Int16_To_Int8 (a[15:0])
dst[15:8] := Saturate_Int16_To_Int8 (a[31:16])
dst[23:16] := Saturate_Int16_To_Int8 (a[47:32])
dst[31:24] := Saturate_Int16_To_Int8 (a[63:48])
dst[39:32] := Saturate_Int16_To_Int8 (a[79:64])
dst[47:40] := Saturate_Int16_To_Int8 (a[95:80])
dst[55:48] := Saturate_Int16_To_Int8 (a[111:96])
dst[63:56] := Saturate_Int16_To_Int8 (a[127:112])
dst[71:64] := Saturate_Int16_To_Int8 (b[15:0])
dst[79:72] := Saturate_Int16_To_Int8 (b[31:16])
dst[87:80] := Saturate_Int16_To_Int8 (b[47:32])
dst[95:88] := Saturate_Int16_To_Int8 (b[63:48])
dst[103:96] := Saturate_Int16_To_Int8 (b[79:64])
dst[111:104] := Saturate_Int16_To_Int8 (b[95:80])
dst[119:112] := Saturate_Int16_To_Int8 (b[111:96])
dst[127:120] := Saturate_Int16_To_Int8 (b[127:112])
dst[135:128] := Saturate_Int16_To_Int8 (a[143:128])
dst[143:136] := Saturate_Int16_To_Int8 (a[159:144])
dst[151:144] := Saturate_Int16_To_Int8 (a[175:160])
dst[159:152] := Saturate_Int16_To_Int8 (a[191:176])
dst[167:160] := Saturate_Int16_To_Int8 (a[207:192])
dst[175:168] := Saturate_Int16_To_Int8 (a[223:208])
dst[183:176] := Saturate_Int16_To_Int8 (a[239:224])
dst[191:184] := Saturate_Int16_To_Int8 (a[255:240])
dst[199:192] := Saturate_Int16_To_Int8 (b[143:128])
dst[207:200] := Saturate_Int16_To_Int8 (b[159:144])
dst[215:208] := Saturate_Int16_To_Int8 (b[175:160])
dst[223:216] := Saturate_Int16_To_Int8 (b[191:176])
dst[231:224] := Saturate_Int16_To_Int8 (b[207:192])
dst[239:232] := Saturate_Int16_To_Int8 (b[223:208])
dst[247:240] := Saturate_Int16_To_Int8 (b[239:224])
dst[255:248] := Saturate_Int16_To_Int8 (b[255:240])
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 1 | 2
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 11-14 | 9 | 5
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm256_packs_epi32

__m256i _mm256_packs_epi32( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: vpackssdw
CPUID Flag: AVX2
Category: Miscellaneous

Description

Convert packed 32-bit integers from "a" and "b" to packed 16-bit integers using signed saturation, and store the results in "dst".

Operation

dst[15:0] := Saturate_Int32_To_Int16 (a[31:0])
dst[31:16] := Saturate_Int32_To_Int16 (a[63:32])
dst[47:32] := Saturate_Int32_To_Int16 (a[95:64])
dst[63:48] := Saturate_Int32_To_Int16 (a[127:96])
dst[79:64] := Saturate_Int32_To_Int16 (b[31:0])
dst[95:80] := Saturate_Int32_To_Int16 (b[63:32])
dst[111:96] := Saturate_Int32_To_Int16 (b[95:64])
dst[127:112] := Saturate_Int32_To_Int16 (b[127:96])
dst[143:128] := Saturate_Int32_To_Int16 (a[159:128])
dst[159:144] := Saturate_Int32_To_Int16 (a[191:160])
dst[175:160] := Saturate_Int32_To_Int16 (a[223:192])
dst[191:176] := Saturate_Int32_To_Int16 (a[255:224])
dst[207:192] := Saturate_Int32_To_Int16 (b[159:128])
dst[223:208] := Saturate_Int32_To_Int16 (b[191:160])
dst[239:224] := Saturate_Int32_To_Int16 (b[223:192])
dst[255:240] := Saturate_Int32_To_Int16 (b[255:224])
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 1 | 2
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 11-14 | 9 | 5


_mm256_packus_epi16

__m256i _mm256_packus_epi16( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: vpackuswb
CPUID Flag: AVX2
Category: Miscellaneous

Description

Convert packed 16-bit integers from "a" and "b" to packed 8-bit integers using unsigned saturation, and store the results in "dst".

Operation

dst[7:0] := Saturate_Int16_To_UnsignedInt8 (a[15:0])
dst[15:8] := Saturate_Int16_To_UnsignedInt8 (a[31:16])
dst[23:16] := Saturate_Int16_To_UnsignedInt8 (a[47:32])
dst[31:24] := Saturate_Int16_To_UnsignedInt8 (a[63:48])
dst[39:32] := Saturate_Int16_To_UnsignedInt8 (a[79:64])
dst[47:40] := Saturate_Int16_To_UnsignedInt8 (a[95:80])
dst[55:48] := Saturate_Int16_To_UnsignedInt8 (a[111:96])
dst[63:56] := Saturate_Int16_To_UnsignedInt8 (a[127:112])
dst[71:64] := Saturate_Int16_To_UnsignedInt8 (b[15:0])
dst[79:72] := Saturate_Int16_To_UnsignedInt8 (b[31:16])
dst[87:80] := Saturate_Int16_To_UnsignedInt8 (b[47:32])
dst[95:88] := Saturate_Int16_To_UnsignedInt8 (b[63:48])
dst[103:96] := Saturate_Int16_To_UnsignedInt8 (b[79:64])
dst[111:104] := Saturate_Int16_To_UnsignedInt8 (b[95:80])
dst[119:112] := Saturate_Int16_To_UnsignedInt8 (b[111:96])
dst[127:120] := Saturate_Int16_To_UnsignedInt8 (b[127:112])
dst[135:128] := Saturate_Int16_To_UnsignedInt8 (a[143:128])
dst[143:136] := Saturate_Int16_To_UnsignedInt8 (a[159:144])
dst[151:144] := Saturate_Int16_To_UnsignedInt8 (a[175:160])
dst[159:152] := Saturate_Int16_To_UnsignedInt8 (a[191:176])
dst[167:160] := Saturate_Int16_To_UnsignedInt8 (a[207:192])
dst[175:168] := Saturate_Int16_To_UnsignedInt8 (a[223:208])
dst[183:176] := Saturate_Int16_To_UnsignedInt8 (a[239:224])
dst[191:184] := Saturate_Int16_To_UnsignedInt8 (a[255:240])
dst[199:192] := Saturate_Int16_To_UnsignedInt8 (b[143:128])
dst[207:200] := Saturate_Int16_To_UnsignedInt8 (b[159:144])
dst[215:208] := Saturate_Int16_To_UnsignedInt8 (b[175:160])
dst[223:216] := Saturate_Int16_To_UnsignedInt8 (b[191:176])
dst[231:224] := Saturate_Int16_To_UnsignedInt8 (b[207:192])
dst[239:232] := Saturate_Int16_To_UnsignedInt8 (b[223:208])
dst[247:240] := Saturate_Int16_To_UnsignedInt8 (b[239:224])
dst[255:248] := Saturate_Int16_To_UnsignedInt8 (b[255:240])
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 1 | 2
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 11-14 | 9 | 5


_mm256_packus_epi32

__m256i _mm256_packus_epi32( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: vpackusdw
CPUID Flag: AVX2
Category: Miscellaneous

Description

Convert packed 32-bit integers from "a" and "b" to packed 16-bit integers using unsigned saturation, and store the results in "dst".

Operation

dst[15:0] := Saturate_Int32_To_UnsignedInt16 (a[31:0])
dst[31:16] := Saturate_Int32_To_UnsignedInt16 (a[63:32])
dst[47:32] := Saturate_Int32_To_UnsignedInt16 (a[95:64])
dst[63:48] := Saturate_Int32_To_UnsignedInt16 (a[127:96])
dst[79:64] := Saturate_Int32_To_UnsignedInt16 (b[31:0])
dst[95:80] := Saturate_Int32_To_UnsignedInt16 (b[63:32])
dst[111:96] := Saturate_Int32_To_UnsignedInt16 (b[95:64])
dst[127:112] := Saturate_Int32_To_UnsignedInt16 (b[127:96])
dst[143:128] := Saturate_Int32_To_UnsignedInt16 (a[159:128])
dst[159:144] := Saturate_Int32_To_UnsignedInt16 (a[191:160])
dst[175:160] := Saturate_Int32_To_UnsignedInt16 (a[223:192])
dst[191:176] := Saturate_Int32_To_UnsignedInt16 (a[255:224])
dst[207:192] := Saturate_Int32_To_UnsignedInt16 (b[159:128])
dst[223:208] := Saturate_Int32_To_UnsignedInt16 (b[191:160])
dst[239:224] := Saturate_Int32_To_UnsignedInt16 (b[223:192])
dst[255:240] := Saturate_Int32_To_UnsignedInt16 (b[255:224])
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 11-14 | 9 | 5
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm256_permute_pd

__m256d _mm256_permute_pd( __m256d a, int imm8 )

Synopsis

#include "immintrin.h"
Instruction: vpermilpd
CPUID Flag: AVX
Category: Swizzle

Description

Shuffle double-precision (64-bit) floating-point elements in "a" within 128-bit lanes using the control in "imm8", and store the results in "dst".

Operation

IF (imm8[0] == 0) dst[63:0] := a[63:0]; FI
IF (imm8[0] == 1) dst[63:0] := a[127:64]; FI
IF (imm8[1] == 0) dst[127:64] := a[63:0]; FI
IF (imm8[1] == 1) dst[127:64] := a[127:64]; FI
IF (imm8[2] == 0) dst[191:128] := a[191:128]; FI
IF (imm8[2] == 1) dst[191:128] := a[255:192]; FI
IF (imm8[3] == 0) dst[255:192] := a[191:128]; FI
IF (imm8[3] == 1) dst[255:192] := a[255:192]; FI
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 4 | 4 | 2
Sandy Bridge | 1 | 1 | 1
Ivy Bridge | 1 | 1 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 3-6 | 1 | 1
Ivy Bridge | 1 | 1 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm256_permute_ps

__m256 _mm256_permute_ps( __m256 a, int imm8 )

Synopsis

#include "immintrin.h"
Instruction: vpermilps
CPUID Flag: AVX
Category: Swizzle

Description

Shuffle single-precision (32-bit) floating-point elements in "a" within 128-bit lanes using the control in "imm8", and store the results in "dst".

Operation

DEFINE SELECT4(src, control) {
    CASE(control[1:0]) OF
    0:	tmp[31:0] := src[31:0]
    1:	tmp[31:0] := src[63:32]
    2:	tmp[31:0] := src[95:64]
    3:	tmp[31:0] := src[127:96]
    ESAC
    RETURN tmp[31:0]
}
dst[31:0] := SELECT4(a[127:0], imm8[1:0])
dst[63:32] := SELECT4(a[127:0], imm8[3:2])
dst[95:64] := SELECT4(a[127:0], imm8[5:4])
dst[127:96] := SELECT4(a[127:0], imm8[7:6])
dst[159:128] := SELECT4(a[255:128], imm8[1:0])
dst[191:160] := SELECT4(a[255:128], imm8[3:2])
dst[223:192] := SELECT4(a[255:128], imm8[5:4])
dst[255:224] := SELECT4(a[255:128], imm8[7:6])
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 4 | 4 | 2
Sandy Bridge | 1 | 1 | 1
Ivy Bridge | 1 | 1 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 3-6 | 1 | 1
Ivy Bridge | 1 | 1 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm256_permute2f128_pd

__m256d _mm256_permute2f128_pd( __m256d a, __m256d b, int imm8 )

Synopsis

#include "immintrin.h"
Instruction: vperm2f128
CPUID Flag: AVX
Category: Swizzle

Description

Shuffle 128-bits (composed of 2 packed double-precision (64-bit) floating-point elements) selected by "imm8" from "a" and "b", and store the results in "dst".

Operation

DEFINE SELECT4(src1, src2, control) {
    CASE(control[1:0]) OF
    0:	tmp[127:0] := src1[127:0]
    1:	tmp[127:0] := src1[255:128]
    2:	tmp[127:0] := src2[127:0]
    3:	tmp[127:0] := src2[255:128]
    ESAC
    IF control[3]
        tmp[127:0] := 0
    FI
    RETURN tmp[127:0]
}
dst[127:0] := SELECT4(a[255:0], b[255:0], imm8[3:0])
dst[255:128] := SELECT4(a[255:0], b[255:0], imm8[7:4])
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 3 | 8
Sandy Bridge | 2 | 1 | 1
Ivy Bridge | 2 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 3 | 1 | 1
Knights Landing | 4-7 | 2 | 1
Ivy Bridge | 2 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 3 | 1 |


_mm256_permute2f128_ps

__m256 _mm256_permute2f128_ps( __m256 a, __m256 b, int imm8 )

Synopsis

#include "immintrin.h"
Instruction: vperm2f128
CPUID Flag: AVX
Category: Swizzle

Description

Shuffle 128-bits (composed of 4 packed single-precision (32-bit) floating-point elements) selected by "imm8" from "a" and "b", and store the results in "dst".

Operation

DEFINE SELECT4(src1, src2, control) {
    CASE(control[1:0]) OF
    0:	tmp[127:0] := src1[127:0]
    1:	tmp[127:0] := src1[255:128]
    2:	tmp[127:0] := src2[127:0]
    3:	tmp[127:0] := src2[255:128]
    ESAC
    IF control[3]
        tmp[127:0] := 0
    FI
    RETURN tmp[127:0]
}
dst[127:0] := SELECT4(a[255:0], b[255:0], imm8[3:0])
dst[255:128] := SELECT4(a[255:0], b[255:0], imm8[7:4])
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 3 | 8
Sandy Bridge | 2 | 1 | 1
Ivy Bridge | 2 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 3 | 1 | 1
Knights Landing | 4-7 | 2 | 1
Ivy Bridge | 2 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 3 | 1 |


_mm256_permute2f128_si256

__m256i _mm256_permute2f128_si256( __m256i a, __m256i b, int imm8 )

Synopsis

#include "immintrin.h"
Instruction: vperm2f128
CPUID Flag: AVX
Category: Swizzle

Description

Shuffle 128-bits (composed of integer data) selected by "imm8" from "a" and "b", and store the results in "dst".

Operation

DEFINE SELECT4(src1, src2, control) {
    CASE(control[1:0]) OF
    0:	tmp[127:0] := src1[127:0]
    1:	tmp[127:0] := src1[255:128]
    2:	tmp[127:0] := src2[127:0]
    3:	tmp[127:0] := src2[255:128]
    ESAC
    IF control[3]
        tmp[127:0] := 0
    FI
    RETURN tmp[127:0]
}
dst[127:0] := SELECT4(a[255:0], b[255:0], imm8[3:0])
dst[255:128] := SELECT4(a[255:0], b[255:0], imm8[7:4])
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 3 | 8
Sandy Bridge | 2 | 1 | 1
Ivy Bridge | 2 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 3 | 1 | 1
Knights Landing | 4-7 | 2 | 1
Ivy Bridge | 2 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 3 | 1 |


_mm256_permute2x128_si256

__m256i _mm256_permute2x128_si256( __m256i a, __m256i b, const int imm8 )

Synopsis

#include "immintrin.h"
Instruction: vperm2i128
CPUID Flag: AVX2
Category: Swizzle

Description

Shuffle 128-bits (composed of integer data) selected by "imm8" from "a" and "b", and store the results in "dst".

Operation

DEFINE SELECT4(src1, src2, control) {
    CASE(control[1:0]) OF
    0:	tmp[127:0] := src1[127:0]
    1:	tmp[127:0] := src1[255:128]
    2:	tmp[127:0] := src2[127:0]
    3:	tmp[127:0] := src2[255:128]
    ESAC
    IF control[3]
        tmp[127:0] := 0
    FI
    RETURN tmp[127:0]
}
dst[127:0] := SELECT4(a[255:0], b[255:0], imm8[3:0])
dst[255:128] := SELECT4(a[255:0], b[255:0], imm8[7:4])
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 3 | 1 | 1
Knights Landing | 4-7 | 2 | 1


_mm256_permute4x64_epi64

__m256i _mm256_permute4x64_epi64( __m256i a, const int imm8 )

Synopsis

#include "immintrin.h"
Instruction: vpermq
CPUID Flag: AVX2
Category: Swizzle

Description

Shuffle 64-bit integers in "a" across lanes using the control in "imm8", and store the results in "dst".

Operation

DEFINE SELECT4(src, control) {
    CASE(control[1:0]) OF
    0:	tmp[63:0] := src[63:0]
    1:	tmp[63:0] := src[127:64]
    2:	tmp[63:0] := src[191:128]
    3:	tmp[63:0] := src[255:192]
    ESAC
    RETURN tmp[63:0]
}
dst[63:0] := SELECT4(a[255:0], imm8[1:0])
dst[127:64] := SELECT4(a[255:0], imm8[3:2])
dst[191:128] := SELECT4(a[255:0], imm8[5:4])
dst[255:192] := SELECT4(a[255:0], imm8[7:6])
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 3 | 1 | 1
Knights Landing | 3-6 | 1 | 1


_mm256_permute4x64_pd

__m256d _mm256_permute4x64_pd( __m256d a, const int imm8 )

Synopsis

#include "immintrin.h"
Instruction: vpermpd
CPUID Flag: AVX2
Category: Swizzle

Description

Shuffle double-precision (64-bit) floating-point elements in "a" across lanes using the control in "imm8", and store the results in "dst".

Operation

DEFINE SELECT4(src, control) {
    CASE(control[1:0]) OF
    0:	tmp[63:0] := src[63:0]
    1:	tmp[63:0] := src[127:64]
    2:	tmp[63:0] := src[191:128]
    3:	tmp[63:0] := src[255:192]
    ESAC
    RETURN tmp[63:0]
}
dst[63:0] := SELECT4(a[255:0], imm8[1:0])
dst[127:64] := SELECT4(a[255:0], imm8[3:2])
dst[191:128] := SELECT4(a[255:0], imm8[5:4])
dst[255:192] := SELECT4(a[255:0], imm8[7:6])
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 2 | 2 | 3
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 3 | 1 | 1
Knights Landing | 3-6 | 1 | 1
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 3 | 1 |


_mm256_permutevar_pd

__m256d _mm256_permutevar_pd( __m256d a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: vpermilpd
CPUID Flag: AVX
Category: Swizzle

Description

Shuffle double-precision (64-bit) floating-point elements in "a" within 128-bit lanes using the control in "b", and store the results in "dst".

Operation

IF (b[1] == 0) dst[63:0] := a[63:0]; FI
IF (b[1] == 1) dst[63:0] := a[127:64]; FI
IF (b[65] == 0) dst[127:64] := a[63:0]; FI
IF (b[65] == 1) dst[127:64] := a[127:64]; FI
IF (b[129] == 0) dst[191:128] := a[191:128]; FI
IF (b[129] == 1) dst[191:128] := a[255:192]; FI
IF (b[193] == 0) dst[255:192] := a[191:128]; FI
IF (b[193] == 1) dst[255:192] := a[255:192]; FI
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 4 | 4 | 2
Sandy Bridge | 1 | 1 | 1
Ivy Bridge | 1 | 1 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 3-6 | 1 | 1
Ivy Bridge | 1 | 1 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm256_permutevar_ps

__m256 _mm256_permutevar_ps( __m256 a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: vpermilps
CPUID Flag: AVX
Category: Swizzle

Description

Shuffle single-precision (32-bit) floating-point elements in "a" within 128-bit lanes using the control in "b", and store the results in "dst".

Operation

DEFINE SELECT4(src, control) {
    CASE(control[1:0]) OF
    0:	tmp[31:0] := src[31:0]
    1:	tmp[31:0] := src[63:32]
    2:	tmp[31:0] := src[95:64]
    3:	tmp[31:0] := src[127:96]
    ESAC
    RETURN tmp[31:0]
}
dst[31:0] := SELECT4(a[127:0], b[1:0])
dst[63:32] := SELECT4(a[127:0], b[33:32])
dst[95:64] := SELECT4(a[127:0], b[65:64])
dst[127:96] := SELECT4(a[127:0], b[97:96])
dst[159:128] := SELECT4(a[255:128], b[129:128])
dst[191:160] := SELECT4(a[255:128], b[161:160])
dst[223:192] := SELECT4(a[255:128], b[193:192])
dst[255:224] := SELECT4(a[255:128], b[225:224])
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 4 | 4 | 2
Sandy Bridge | 1 | 1 | 1
Ivy Bridge | 1 | 1 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 3-6 | 1 | 1
Ivy Bridge | 1 | 1 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm256_permutevar8x32_epi32

__m256i _mm256_permutevar8x32_epi32( __m256i a, __m256i idx )

Synopsis

#include "immintrin.h"
Instruction: vpermd
CPUID Flag: AVX2
Category: Swizzle

Description

Shuffle 32-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*32
    id := idx[i+2:i]*32
    dst[i+31:i] := a[id+31:id]
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 3 | 1 | 1
Knights Landing | 3-6 | 1 | 1


_mm256_permutevar8x32_ps

__m256 _mm256_permutevar8x32_ps( __m256 a, __m256i idx )

Synopsis

#include "immintrin.h"
Instruction: vpermps
CPUID Flag: AVX2
Category: Swizzle

Description

Shuffle single-precision (32-bit) floating-point elements in "a" across lanes using the corresponding index in "idx".

Operation

FOR j := 0 to 7
    i := j*32
    id := idx[i+2:i]*32
    dst[i+31:i] := a[id+31:id]
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 5 | 4 | 3
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 3 | 1 | 1
Knights Landing | 3-6 | 1 | 1
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 3 | 1 |


_mm256_pow_pd

__m256d _mm256_pow_pd( __m256d a, __m256d b )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Elementary Math Functions

Description

Compute the exponential value of packed double-precision (64-bit) floating-point elements in "a" raised by packed elements in "b", and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*64
    dst[i+63:i] := (a[i+63:i])^(b[i+63:i])
ENDFOR
dst[MAX:256] := 0


_mm256_pow_ps

__m256 _mm256_pow_ps( __m256 a, __m256 b )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Elementary Math Functions

Description

Compute the exponential value of packed single-precision (32-bit) floating-point elements in "a" raised by packed elements in "b", and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*32
    dst[i+31:i] := (a[i+31:i])^(b[i+31:i])
ENDFOR
dst[MAX:256] := 0


_mm256_rcp_ps

__m256 _mm256_rcp_ps( __m256 a )

Synopsis

#include "immintrin.h"
Instruction: vrcpps
CPUID Flag: AVX
Category: Elementary Math Functions

Description

Compute the approximate reciprocal of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". The maximum relative error for this approximation is less than 1.5*2^-12.

Operation

FOR j := 0 to 7
    i := j*32
    dst[i+31:i] := APPROXIMATE(1.0/a[i+31:i])
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 5 | 2 | 2
Jaguar | 2 | 2 | 2
Sandy Bridge | 7 | 2 | 3
Ivy Bridge | 7 | 2 | 3
Haswell | 7 | 2 | 3
Broadwell | 7 | 2 | 3
Skylake | 4 | 1 | 1
Knights Landing | 8 | 3 | 1
Ivy Bridge | 7 | 2 |
Haswell | 7 | 2 |
Broadwell | 7 | 2 |
Skylake | 4 | 1 |


_mm256_rem_epi16

__m256i _mm256_rem_epi16( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Arithmetic

Description

Divide packed 16-bit integers in "a" by packed elements in "b", and store the remainders as packed 32-bit integers in "dst".

Operation

FOR j := 0 to 15
    i := 16*j
    dst[i+15:i] := REMAINDER(a[i+15:i] / b[i+15:i])
ENDFOR
dst[MAX:256] := 0


_mm256_rem_epi32

__m256i _mm256_rem_epi32( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Arithmetic

Description

Divide packed 32-bit integers in "a" by packed elements in "b", and store the remainders as packed 32-bit integers in "dst".

Operation

FOR j := 0 to 7
    i := 32*j
    dst[i+31:i] := REMAINDER(a[i+31:i] / b[i+31:i])
ENDFOR
dst[MAX:256] := 0


_mm256_rem_epi64

__m256i _mm256_rem_epi64( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Arithmetic

Description

Divide packed 64-bit integers in "a" by packed elements in "b", and store the remainders as packed 32-bit integers in "dst".

Operation

FOR j := 0 to 3
    i := 64*j
    dst[i+63:i] := REMAINDER(a[i+63:i] / b[i+63:i])
ENDFOR
dst[MAX:256] := 0


_mm256_rem_epi8

__m256i _mm256_rem_epi8( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Arithmetic

Description

Divide packed 8-bit integers in "a" by packed elements in "b", and store the remainders as packed 32-bit integers in "dst".

Operation

FOR j := 0 to 31
    i := 8*j
    dst[i+7:i] := REMAINDER(a[i+7:i] / b[i+7:i])
ENDFOR
dst[MAX:256] := 0


_mm256_rem_epu16

__m256i _mm256_rem_epu16( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Arithmetic

Description

Divide packed unsigned 16-bit integers in "a" by packed elements in "b", and store the remainders as packed unsigned 32-bit integers in "dst".

Operation

FOR j := 0 to 15
    i := 16*j
    dst[i+15:i] := REMAINDER(a[i+15:i] / b[i+15:i])
ENDFOR
dst[MAX:256] := 0


_mm256_rem_epu32

__m256i _mm256_rem_epu32( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Arithmetic

Description

Divide packed unsigned 32-bit integers in "a" by packed elements in "b", and store the remainders as packed unsigned 32-bit integers in "dst".

Operation

FOR j := 0 to 7
    i := 32*j
    dst[i+31:i] := REMAINDER(a[i+31:i] / b[i+31:i])
ENDFOR
dst[MAX:256] := 0


_mm256_rem_epu64

__m256i _mm256_rem_epu64( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Arithmetic

Description

Divide packed unsigned 64-bit integers in "a" by packed elements in "b", and store the remainders as packed unsigned 32-bit integers in "dst".

Operation

FOR j := 0 to 3
    i := 64*j
    dst[i+63:i] := REMAINDER(a[i+63:i] / b[i+63:i])
ENDFOR
dst[MAX:256] := 0


_mm256_rem_epu8

__m256i _mm256_rem_epu8( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Arithmetic

Description

Divide packed unsigned 8-bit integers in "a" by packed elements in "b", and store the remainders as packed unsigned 32-bit integers in "dst".

Operation

FOR j := 0 to 31
    i := 8*j
    dst[i+7:i] := REMAINDER(a[i+7:i] / b[i+7:i])
ENDFOR
dst[MAX:256] := 0


_mm256_round_pd

__m256d _mm256_round_pd( __m256d a, int rounding )

Synopsis

#include "immintrin.h"
Instruction: vroundpd
CPUID Flag: AVX
Category: Special Math Functions

Description

Round the packed double-precision (64-bit) floating-point elements in "a" using the "rounding" parameter, and store the results as packed double-precision floating-point elements in "dst". [round_note]

Operation

FOR j := 0 to 3
    i := j*64
    dst[i+63:i] := ROUND(a[i+63:i], rounding)
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 4 | 2 | 2
Jaguar | 4 | 2 | 2
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 6 | 2 | 2
Broadwell | 6 | 2 | 2
Skylake | 8 | 1 | 2
Knights Landing | 6 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 6 | 2 |
Broadwell | 6 | 2 |
Skylake | 8 | 1 |


_mm256_round_ps

__m256 _mm256_round_ps( __m256 a, int rounding )

Synopsis

#include "immintrin.h"
Instruction: vroundps
CPUID Flag: AVX
Category: Special Math Functions

Description

Round the packed single-precision (32-bit) floating-point elements in "a" using the "rounding" parameter, and store the results as packed single-precision floating-point elements in "dst". [round_note]

Operation

FOR j := 0 to 7
    i := j*32
    dst[i+31:i] := ROUND(a[i+31:i], rounding)
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 4 | 2 | 2
Jaguar | 4 | 2 | 2
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 6 | 2 | 2
Broadwell | 6 | 2 | 2
Skylake | 8 | 1 | 2
Knights Landing | 6 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 6 | 2 |
Broadwell | 6 | 2 |
Skylake | 8 | 1 |


_mm256_rsqrt_ps

__m256 _mm256_rsqrt_ps( __m256 a )

Synopsis

#include "immintrin.h"
Instruction: vrsqrtps
CPUID Flag: AVX
Category: Elementary Math Functions

Description

Compute the approximate reciprocal square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". The maximum relative error for this approximation is less than 1.5*2^-12.

Operation

FOR j := 0 to 7
    i := j*32
    dst[i+31:i] := APPROXIMATE(1.0 / SQRT(a[i+31:i]))
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 5 | 2 | 2
Jaguar | 2 | 2 | 2
Sandy Bridge | 7 | 2 | 3
Ivy Bridge | 7 | 2 | 3
Haswell | 7 | 2 | 3
Broadwell | 7 | 2 | 3
Skylake | 4 | 1 | 1
Knights Landing | 7 | 3 | 1
Ivy Bridge | 7 | 2 |
Haswell | 7 | 2 |
Broadwell | 7 | 2 |
Skylake | 4 | 1 |


_mm256_sad_epu8

__m256i _mm256_sad_epu8( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: vpsadbw
CPUID Flag: AVX2
Category: Arithmetic

Description

Compute the absolute differences of packed unsigned 8-bit integers in "a" and "b", then horizontally sum each consecutive 8 differences to produce four unsigned 16-bit integers, and pack these unsigned 16-bit integers in the low 16 bits of 64-bit elements in "dst".

Operation

FOR j := 0 to 31
    i := j*8
    tmp[i+7:i] := ABS(a[i+7:i] - b[i+7:i])
ENDFOR
FOR j := 0 to 4
    i := j*64
    dst[i+15:i] := tmp[i+7:i] + tmp[i+15:i+8] + tmp[i+23:i+16] + tmp[i+31:i+24] + tmp[i+39:i+32] + tmp[i+47:i+40] + tmp[i+55:i+48] + tmp[i+63:i+56]
    dst[i+63:i+16] := 0
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 2 | 1
Haswell | 5 | 1 | 1
Broadwell | 5 | 1 | 1
Skylake | 3 | 1 | 1
Knights Landing | 16 | 9 | 5
Haswell | 5 | 1 |
Broadwell | 5 | 1 |
Skylake | 3 | 1 |


_mm256_set_epi16

__m256i _mm256_set_epi16( short e15, short e14, short e13, short e12, short e11, short e10, short e9, short e8, short e7, short e6, short e5, short e4, short e3, short e2, short e1, short e0 )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Set

Description

Set packed 16-bit integers in "dst" with the supplied values.

Operation

dst[15:0] := e0
dst[31:16] := e1
dst[47:32] := e2
dst[63:48] := e3
dst[79:64] := e4
dst[95:80] := e5
dst[111:96] := e6
dst[127:112] := e7
dst[143:128] := e8
dst[159:144] := e9
dst[175:160] := e10
dst[191:176] := e11
dst[207:192] := e12
dst[223:208] := e13
dst[239:224] := e14
dst[255:240] := e15
dst[MAX:256] := 0


_mm256_set_epi32

__m256i _mm256_set_epi32( int e7, int e6, int e5, int e4, int e3, int e2, int e1, int e0 )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Set

Description

Set packed 32-bit integers in "dst" with the supplied values.

Operation

dst[31:0] := e0
dst[63:32] := e1
dst[95:64] := e2
dst[127:96] := e3
dst[159:128] := e4
dst[191:160] := e5
dst[223:192] := e6
dst[255:224] := e7
dst[MAX:256] := 0


_mm256_set_epi64x

__m256i _mm256_set_epi64x( __int64 e3, __int64 e2, __int64 e1, __int64 e0 )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Set

Description

Set packed 64-bit integers in "dst" with the supplied values.

Operation

dst[63:0] := e0
dst[127:64] := e1
dst[191:128] := e2
dst[255:192] := e3
dst[MAX:256] := 0


_mm256_set_epi8

__m256i _mm256_set_epi8( char e31, char e30, char e29, char e28, char e27, char e26, char e25, char e24, char e23, char e22, char e21, char e20, char e19, char e18, char e17, char e16, char e15, char e14, char e13, char e12, char e11, char e10, char e9, char e8, char e7, char e6, char e5, char e4, char e3, char e2, char e1, char e0 )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Set

Description

Set packed 8-bit integers in "dst" with the supplied values in reverse order.

Operation

dst[7:0] := e0
dst[15:8] := e1
dst[23:16] := e2
dst[31:24] := e3
dst[39:32] := e4
dst[47:40] := e5
dst[55:48] := e6
dst[63:56] := e7
dst[71:64] := e8
dst[79:72] := e9
dst[87:80] := e10
dst[95:88] := e11
dst[103:96] := e12
dst[111:104] := e13
dst[119:112] := e14
dst[127:120] := e15
dst[135:128] := e16
dst[143:136] := e17
dst[151:144] := e18
dst[159:152] := e19
dst[167:160] := e20
dst[175:168] := e21
dst[183:176] := e22
dst[191:184] := e23
dst[199:192] := e24
dst[207:200] := e25
dst[215:208] := e26
dst[223:216] := e27
dst[231:224] := e28
dst[239:232] := e29
dst[247:240] := e30
dst[255:248] := e31
dst[MAX:256] := 0


_mm256_set_m128

__m256 _mm256_set_m128( __m128 hi, __m128 lo )

Synopsis

#include "immintrin.h"
Instruction: vinsertf128
CPUID Flag: AVX
Category: Set

Description

Set packed __m256 vector "dst" with the supplied values.

Operation

dst[127:0] := lo[127:0]
dst[255:128] := hi[127:0]
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 2
Jaguar | 1 | 1 | 2
Sandy Bridge | 2 | 1 | 1
Ivy Bridge | 2 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 3 | 1 | 1
Knights Landing | 3-6 | 1 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 3 | 1 |


_mm256_set_m128d

__m256d _mm256_set_m128d( __m128d hi, __m128d lo )

Synopsis

#include "immintrin.h"
Instruction: vinsertf128
CPUID Flag: AVX
Category: Set

Description

Set packed __m256d vector "dst" with the supplied values.

Operation

dst[127:0] := lo[127:0]
dst[255:128] := hi[127:0]
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 2
Jaguar | 1 | 1 | 2
Sandy Bridge | 2 | 1 | 1
Ivy Bridge | 2 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 3 | 1 | 1
Knights Landing | 3-6 | 1 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 3 | 1 |


_mm256_set_m128i

__m256i _mm256_set_m128i( __m128i hi, __m128i lo )

Synopsis

#include "immintrin.h"
Instruction: vinsertf128
CPUID Flag: AVX
Category: Set

Description

Set packed __m256i vector "dst" with the supplied values.

Operation

dst[127:0] := lo[127:0]
dst[255:128] := hi[127:0]
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 2
Jaguar | 1 | 1 | 2
Sandy Bridge | 2 | 1 | 1
Ivy Bridge | 2 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 3 | 1 | 1
Knights Landing | 3-6 | 1 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 3 | 1 |


_mm256_set_pd

__m256d _mm256_set_pd( double e3, double e2, double e1, double e0 )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Set

Description

Set packed double-precision (64-bit) floating-point elements in "dst" with the supplied values.

Operation

dst[63:0] := e0
dst[127:64] := e1
dst[191:128] := e2
dst[255:192] := e3
dst[MAX:256] := 0


_mm256_set_ps

__m256 _mm256_set_ps( float e7, float e6, float e5, float e4, float e3, float e2, float e1, float e0 )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Set

Description

Set packed single-precision (32-bit) floating-point elements in "dst" with the supplied values.

Operation

dst[31:0] := e0
dst[63:32] := e1
dst[95:64] := e2
dst[127:96] := e3
dst[159:128] := e4
dst[191:160] := e5
dst[223:192] := e6
dst[255:224] := e7
dst[MAX:256] := 0


_mm256_set1_epi16

__m256i _mm256_set1_epi16( short a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Set

Description

Broadcast 16-bit integer "a" to all all elements of "dst". This intrinsic may generate the "vpbroadcastw".

Operation

FOR j := 0 to 15
    i := j*16
    dst[i+15:i] := a[15:0]
ENDFOR
dst[MAX:256] := 0


_mm256_set1_epi32

__m256i _mm256_set1_epi32( int a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Set

Description

Broadcast 32-bit integer "a" to all elements of "dst". This intrinsic may generate the "vpbroadcastd".

Operation

FOR j := 0 to 7
    i := j*32
    dst[i+31:i] := a[31:0]
ENDFOR
dst[MAX:256] := 0


_mm256_set1_epi64x

__m256i _mm256_set1_epi64x( long long a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Set

Description

Broadcast 64-bit integer "a" to all elements of "dst". This intrinsic may generate the "vpbroadcastq".

Operation

FOR j := 0 to 3
    i := j*64
    dst[i+63:i] := a[63:0]
ENDFOR
dst[MAX:256] := 0


_mm256_set1_epi8

__m256i _mm256_set1_epi8( char a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Set

Description

Broadcast 8-bit integer "a" to all elements of "dst". This intrinsic may generate the "vpbroadcastb".

Operation

FOR j := 0 to 31
    i := j*8
    dst[i+7:i] := a[7:0]
ENDFOR
dst[MAX:256] := 0


_mm256_set1_pd

__m256d _mm256_set1_pd( double a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Set

Description

Broadcast double-precision (64-bit) floating-point value "a" to all elements of "dst".

Operation

FOR j := 0 to 3
    i := j*64
    dst[i+63:i] := a[63:0]
ENDFOR
dst[MAX:256] := 0


_mm256_set1_ps

__m256 _mm256_set1_ps( float a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Set

Description

Broadcast single-precision (32-bit) floating-point value "a" to all elements of "dst".

Operation

FOR j := 0 to 7
    i := j*32
    dst[i+31:i] := a[31:0]
ENDFOR
dst[MAX:256] := 0


_mm256_setr_epi16

__m256i _mm256_setr_epi16( short e15, short e14, short e13, short e12, short e11, short e10, short e9, short e8, short e7, short e6, short e5, short e4, short e3, short e2, short e1, short e0 )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Set

Description

Set packed 16-bit integers in "dst" with the supplied values in reverse order.

Operation

dst[15:0] := e15
dst[31:16] := e14
dst[47:32] := e13
dst[63:48] := e12
dst[79:64] := e11
dst[95:80] := e10
dst[111:96] := e9
dst[127:112] := e8
dst[143:128] := e7
dst[159:144] := e6
dst[175:160] := e5
dst[191:176] := e4
dst[207:192] := e3
dst[223:208] := e2
dst[239:224] := e1
dst[255:240] := e0
dst[MAX:256] := 0


_mm256_setr_epi32

__m256i _mm256_setr_epi32( int e7, int e6, int e5, int e4, int e3, int e2, int e1, int e0 )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Set

Description

Set packed 32-bit integers in "dst" with the supplied values in reverse order.

Operation

dst[31:0] := e7
dst[63:32] := e6
dst[95:64] := e5
dst[127:96] := e4
dst[159:128] := e3
dst[191:160] := e2
dst[223:192] := e1
dst[255:224] := e0
dst[MAX:256] := 0


_mm256_setr_epi64x

__m256i _mm256_setr_epi64x( __int64 e3, __int64 e2, __int64 e1, __int64 e0 )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Set

Description

Set packed 64-bit integers in "dst" with the supplied values in reverse order.

Operation

dst[63:0] := e3
dst[127:64] := e2
dst[191:128] := e1
dst[255:192] := e0
dst[MAX:256] := 0


_mm256_setr_epi8

__m256i _mm256_setr_epi8( char e31, char e30, char e29, char e28, char e27, char e26, char e25, char e24, char e23, char e22, char e21, char e20, char e19, char e18, char e17, char e16, char e15, char e14, char e13, char e12, char e11, char e10, char e9, char e8, char e7, char e6, char e5, char e4, char e3, char e2, char e1, char e0 )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Set

Description

Set packed 8-bit integers in "dst" with the supplied values in reverse order.

Operation

dst[7:0] := e31
dst[15:8] := e30
dst[23:16] := e29
dst[31:24] := e28
dst[39:32] := e27
dst[47:40] := e26
dst[55:48] := e25
dst[63:56] := e24
dst[71:64] := e23
dst[79:72] := e22
dst[87:80] := e21
dst[95:88] := e20
dst[103:96] := e19
dst[111:104] := e18
dst[119:112] := e17
dst[127:120] := e16
dst[135:128] := e15
dst[143:136] := e14
dst[151:144] := e13
dst[159:152] := e12
dst[167:160] := e11
dst[175:168] := e10
dst[183:176] := e9
dst[191:184] := e8
dst[199:192] := e7
dst[207:200] := e6
dst[215:208] := e5
dst[223:216] := e4
dst[231:224] := e3
dst[239:232] := e2
dst[247:240] := e1
dst[255:248] := e0
dst[MAX:256] := 0


_mm256_setr_m128

__m256 _mm256_setr_m128( __m128 lo, __m128 hi )

Synopsis

#include "immintrin.h"
Instruction: vinsertf128
CPUID Flag: AVX
Category: Set

Description

Set packed __m256 vector "dst" with the supplied values.

Operation

dst[127:0] := lo[127:0]
dst[255:128] := hi[127:0]
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 2
Jaguar | 1 | 1 | 2
Sandy Bridge | 2 | 1 | 1
Ivy Bridge | 2 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 3 | 1 | 1
Knights Landing | 3-6 | 1 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 3 | 1 |


_mm256_setr_m128d

__m256d _mm256_setr_m128d( __m128d lo, __m128d hi )

Synopsis

#include "immintrin.h"
Instruction: vinsertf128
CPUID Flag: AVX
Category: Set

Description

Set packed __m256d vector "dst" with the supplied values.

Operation

dst[127:0] := lo[127:0]
dst[255:128] := hi[127:0]
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 2
Jaguar | 1 | 1 | 2
Sandy Bridge | 2 | 1 | 1
Ivy Bridge | 2 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 3 | 1 | 1
Knights Landing | 3-6 | 1 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 3 | 1 |


_mm256_setr_m128i

__m256i _mm256_setr_m128i( __m128i lo, __m128i hi )

Synopsis

#include "immintrin.h"
Instruction: vinsertf128
CPUID Flag: AVX
Category: Set

Description

Set packed __m256i vector "dst" with the supplied values.

Operation

dst[127:0] := lo[127:0]
dst[255:128] := hi[127:0]
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 2
Jaguar | 1 | 1 | 2
Sandy Bridge | 2 | 1 | 1
Ivy Bridge | 2 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 3 | 1 | 1
Knights Landing | 3-6 | 1 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 3 | 1 |


_mm256_setr_pd

__m256d _mm256_setr_pd( double e3, double e2, double e1, double e0 )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Set

Description

Set packed double-precision (64-bit) floating-point elements in "dst" with the supplied values in reverse order.

Operation

dst[63:0] := e3
dst[127:64] := e2
dst[191:128] := e1
dst[255:192] := e0
dst[MAX:256] := 0


_mm256_setr_ps

__m256 _mm256_setr_ps( float e7, float e6, float e5, float e4, float e3, float e2, float e1, float e0 )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Set

Description

Set packed single-precision (32-bit) floating-point elements in "dst" with the supplied values in reverse order.

Operation

dst[31:0] := e7
dst[63:32] := e6
dst[95:64] := e5
dst[127:96] := e4
dst[159:128] := e3
dst[191:160] := e2
dst[223:192] := e1
dst[255:224] := e0
dst[MAX:256] := 0


_mm256_setzero_pd

__m256d _mm256_setzero_pd( void )

Synopsis

#include "immintrin.h"
Instruction: vxorpd
CPUID Flag: AVX
Category: Set

Description

Return vector of type __m256d with all elements set to zero.

Operation

dst[MAX:0] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 2
Sandy Bridge | 1 | 1 | 1
Ivy Bridge | 1 | 1 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 0.33 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 1 | 1 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 0.33 |


_mm256_setzero_ps

__m256 _mm256_setzero_ps( void )

Synopsis

#include "immintrin.h"
Instruction: vxorps
CPUID Flag: AVX
Category: Set

Description

Return vector of type __m256 with all elements set to zero.

Operation

dst[MAX:0] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 2
Sandy Bridge | 1 | 1 | 1
Ivy Bridge | 1 | 1 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 0.33 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 1 | 1 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 0.33 |


_mm256_setzero_si256

__m256i _mm256_setzero_si256( void )

Synopsis

#include "immintrin.h"
Instruction: vpxor
CPUID Flag: AVX
Category: Set

Description

Return vector of type __m256i with all elements set to zero.

Operation

dst[MAX:0] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 2
Haswell | 1 | 0.33 | 1
Broadwell | 1 | 0.33 | 1
Skylake | 1 | 0.33 | 1
Knights Landing | 2 | 0.5 | 1


_mm256_shuffle_epi32

__m256i _mm256_shuffle_epi32( __m256i a, const int imm8 )

Synopsis

#include "immintrin.h"
Instruction: vpshufd
CPUID Flag: AVX2
Category: Swizzle

Description

Shuffle 32-bit integers in "a" within 128-bit lanes using the control in "imm8", and store the results in "dst".

Operation

DEFINE SELECT4(src, control) {
    CASE(control[1:0]) OF
    0:	tmp[31:0] := src[31:0]
    1:	tmp[31:0] := src[63:32]
    2:	tmp[31:0] := src[95:64]
    3:	tmp[31:0] := src[127:96]
    ESAC
    RETURN tmp[31:0]
}
dst[31:0] := SELECT4(a[127:0], imm8[1:0])
dst[63:32] := SELECT4(a[127:0], imm8[3:2])
dst[95:64] := SELECT4(a[127:0], imm8[5:4])
dst[127:96] := SELECT4(a[127:0], imm8[7:6])
dst[159:128] := SELECT4(a[255:128], imm8[1:0])
dst[191:160] := SELECT4(a[255:128], imm8[3:2])
dst[223:192] := SELECT4(a[255:128], imm8[5:4])
dst[255:224] := SELECT4(a[255:128], imm8[7:6])
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 1 | 2
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 3-6 | 1 | 1
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm256_shuffle_epi8

__m256i _mm256_shuffle_epi8( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: vpshufb
CPUID Flag: AVX2
Category: Swizzle

Description

Shuffle 8-bit integers in "a" within 128-bit lanes according to shuffle control mask in the corresponding 8-bit element of "b", and store the results in "dst".

Operation

FOR j := 0 to 15
    i := j*8
    IF b[i+7] == 1
        dst[i+7:i] := 0
    ELSE
        index[3:0] := b[i+3:i]
        dst[i+7:i] := a[index*8+7:index*8]
    FI
    IF b[128+i+7] == 1
        dst[128+i+7:128+i] := 0
    ELSE
        index[3:0] := b[128+i+3:128+i]
        dst[128+i+7:128+i] := a[128+index*8+7:128+index*8]
    FI
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 1 | 2
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 23-25 | 12 | 12
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm256_shuffle_pd

__m256d _mm256_shuffle_pd( __m256d a, __m256d b, const int imm8 )

Synopsis

#include "immintrin.h"
Instruction: vshufpd
CPUID Flag: AVX
Category: Swizzle

Description

Shuffle double-precision (64-bit) floating-point elements within 128-bit lanes using the control in "imm8", and store the results in "dst".

Operation

dst[63:0] := (imm8[0] == 0) ? a[63:0] : a[127:64]
dst[127:64] := (imm8[1] == 0) ? b[63:0] : b[127:64]
dst[191:128] := (imm8[2] == 0) ? a[191:128] : a[255:192]
dst[255:192] := (imm8[3] == 0) ? b[191:128] : b[255:192]
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 1 | 2
Jaguar | 2 | 1 | 2
Sandy Bridge | 1 | 1 | 1
Ivy Bridge | 1 | 1 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 4-7 | 2 | 1
Ivy Bridge | 1 | 1 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm256_shuffle_ps

__m256 _mm256_shuffle_ps( __m256 a, __m256 b, const int imm8 )

Synopsis

#include "immintrin.h"
Instruction: vshufps
CPUID Flag: AVX
Category: Swizzle

Description

Shuffle single-precision (32-bit) floating-point elements in "a" within 128-bit lanes using the control in "imm8", and store the results in "dst".

Operation

DEFINE SELECT4(src, control) {
    CASE(control[1:0]) OF
    0:	tmp[31:0] := src[31:0]
    1:	tmp[31:0] := src[63:32]
    2:	tmp[31:0] := src[95:64]
    3:	tmp[31:0] := src[127:96]
    ESAC
    RETURN tmp[31:0]
}
dst[31:0] := SELECT4(a[127:0], imm8[1:0])
dst[63:32] := SELECT4(a[127:0], imm8[3:2])
dst[95:64] := SELECT4(b[127:0], imm8[5:4])
dst[127:96] := SELECT4(b[127:0], imm8[7:6])
dst[159:128] := SELECT4(a[255:128], imm8[1:0])
dst[191:160] := SELECT4(a[255:128], imm8[3:2])
dst[223:192] := SELECT4(b[255:128], imm8[5:4])
dst[255:224] := SELECT4(b[255:128], imm8[7:6])
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 1 | 2
Jaguar | 2 | 1 | 2
Sandy Bridge | 1 | 1 | 1
Ivy Bridge | 1 | 1 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 4-7 | 2 | 1
Ivy Bridge | 1 | 1 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm256_shufflehi_epi16

__m256i _mm256_shufflehi_epi16( __m256i a, const int imm8 )

Synopsis

#include "immintrin.h"
Instruction: vpshufhw
CPUID Flag: AVX2
Category: Swizzle

Description

Shuffle 16-bit integers in the high 64 bits of 128-bit lanes of "a" using the control in "imm8". Store the results in the high 64 bits of 128-bit lanes of "dst", with the low 64 bits of 128-bit lanes being copied from from "a" to "dst".

Operation

dst[63:0] := a[63:0]
dst[79:64] := (a >> (imm8[1:0] * 16))[79:64]
dst[95:80] := (a >> (imm8[3:2] * 16))[79:64]
dst[111:96] := (a >> (imm8[5:4] * 16))[79:64]
dst[127:112] := (a >> (imm8[7:6] * 16))[79:64]
dst[191:128] := a[191:128]
dst[207:192] := (a >> (imm8[1:0] * 16))[207:192]
dst[223:208] := (a >> (imm8[3:2] * 16))[207:192]
dst[239:224] := (a >> (imm8[5:4] * 16))[207:192]
dst[255:240] := (a >> (imm8[7:6] * 16))[207:192]
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 1 | 2
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 11-14 | 8 | 4
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm256_shufflelo_epi16

__m256i _mm256_shufflelo_epi16( __m256i a, const int imm8 )

Synopsis

#include "immintrin.h"
Instruction: vpshuflw
CPUID Flag: AVX2
Category: Swizzle

Description

Shuffle 16-bit integers in the low 64 bits of 128-bit lanes of "a" using the control in "imm8". Store the results in the low 64 bits of 128-bit lanes of "dst", with the high 64 bits of 128-bit lanes being copied from from "a" to "dst".

Operation

dst[15:0] := (a >> (imm8[1:0] * 16))[15:0]
dst[31:16] := (a >> (imm8[3:2] * 16))[15:0]
dst[47:32] := (a >> (imm8[5:4] * 16))[15:0]
dst[63:48] := (a >> (imm8[7:6] * 16))[15:0]
dst[127:64] := a[127:64]
dst[143:128] := (a >> (imm8[1:0] * 16))[143:128]
dst[159:144] := (a >> (imm8[3:2] * 16))[143:128]
dst[175:160] := (a >> (imm8[5:4] * 16))[143:128]
dst[191:176] := (a >> (imm8[7:6] * 16))[143:128]
dst[255:192] := a[255:192]
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 1 | 2
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 11-14 | 8 | 4
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm256_sign_epi16

__m256i _mm256_sign_epi16( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: vpsignw
CPUID Flag: AVX2
Category: Arithmetic

Description

Negate packed 16-bit integers in "a" when the corresponding signed 16-bit integer in "b" is negative, and store the results in "dst". Element in "dst" are zeroed out when the corresponding element in "b" is zero.

Operation

FOR j := 0 to 15
    i := j*16
    IF b[i+15:i] < 0
        dst[i+15:i] := -(a[i+15:i])
    ELSE IF b[i+15:i] == 0
        dst[i+15:i] := 0
    ELSE
        dst[i+15:i] := a[i+15:i]
    FI
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 1 | 2
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.5 |


_mm256_sign_epi32

__m256i _mm256_sign_epi32( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: vpsignd
CPUID Flag: AVX2
Category: Arithmetic

Description

Negate packed 32-bit integers in "a" when the corresponding signed 32-bit integer in "b" is negative, and store the results in "dst". Element in "dst" are zeroed out when the corresponding element in "b" is zero.

Operation

FOR j := 0 to 7
    i := j*32
    IF b[i+31:i] < 0
        dst[i+31:i] := -(a[i+31:i])
    ELSE IF b[i+31:i] == 0
        dst[i+31:i] := 0
    ELSE
        dst[i+31:i] := a[i+31:i]
    FI
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 1 | 2
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.5 |


_mm256_sign_epi8

__m256i _mm256_sign_epi8( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: vpsignb
CPUID Flag: AVX2
Category: Arithmetic

Description

Negate packed 8-bit integers in "a" when the corresponding signed 8-bit integer in "b" is negative, and store the results in "dst". Element in "dst" are zeroed out when the corresponding element in "b" is zero.

Operation

FOR j := 0 to 31
    i := j*8
    IF b[i+7:i] < 0
        dst[i+7:i] := -(a[i+7:i])
    ELSE IF b[i+7:i] == 0
        dst[i+7:i] := 0
    ELSE
        dst[i+7:i] := a[i+7:i]
    FI
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 1 | 2
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.5 | 1
Knights Landing | 2 | 0.5 | 1
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.5 |


_mm256_sin_pd

__m256d _mm256_sin_pd( __m256d a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Trigonometry

Description

Compute the sine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*64
    dst[i+63:i] := SIN(a[i+63:i])
ENDFOR
dst[MAX:256] := 0


_mm256_sin_ps

__m256 _mm256_sin_ps( __m256 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Trigonometry

Description

Compute the sine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*32
    dst[i+31:i] := SIN(a[i+31:i])
ENDFOR
dst[MAX:256] := 0


_mm256_sincos_pd

__m256d _mm256_sincos_pd( __m256d * mem_addr, __m256d a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Trigonometry

Description

Compute the sine and cosine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, store the sine in "dst", and store the cosine into memory at "mem_addr".

Operation

FOR j := 0 to 3
    i := j*64
    dst[i+63:i] := SIN(a[i+63:i])
    MEM[mem_addr+i+63:mem_addr+i] := COS(a[i+63:i])
ENDFOR
dst[MAX:256] := 0


_mm256_sincos_ps

__m256 _mm256_sincos_ps( __m256 * mem_addr, __m256 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Trigonometry

Description

Compute the sine and cosine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, store the sine in "dst", and store the cosine into memory at "mem_addr".

Operation

FOR j := 0 to 7
    i := j*32
    dst[i+31:i] := SIN(a[i+31:i])
    MEM[mem_addr+i+31:mem_addr+i] := COS(a[i+31:i])
ENDFOR
dst[MAX:256] := 0


_mm256_sind_pd

__m256d _mm256_sind_pd( __m256d a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Trigonometry

Description

Compute the sine of packed double-precision (64-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*64
    dst[i+63:i] := SIND(a[i+63:i])
ENDFOR
dst[MAX:256] := 0


_mm256_sind_ps

__m256 _mm256_sind_ps( __m256 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Trigonometry

Description

Compute the sine of packed single-precision (32-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*32
    dst[i+31:i] := SIND(a[i+31:i])
ENDFOR
dst[MAX:256] := 0


_mm256_sinh_pd

__m256d _mm256_sinh_pd( __m256d a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Trigonometry

Description

Compute the hyperbolic sine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*64
    dst[i+63:i] := SINH(a[i+63:i])
ENDFOR
dst[MAX:256] := 0


_mm256_sinh_ps

__m256 _mm256_sinh_ps( __m256 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Trigonometry

Description

Compute the hyperbolic sine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*32
    dst[i+31:i] := SINH(a[i+31:i])
ENDFOR
dst[MAX:256] := 0


_mm256_sll_epi16

__m256i _mm256_sll_epi16( __m256i a, __m128i count )

Synopsis

#include "immintrin.h"
Instruction: vpsllw
CPUID Flag: AVX2
Category: Shift

Description

Shift packed 16-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst".

Operation

FOR j := 0 to 15
    i := j*16
    IF count[63:0] > 15
        dst[i+15:i] := 0
    ELSE
        dst[i+15:i] := ZeroExtend(a[i+15:i] << count[63:0])
    FI
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 2 | 2
Haswell | 2 | 1 | 2
Broadwell | 2 | 1 | 2
Skylake | 1 | 1 | 2
Knights Landing | 11 | 8 | 4
Haswell | 4 | 1 |
Broadwell | 4 | 1 |
Skylake | 4 | 1 |


_mm256_sll_epi32

__m256i _mm256_sll_epi32( __m256i a, __m128i count )

Synopsis

#include "immintrin.h"
Instruction: vpslld
CPUID Flag: AVX2
Category: Shift

Description

Shift packed 32-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*32
    IF count[63:0] > 31
        dst[i+31:i] := 0
    ELSE
        dst[i+31:i] := ZeroExtend(a[i+31:i] << count[63:0])
    FI
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 2 | 2
Haswell | 2 | 1 | 2
Broadwell | 2 | 1 | 2
Skylake | 1 | 1 | 2
Knights Landing | 11 | 8 | 4
Haswell | 4 | 1 |
Broadwell | 4 | 1 |
Skylake | 4 | 1 |


_mm256_sll_epi64

__m256i _mm256_sll_epi64( __m256i a, __m128i count )

Synopsis

#include "immintrin.h"
Instruction: vpsllq
CPUID Flag: AVX2
Category: Shift

Description

Shift packed 64-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*64
    IF count[63:0] > 63
        dst[i+63:i] := 0
    ELSE
        dst[i+63:i] := ZeroExtend(a[i+63:i] << count[63:0])
    FI
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 2 | 2
Haswell | 2 | 1 | 2
Broadwell | 2 | 1 | 2
Skylake | 1 | 1 | 2
Knights Landing | 11 | 8 | 4
Haswell | 4 | 1 |
Broadwell | 4 | 1 |
Skylake | 4 | 1 |


_mm256_slli_epi16

__m256i _mm256_slli_epi16( __m256i a, int imm8 )

Synopsis

#include "immintrin.h"
Instruction: vpsllw
CPUID Flag: AVX2
Category: Shift

Description

Shift packed 16-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst".

Operation

FOR j := 0 to 15
    i := j*16
    IF imm8[7:0] > 15
        dst[i+15:i] := 0
    ELSE
        dst[i+15:i] := ZeroExtend(a[i+15:i] << imm8[7:0])
    FI
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 2 | 2
Haswell | 2 | 1 | 2
Broadwell | 2 | 1 | 2
Skylake | 1 | 1 | 2
Knights Landing | 11 | 8 | 4
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm256_slli_epi32

__m256i _mm256_slli_epi32( __m256i a, int imm8 )

Synopsis

#include "immintrin.h"
Instruction: vpslld
CPUID Flag: AVX2
Category: Shift

Description

Shift packed 32-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*32
    IF imm8[7:0] > 31
        dst[i+31:i] := 0
    ELSE
        dst[i+31:i] := ZeroExtend(a[i+31:i] << imm8[7:0])
    FI
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 2 | 2
Haswell | 2 | 1 | 2
Broadwell | 2 | 1 | 2
Skylake | 1 | 1 | 2
Knights Landing | 11 | 8 | 4
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm256_slli_epi64

__m256i _mm256_slli_epi64( __m256i a, int imm8 )

Synopsis

#include "immintrin.h"
Instruction: vpsllq
CPUID Flag: AVX2
Category: Shift

Description

Shift packed 64-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*64
    IF imm8[7:0] > 63
        dst[i+63:i] := 0
    ELSE
        dst[i+63:i] := ZeroExtend(a[i+63:i] << imm8[7:0])
    FI
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 2 | 2
Haswell | 2 | 1 | 2
Broadwell | 2 | 1 | 2
Skylake | 1 | 1 | 2
Knights Landing | 11 | 8 | 4
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm256_slli_si256

__m256i _mm256_slli_si256( __m256i a, const int imm8 )

Synopsis

#include "immintrin.h"
Instruction: vpslldq
CPUID Flag: AVX2
Category: Shift

Description

Shift 128-bit lanes in "a" left by "imm8" bytes while shifting in zeros, and store the results in "dst".

Operation

tmp := imm8[7:0]
IF tmp > 15
    tmp := 16
FI
dst[127:0] := a[127:0] << (tmp*8)
dst[255:128] := a[255:128] << (tmp*8)
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 1 | 2
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm256_sllv_epi32

__m256i _mm256_sllv_epi32( __m256i a, __m256i count )

Synopsis

#include "immintrin.h"
Instruction: vpsllvd
CPUID Flag: AVX2
Category: Shift

Description

Shift packed 32-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*32
    dst[i+31:i] := ZeroExtend(a[i+31:i] << count[i+31:i])
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 2 | 1
Haswell | 2 | 2 | 3
Broadwell | 2 | 2 | 3
Skylake | 1 | 0.5 | 1
Knights Landing | 2 | 1 | 1
Haswell | 2 | 2 |
Broadwell | 2 | 2 |
Skylake | 2 | 0.5 |


_mm256_sllv_epi64

__m256i _mm256_sllv_epi64( __m256i a, __m256i count )

Synopsis

#include "immintrin.h"
Instruction: vpsllvq
CPUID Flag: AVX2
Category: Shift

Description

Shift packed 64-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*64
    dst[i+63:i] := ZeroExtend(a[i+63:i] << count[i+63:i])
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 2 | 1
Haswell | 2 | 2 | 3
Broadwell | 2 | 2 | 3
Skylake | 1 | 0.5 | 1
Knights Landing | 2 | 1 | 1
Haswell | 2 | 2 |
Broadwell | 2 | 2 |
Skylake | 2 | 0.5 |


_mm256_sqrt_pd

__m256d _mm256_sqrt_pd( __m256d a )

Synopsis

#include "immintrin.h"
Instruction: vsqrtpd
CPUID Flag: AVX
Category: Elementary Math Functions

Description

Compute the square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*64
    dst[i+63:i] := SQRT(a[i+63:i])
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 14-15 | 8-16 | 2
Jaguar | 54 | 54 | 2
Sandy Bridge | 21-43 | 21-43 | 3
Ivy Bridge | 28 | 16-28 | 3
Haswell | 28-29 | 16-28 | 3
Broadwell | 27-29 | 16-28 | 3
Skylake | 15-16 | 9-12 | 1
Knights Landing | 37 | 16 | 18
Ivy Bridge | 19-35 | 28 |
Haswell | 19-35 | 16-27 |
Broadwell | 19-35 | 16-27 |
Skylake | <18 | <12 |
Knights Landing | 38 | ~10 |


_mm256_sqrt_ps

__m256 _mm256_sqrt_ps( __m256 a )

Synopsis

#include "immintrin.h"
Instruction: vsqrtps
CPUID Flag: AVX
Category: Elementary Math Functions

Description

Compute the square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*32
    dst[i+31:i] := SQRT(a[i+31:i])
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 9-10 | 8-10 | 2
Jaguar | 42 | 42 | 2
Sandy Bridge |  | 21-28 | 3
Ivy Bridge | 19 | 14 | 3
Haswell | 19 | 14 | 3
Broadwell | 19 | 14 | 3
Skylake | 12 | 6 | 1
Knights Landing | 38 | 16 | 18
Ivy Bridge | 18-21 | 14 |
Haswell | 18-21 | 13 |
Broadwell | 18-21 | 13 |
Skylake | 12 | <6 |
Knights Landing | 38 | ~10 |


_mm256_sra_epi16

__m256i _mm256_sra_epi16( __m256i a, __m128i count )

Synopsis

#include "immintrin.h"
Instruction: vpsraw
CPUID Flag: AVX2
Category: Shift

Description

Shift packed 16-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst".

Operation

FOR j := 0 to 15
    i := j*16
    IF count[63:0] > 15
        dst[i+15:i] := SignBit
    ELSE
        dst[i+15:i] := SignExtend(a[i+15:i] >> count[63:0])
    FI
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 2 | 2
Haswell | 2 | 1 | 2
Broadwell | 2 | 1 | 2
Skylake | 1 | 1 | 2
Knights Landing | 11 | 8 | 4
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm256_sra_epi32

__m256i _mm256_sra_epi32( __m256i a, __m128i count )

Synopsis

#include "immintrin.h"
Instruction: vpsrad
CPUID Flag: AVX2
Category: Shift

Description

Shift packed 32-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*32
    IF count[63:0] > 31
        dst[i+31:i] := SignBit
    ELSE
        dst[i+31:i] := SignExtend(a[i+31:i] >> count[63:0])
    FI
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 2 | 2
Haswell | 2 | 1 | 2
Broadwell | 2 | 1 | 2
Skylake | 1 | 1 | 2
Knights Landing | 11 | 8 | 4
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm256_srai_epi16

__m256i _mm256_srai_epi16( __m256i a, int imm8 )

Synopsis

#include "immintrin.h"
Instruction: vpsraw
CPUID Flag: AVX2
Category: Shift

Description

Shift packed 16-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst".

Operation

FOR j := 0 to 15
    i := j*16
    IF imm8[7:0] > 15
        dst[i+15:i] := SignBit
    ELSE
        dst[i+15:i] := SignExtend(a[i+15:i] >> imm8[7:0])
    FI
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 2 | 2
Haswell | 2 | 1 | 2
Broadwell | 2 | 1 | 2
Skylake | 1 | 1 | 2
Knights Landing | 11 | 8 | 4
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm256_srai_epi32

__m256i _mm256_srai_epi32( __m256i a, int imm8 )

Synopsis

#include "immintrin.h"
Instruction: vpsrad
CPUID Flag: AVX2
Category: Shift

Description

Shift packed 32-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*32
    IF imm8[7:0] > 31
        dst[i+31:i] := SignBit
    ELSE
        dst[i+31:i] := SignExtend(a[i+31:i] >> imm8[7:0])
    FI
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 2 | 2
Haswell | 2 | 1 | 2
Broadwell | 2 | 1 | 2
Skylake | 1 | 1 | 2
Knights Landing | 11 | 8 | 4
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm256_srav_epi32

__m256i _mm256_srav_epi32( __m256i a, __m256i count )

Synopsis

#include "immintrin.h"
Instruction: vpsravd
CPUID Flag: AVX2
Category: Shift

Description

Shift packed 32-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*32
    dst[i+31:i] := SignExtend(a[i+31:i] >> count[i+31:i])
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 2 | 1
Haswell | 2 | 2 | 3
Broadwell | 2 | 2 | 3
Skylake | 1 | 0.5 | 1
Knights Landing | 2 | 1 | 1
Haswell | 2 | 2 |
Broadwell | 2 | 2 |
Skylake | 2 | 0.5 |


_mm256_srl_epi16

__m256i _mm256_srl_epi16( __m256i a, __m128i count )

Synopsis

#include "immintrin.h"
Instruction: vpsrlw
CPUID Flag: AVX2
Category: Shift

Description

Shift packed 16-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst".

Operation

FOR j := 0 to 15
    i := j*16
    IF count[63:0] > 15
        dst[i+15:i] := 0
    ELSE
        dst[i+15:i] := ZeroExtend(a[i+15:i] >> count[63:0])
    FI
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 2 | 2
Haswell | 2 | 1 | 2
Broadwell | 2 | 1 | 2
Skylake | 1 | 1 | 2
Knights Landing | 11 | 8 | 4


_mm256_srl_epi32

__m256i _mm256_srl_epi32( __m256i a, __m128i count )

Synopsis

#include "immintrin.h"
Instruction: vpsrld
CPUID Flag: AVX2
Category: Shift

Description

Shift packed 32-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*32
    IF count[63:0] > 31
        dst[i+31:i] := 0
    ELSE
        dst[i+31:i] := ZeroExtend(a[i+31:i] >> count[63:0])
    FI
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 2 | 2
Haswell | 2 | 1 | 2
Broadwell | 2 | 1 | 2
Skylake | 1 | 1 | 2
Knights Landing | 11 | 8 | 4


_mm256_srl_epi64

__m256i _mm256_srl_epi64( __m256i a, __m128i count )

Synopsis

#include "immintrin.h"
Instruction: vpsrlq
CPUID Flag: AVX2
Category: Shift

Description

Shift packed 64-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*64
    IF count[63:0] > 63
        dst[i+63:i] := 0
    ELSE
        dst[i+63:i] := ZeroExtend(a[i+63:i] >> count[63:0])
    FI
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 2 | 2
Haswell | 2 | 1 | 2
Broadwell | 2 | 1 | 2
Skylake | 1 | 1 | 2
Knights Landing | 11 | 8 | 4


_mm256_srli_epi16

__m256i _mm256_srli_epi16( __m256i a, int imm8 )

Synopsis

#include "immintrin.h"
Instruction: vpsrlw
CPUID Flag: AVX2
Category: Shift

Description

Shift packed 16-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst".

Operation

FOR j := 0 to 15
    i := j*16
    IF imm8[7:0] > 15
        dst[i+15:i] := 0
    ELSE
        dst[i+15:i] := ZeroExtend(a[i+15:i] >> imm8[7:0])
    FI
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 2 | 2
Haswell | 2 | 1 | 2
Broadwell | 2 | 1 | 2
Skylake | 1 | 1 | 2
Knights Landing | 11 | 8 | 4


_mm256_srli_epi32

__m256i _mm256_srli_epi32( __m256i a, int imm8 )

Synopsis

#include "immintrin.h"
Instruction: vpsrld
CPUID Flag: AVX2
Category: Shift

Description

Shift packed 32-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*32
    IF imm8[7:0] > 31
        dst[i+31:i] := 0
    ELSE
        dst[i+31:i] := ZeroExtend(a[i+31:i] >> imm8[7:0])
    FI
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 2 | 2
Haswell | 2 | 1 | 2
Broadwell | 2 | 1 | 2
Skylake | 1 | 1 | 2
Knights Landing | 11 | 8 | 4


_mm256_srli_epi64

__m256i _mm256_srli_epi64( __m256i a, int imm8 )

Synopsis

#include "immintrin.h"
Instruction: vpsrlq
CPUID Flag: AVX2
Category: Shift

Description

Shift packed 64-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*64
    IF imm8[7:0] > 63
        dst[i+63:i] := 0
    ELSE
        dst[i+63:i] := ZeroExtend(a[i+63:i] >> imm8[7:0])
    FI
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 2 | 2
Haswell | 2 | 1 | 2
Broadwell | 2 | 1 | 2
Skylake | 1 | 1 | 2
Knights Landing | 11 | 8 | 4


_mm256_srli_si256

__m256i _mm256_srli_si256( __m256i a, const int imm8 )

Synopsis

#include "immintrin.h"
Instruction: vpsrldq
CPUID Flag: AVX2
Category: Shift

Description

Shift 128-bit lanes in "a" right by "imm8" bytes while shifting in zeros, and store the results in "dst".

Operation

tmp := imm8[7:0]
IF tmp > 15
    tmp := 16
FI
dst[127:0] := a[127:0] >> (tmp*8)
dst[255:128] := a[255:128] >> (tmp*8)
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 1 | 2
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1


_mm256_srlv_epi32

__m256i _mm256_srlv_epi32( __m256i a, __m256i count )

Synopsis

#include "immintrin.h"
Instruction: vpsrlvd
CPUID Flag: AVX2
Category: Shift

Description

Shift packed 32-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*32
    dst[i+31:i] := ZeroExtend(a[i+31:i] >> count[i+31:i])
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 2 | 1
Haswell | 2 | 2 | 3
Broadwell | 2 | 2 | 3
Skylake | 1 | 0.5 | 1
Knights Landing | 2 | 1 | 1


_mm256_srlv_epi64

__m256i _mm256_srlv_epi64( __m256i a, __m256i count )

Synopsis

#include "immintrin.h"
Instruction: vpsrlvq
CPUID Flag: AVX2
Category: Shift

Description

Shift packed 64-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*64
    dst[i+63:i] := ZeroExtend(a[i+63:i] >> count[i+63:i])
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 2 | 1
Haswell | 2 | 2 | 3
Broadwell | 2 | 2 | 3
Skylake | 1 | 0.5 | 1
Knights Landing | 2 | 1 | 1


_mm256_store_pd

void _mm256_store_pd( double * mem_addr, __m256d a )

Synopsis

#include "immintrin.h"
Instruction: vmovapd
CPUID Flag: AVX
Category: Store

Description

Store 256-bits (composed of 4 packed double-precision (64-bit) floating-point elements) from "a" into memory. "mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.

Operation

MEM[mem_addr+255:mem_addr] := a[255:0]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 2
Jaguar | 1 | 1 | 2
Sandy Bridge | 1 | 1 | 1
Ivy Bridge | 0-1 | ≤1 | 1
Haswell | 0-1 | 1 | 1
Broadwell | 0-1 | 1 | 1
Skylake | 0-1 | 0.25 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 1 | 1 |
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.25 |


_mm256_store_ps

void _mm256_store_ps( float * mem_addr, __m256 a )

Synopsis

#include "immintrin.h"
Instruction: vmovaps
CPUID Flag: AVX
Category: Store

Description

Store 256-bits (composed of 8 packed single-precision (32-bit) floating-point elements) from "a" into memory. "mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.

Operation

MEM[mem_addr+255:mem_addr] := a[255:0]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 2
Jaguar | 1 | 1 | 2
Sandy Bridge | 1 | 1 | 1
Ivy Bridge | 0-1 | ≤1 | 1
Haswell | 0-1 | 1 | 1
Broadwell | 0-1 | 1 | 1
Skylake | 0-1 | 0.25 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 1 | 1 |
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.25 |


_mm256_store_si256

void _mm256_store_si256( __m256i * mem_addr, __m256i a )

Synopsis

#include "immintrin.h"
Instruction: vmovdqa
CPUID Flag: AVX
Category: Store

Description

Store 256-bits of integer data from "a" into memory. "mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.

Operation

MEM[mem_addr+255:mem_addr] := a[255:0]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 2
Jaguar | 1 | 1 | 2
Haswell | 0-1 | 0.33 | 1
Broadwell | 0-1 | 0.25 | 1
Skylake | 0-1 | 0.25 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 0.25 |
Broadwell | 1 | 0.25 |
Skylake | 1 | 0.25 |


_mm256_storeu_pd

void _mm256_storeu_pd( double * mem_addr, __m256d a )

Synopsis

#include "immintrin.h"
Instruction: vmovupd
CPUID Flag: AVX
Category: Store

Description

Store 256-bits (composed of 4 packed double-precision (64-bit) floating-point elements) from "a" into memory. "mem_addr" does not need to be aligned on any particular boundary.

Operation

MEM[mem_addr+255:mem_addr] := a[255:0]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 5 | 1 | 2
Jaguar | 1 | 1 | 2
Sandy Bridge | 4 | 1 | 1
Ivy Bridge | 4 | 1 | 1
Haswell | 3 | 0.5 | 1
Broadwell | 3 | 0.5 | 1
Skylake | 3 | 0.5 | 1
Knights Landing | 5 | 0.5 | 1
Ivy Bridge | 1 | 1 |
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.25 |


_mm256_storeu_ps

void _mm256_storeu_ps( float * mem_addr, __m256 a )

Synopsis

#include "immintrin.h"
Instruction: vmovups
CPUID Flag: AVX
Category: Store

Description

Store 256-bits (composed of 8 packed single-precision (32-bit) floating-point elements) from "a" into memory. "mem_addr" does not need to be aligned on any particular boundary.

Operation

MEM[mem_addr+255:mem_addr] := a[255:0]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 5 | 1 | 2
Jaguar | 1 | 1 | 2
Sandy Bridge | 4 | 1 | 1
Ivy Bridge | 4 | 1 | 1
Haswell | 3 | 0.5 | 1
Broadwell | 3 | 0.5 | 1
Skylake | 3 | 0.5 | 1
Knights Landing | 5 | 0.5 | 1
Ivy Bridge | 1 | 1 |
Haswell | 1 | 0.5 |
Broadwell | 1 | 0.5 |
Skylake | 1 | 0.25 |


_mm256_storeu_si256

void _mm256_storeu_si256( __m256i * mem_addr, __m256i a )

Synopsis

#include "immintrin.h"
Instruction: vmovdqu
CPUID Flag: AVX
Category: Store

Description

Store 256-bits of integer data from "a" into memory. "mem_addr" does not need to be aligned on any particular boundary.

Operation

MEM[mem_addr+255:mem_addr] := a[255:0]

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 1 | 2
Haswell | 0-1 | 0.33 | 1
Broadwell | 0-1 | 0.25 | 1
Skylake | 0-1 | 0.25 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 1 | 0.5 |
Haswell | 1 | 0.25 |
Broadwell | 1 | 0.25 |
Skylake | 1 | 0.25 |


_mm256_storeu2_m128

void _mm256_storeu2_m128( float* hiaddr, float* loaddr, __m256 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Store

Description

Store the high and low 128-bit halves (each composed of 4 packed single-precision (32-bit) floating-point elements) from "a" into memory two different 128-bit locations. "hiaddr" and "loaddr" do not need to be aligned on any particular boundary.

Operation

MEM[loaddr+127:loaddr] := a[127:0]
MEM[hiaddr+127:hiaddr] := a[255:128]


_mm256_storeu2_m128d

void _mm256_storeu2_m128d( double* hiaddr, double* loaddr, __m256d a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Store

Description

Store the high and low 128-bit halves (each composed of 2 packed double-precision (64-bit) floating-point elements) from "a" into memory two different 128-bit locations. "hiaddr" and "loaddr" do not need to be aligned on any particular boundary.

Operation

MEM[loaddr+127:loaddr] := a[127:0]
MEM[hiaddr+127:hiaddr] := a[255:128]


_mm256_storeu2_m128i

void _mm256_storeu2_m128i( __m128i* hiaddr, __m128i* loaddr, __m256i a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Store

Description

Store the high and low 128-bit halves (each composed of integer data) from "a" into memory two different 128-bit locations. "hiaddr" and "loaddr" do not need to be aligned on any particular boundary.

Operation

MEM[loaddr+127:loaddr] := a[127:0]
MEM[hiaddr+127:hiaddr] := a[255:128]


_mm256_stream_load_si256

__m256i _mm256_stream_load_si256( __m256i const* mem_addr )

Synopsis

#include "immintrin.h"
Instruction: vmovntdqa
CPUID Flag: AVX2
Category: Load

Description

Load 256-bits of integer data from memory into "dst" using a non-temporal memory hint. "mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.

Operation

dst[255:0] := MEM[mem_addr+255:mem_addr]
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Haswell | 3 | 0.5 | 1
Broadwell | 3 | 0.5 | 1
Skylake | 3 | 0.5 | 2
Knights Landing | 5 | 0.5 | 1


_mm256_stream_pd

void _mm256_stream_pd( double * mem_addr, __m256d a )

Synopsis

#include "immintrin.h"
Instruction: vmovntpd
CPUID Flag: AVX
Category: Store

Description

Store 256-bits (composed of 4 packed double-precision (64-bit) floating-point elements) from "a" into memory using a non-temporal memory hint. "mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.

Operation

MEM[mem_addr+255:mem_addr] := a[255:0]

Performance

Architecture | Latency | Throughput | μops
Ryzen | ~950 | 2 | 2
Sandy Bridge | ~300 | 25 | 1
Ivy Bridge | ~380 | 2 | 1
Haswell | ~400 | 1 | 1
Broadwell | ~400 | 1 | 1
Skylake | ~400 | 1 | 1
Knights Landing | ~500 |  | 1
Ivy Bridge |  | 1 |
Haswell |  | 1 |
Broadwell |  | 1 |
Skylake |  | 1 |


_mm256_stream_ps

void _mm256_stream_ps( float * mem_addr, __m256 a )

Synopsis

#include "immintrin.h"
Instruction: vmovntps
CPUID Flag: AVX
Category: Store

Description

Store 256-bits (composed of 8 packed single-precision (32-bit) floating-point elements) from "a" into memory using a non-temporal memory hint. "mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.

Operation

MEM[mem_addr+255:mem_addr] := a[255:0]

Performance

Architecture | Latency | Throughput | μops
Ryzen | ~950 | 2 | 2
Sandy Bridge | ~300 | 25 | 1
Ivy Bridge | ~380 | 2 | 1
Haswell | ~400 | 1 | 1
Broadwell | ~400 | 1 | 1
Skylake | ~400 | 1 | 1
Knights Landing | ~500 |  | 1
Ivy Bridge |  | 1 |
Haswell |  | 1 |
Broadwell |  | 1 |
Skylake |  | 1 |


_mm256_stream_si256

void _mm256_stream_si256( __m256i * mem_addr, __m256i a )

Synopsis

#include "immintrin.h"
Instruction: vmovntdq
CPUID Flag: AVX
Category: Store

Description

Store 256-bits of integer data from "a" into memory using a non-temporal memory hint. "mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.

Operation

MEM[mem_addr+255:mem_addr] := a[255:0]

Performance

Architecture | Latency | Throughput | μops
Haswell | ~400 | 1 | 1
Broadwell | ~400 | 1 | 1
Skylake | ~400 | 1 | 1
Ivy Bridge |  | 1 |
Haswell |  | 1 |
Broadwell |  | 1 |
Skylake |  | 1 |


_mm256_sub_epi16

__m256i _mm256_sub_epi16( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: vpsubw
CPUID Flag: AVX2
Category: Arithmetic

Description

Subtract packed 16-bit integers in "b" from packed 16-bit integers in "a", and store the results in "dst".

Operation

FOR j := 0 to 15
    i := j*16
    dst[i+15:i] := a[i+15:i] - b[i+15:i]
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.33 | 1
Knights Landing | 2 | 0.5 | 1


_mm256_sub_epi32

__m256i _mm256_sub_epi32( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: vpsubd
CPUID Flag: AVX2
Category: Arithmetic

Description

Subtract packed 32-bit integers in "b" from packed 32-bit integers in "a", and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*32
    dst[i+31:i] := a[i+31:i] - b[i+31:i]
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.33 | 1
Knights Landing | 2 | 0.5 | 1


_mm256_sub_epi64

__m256i _mm256_sub_epi64( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: vpsubq
CPUID Flag: AVX2
Category: Arithmetic

Description

Subtract packed 64-bit integers in "b" from packed 64-bit integers in "a", and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*64
    dst[i+63:i] := a[i+63:i] - b[i+63:i]
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.33 | 1
Knights Landing | 2 | 0.5 | 1


_mm256_sub_epi8

__m256i _mm256_sub_epi8( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: vpsubb
CPUID Flag: AVX2
Category: Arithmetic

Description

Subtract packed 8-bit integers in "b" from packed 8-bit integers in "a", and store the results in "dst".

Operation

FOR j := 0 to 31
    i := j*8
    dst[i+7:i] := a[i+7:i] - b[i+7:i]
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.33 | 1
Knights Landing | 2 | 0.5 | 1


_mm256_sub_pd

__m256d _mm256_sub_pd( __m256d a, __m256d b )

Synopsis

#include "immintrin.h"
Instruction: vsubpd
CPUID Flag: AVX
Category: Arithmetic

Description

Subtract packed double-precision (64-bit) floating-point elements in "b" from packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*64
    dst[i+63:i] := a[i+63:i] - b[i+63:i]
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 1 | 2
Jaguar | 3 | 2 | 2
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 4 | 0.5 | 1
Knights Landing | 6 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 4 | 0.5 |


_mm256_sub_ps

__m256 _mm256_sub_ps( __m256 a, __m256 b )

Synopsis

#include "immintrin.h"
Instruction: vsubps
CPUID Flag: AVX
Category: Arithmetic

Description

Subtract packed single-precision (32-bit) floating-point elements in "b" from packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*32
    dst[i+31:i] := a[i+31:i] - b[i+31:i]
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 3 | 1 | 2
Jaguar | 3 | 2 | 2
Sandy Bridge | 3 | 1 | 1
Ivy Bridge | 3 | 1 | 1
Haswell | 3 | 1 | 1
Broadwell | 3 | 1 | 1
Skylake | 4 | 0.5 | 1
Knights Landing | 6 | 0.5 | 1
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 4 | 0.5 |


_mm256_subs_epi16

__m256i _mm256_subs_epi16( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: vpsubsw
CPUID Flag: AVX2
Category: Arithmetic

Description

Subtract packed 16-bit integers in "b" from packed 16-bit integers in "a" using saturation, and store the results in "dst".

Operation

FOR j := 0 to 15
    i := j*16
    dst[i+15:i] := Saturate_To_Int16(a[i+15:i] - b[i+15:i])
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.33 | 1
Knights Landing | 2 | 0.5 | 1


_mm256_subs_epi8

__m256i _mm256_subs_epi8( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: vpsubsb
CPUID Flag: AVX2
Category: Arithmetic

Description

Subtract packed 8-bit integers in "b" from packed 8-bit integers in "a" using saturation, and store the results in "dst".

Operation

FOR j := 0 to 31
    i := j*8
    dst[i+7:i] := Saturate_To_Int8(a[i+7:i] - b[i+7:i])
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.33 | 1
Knights Landing | 2 | 0.5 | 1


_mm256_subs_epu16

__m256i _mm256_subs_epu16( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: vpsubusw
CPUID Flag: AVX2
Category: Arithmetic

Description

Subtract packed unsigned 16-bit integers in "b" from packed unsigned 16-bit integers in "a" using saturation, and store the results in "dst".

Operation

FOR j := 0 to 15
    i := j*16
    dst[i+15:i] := Saturate_To_UnsignedInt16(a[i+15:i] - b[i+15:i])
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.33 | 1


_mm256_subs_epu8

__m256i _mm256_subs_epu8( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: vpsubusb
CPUID Flag: AVX2
Category: Arithmetic

Description

Subtract packed unsigned 8-bit integers in "b" from packed unsigned 8-bit integers in "a" using saturation, and store the results in "dst".

Operation

FOR j := 0 to 31
    i := j*8
    dst[i+7:i] := Saturate_To_UnsignedInt8(a[i+7:i] - b[i+7:i])
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Haswell | 1 | 0.5 | 1
Broadwell | 1 | 0.5 | 1
Skylake | 1 | 0.33 | 1


_mm256_svml_ceil_pd

__m256d _mm256_svml_ceil_pd( __m256d a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Special Math Functions

Description

Round the packed double-precision (64-bit) floating-point elements in "a" up to an integer value, and store the results as packed double-precision floating-point elements in "dst". This intrinsic may generate the "roundpd"/"vroundpd" instruction.

Operation

FOR j := 0 to 3
    i := j*64
    dst[i+63:i] := CEIL(a[i+63:i])
ENDFOR
dst[MAX:256] := 0


_mm256_svml_ceil_ps

__m256 _mm256_svml_ceil_ps( __m256 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Special Math Functions

Description

Round the packed single-precision (32-bit) floating-point elements in "a" up to an integer value, and store the results as packed single-precision floating-point elements in "dst". This intrinsic may generate the "roundps"/"vroundps" instruction.

Operation

FOR j := 0 to 7
    i := j*32
    dst[i+31:i] := CEIL(a[i+31:i])
ENDFOR
dst[MAX:256] := 0


_mm256_svml_floor_pd

__m256d _mm256_svml_floor_pd( __m256d a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Special Math Functions

Description

Round the packed double-precision (64-bit) floating-point elements in "a" down to an integer value, and store the results as packed double-precision floating-point elements in "dst". This intrinsic may generate the "roundpd"/"vroundpd" instruction.

Operation

FOR j := 0 to 3
    i := j*64
    dst[i+63:i] := FLOOR(a[i+63:i])
ENDFOR
dst[MAX:256] := 0


_mm256_svml_floor_ps

__m256 _mm256_svml_floor_ps( __m256 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Special Math Functions

Description

Round the packed single-precision (32-bit) floating-point elements in "a" down to an integer value, and store the results as packed single-precision floating-point elements in "dst". This intrinsic may generate the "roundps"/"vroundps" instruction.

Operation

FOR j := 0 to 7
    i := j*32
    dst[i+31:i] := FLOOR(a[i+31:i])
ENDFOR
dst[MAX:256] := 0


_mm256_svml_round_pd

__m256d _mm256_svml_round_pd( __m256d a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Special Math Functions

Description

Round the packed double-precision (64-bit) floating-point elements in "a" to the nearest integer value, and store the results as packed double-precision floating-point elements in "dst". This intrinsic may generate the "roundpd"/"vroundpd" instruction.

Operation

FOR j := 0 to 3
    i := j*64
    dst[i+63:i] := ROUND(a[i+63:i])
ENDFOR
dst[MAX:256] := 0


_mm256_svml_round_ps

__m256 _mm256_svml_round_ps( __m256 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Special Math Functions

Description

Round the packed single-precision (32-bit) floating-point elements in "a" to the nearest integer value, and store the results as packed single-precision floating-point elements in "dst". This intrinsic may generate the "roundps"/"vroundps" instruction.

Operation

FOR j := 0 to 7
    i := j*32
    dst[i+31:i] := ROUND(a[i+31:i])
ENDFOR
dst[MAX:256] := 0


_mm256_svml_sqrt_pd

__m256d _mm256_svml_sqrt_pd( __m256d a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Elementary Math Functions

Description

Compute the square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". Note that this intrinsic is less efficient than "_mm_sqrt_pd".

Operation

FOR j := 0 to 3
    i := j*64
    dst[i+63:i] := SQRT(a[i+63:i])
ENDFOR
dst[MAX:256] := 0


_mm256_svml_sqrt_ps

__m256 _mm256_svml_sqrt_ps( __m256 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Elementary Math Functions

Description

Compute the square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". Note that this intrinsic is less efficient than "_mm_sqrt_ps".

Operation

FOR j := 0 to 7
    i := j*32
    dst[i+31:i] := SQRT(a[i+31:i])
ENDFOR
dst[MAX:256] := 0


_mm256_tan_pd

__m256d _mm256_tan_pd( __m256d a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Trigonometry

Description

Compute the tangent of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*64
    dst[i+63:i] := TAN(a[i+63:i])
ENDFOR
dst[MAX:256] := 0


_mm256_tan_ps

__m256 _mm256_tan_ps( __m256 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Trigonometry

Description

Compute the tangent of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*32
    dst[i+31:i] := TAN(a[i+31:i])
ENDFOR
dst[MAX:256] := 0


_mm256_tand_pd

__m256d _mm256_tand_pd( __m256d a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Trigonometry

Description

Compute the tangent of packed double-precision (64-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*64
    dst[i+63:i] := TAND(a[i+63:i])
ENDFOR
dst[MAX:256] := 0


_mm256_tand_ps

__m256 _mm256_tand_ps( __m256 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Trigonometry

Description

Compute the tangent of packed single-precision (32-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*32
    dst[i+31:i] := TAND(a[i+31:i])
ENDFOR
dst[MAX:256] := 0


_mm256_tanh_pd

__m256d _mm256_tanh_pd( __m256d a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Trigonometry

Description

Compute the hyperbolic tangent of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*64
    dst[i+63:i] := TANH(a[i+63:i])
ENDFOR
dst[MAX:256] := 0


_mm256_tanh_ps

__m256 _mm256_tanh_ps( __m256 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Trigonometry

Description

Compute the hyperbolic tangent of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*32
    dst[i+31:i] := TANH(a[i+31:i])
ENDFOR
dst[MAX:256] := 0


_mm256_testc_pd

int _mm256_testc_pd( __m256d a, __m256d b )

Synopsis

#include "immintrin.h"
Instruction: vtestpd
CPUID Flag: AVX
Category: Logical

Description

Compute the bitwise AND of 256 bits (representing double-precision (64-bit) floating-point elements) in "a" and "b", producing an intermediate 256-bit value, and set "ZF" to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set "ZF" to 0. Compute the bitwise NOT of "a" and then AND with "b", producing an intermediate value, and set "CF" to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set "CF" to 0. Return the "CF" value.

Operation

tmp[255:0] := a[255:0] AND b[255:0]
IF (tmp[63] == tmp[127] == tmp[191] == tmp[255] == 0)
    ZF := 1
ELSE
    ZF := 0
FI
tmp[255:0] := (NOT a[255:0]) AND b[255:0]
IF (tmp[63] == tmp[127] == tmp[191] == tmp[255] == 0)
    CF := 1
ELSE
    CF := 0
FI
dst := CF


_mm256_testc_ps

int _mm256_testc_ps( __m256 a, __m256 b )

Synopsis

#include "immintrin.h"
Instruction: vtestps
CPUID Flag: AVX
Category: Logical

Description

Compute the bitwise AND of 256 bits (representing single-precision (32-bit) floating-point elements) in "a" and "b", producing an intermediate 256-bit value, and set "ZF" to 1 if the sign bit of each 32-bit element in the intermediate value is zero, otherwise set "ZF" to 0. Compute the bitwise NOT of "a" and then AND with "b", producing an intermediate value, and set "CF" to 1 if the sign bit of each 32-bit element in the intermediate value is zero, otherwise set "CF" to 0. Return the "CF" value.

Operation

tmp[255:0] := a[255:0] AND b[255:0]
IF (tmp[31] == tmp[63] == tmp[95] == tmp[127] == tmp[159] == tmp[191] == tmp[223] == tmp[255] == 0)
    ZF := 1
ELSE
    ZF := 0
FI
tmp[255:0] := (NOT a[255:0]) AND b[255:0]
IF (tmp[31] == tmp[63] == tmp[95] == tmp[127] == tmp[159] == tmp[191] == tmp[223] == tmp[255] == 0)
    CF := 1
ELSE
    CF := 0
FI
dst := CF

Performance

Architecture | Latency | Throughput | μops
Ivy Bridge | 2 | 1 |
Haswell | 2 | 1 |
Broadwell | 2 | 1 |
Skylake | 3 | 1 |


_mm256_testc_si256

int _mm256_testc_si256( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: vptest
CPUID Flag: AVX
Category: Logical

Description

Compute the bitwise AND of 256 bits (representing integer data) in "a" and "b", and set "ZF" to 1 if the result is zero, otherwise set "ZF" to 0. Compute the bitwise NOT of "a" and then AND with "b", and set "CF" to 1 if the result is zero, otherwise set "CF" to 0. Return the "CF" value.

Operation

IF (a[255:0] AND b[255:0] == 0)
    ZF := 1
ELSE
    ZF := 0
FI
IF ((NOT a[255:0]) AND b[255:0] == 0)
    CF := 1
ELSE
    CF := 0
FI
RETURN CF

Performance

Architecture | Latency | Throughput | μops
Ryzen | 4 | 2 | 3
Haswell | 2 | 1 | 2
Broadwell | 2 | 1 | 2
Skylake | 3 | 1 | 2
Knights Landing | 9 | 8 | 4


_mm256_testnzc_pd

int _mm256_testnzc_pd( __m256d a, __m256d b )

Synopsis

#include "immintrin.h"
Instruction: vtestpd
CPUID Flag: AVX
Category: Logical

Description

Compute the bitwise AND of 256 bits (representing double-precision (64-bit) floating-point elements) in "a" and "b", producing an intermediate 256-bit value, and set "ZF" to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set "ZF" to 0. Compute the bitwise NOT of "a" and then AND with "b", producing an intermediate value, and set "CF" to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set "CF" to 0. Return 1 if both the "ZF" and "CF" values are zero, otherwise return 0.

Operation

tmp[255:0] := a[255:0] AND b[255:0]
IF (tmp[63] == tmp[127] == tmp[191] == tmp[255] == 0)
    ZF := 1
ELSE
    ZF := 0
FI
tmp[255:0] := (NOT a[255:0]) AND b[255:0]
IF (tmp[63] == tmp[127] == tmp[191] == tmp[255] == 0)
    CF := 1
ELSE
    CF := 0
FI
IF (ZF == 0 && CF == 0)
    dst := 1
ELSE
    dst := 0
FI


_mm256_testnzc_ps

int _mm256_testnzc_ps( __m256 a, __m256 b )

Synopsis

#include "immintrin.h"
Instruction: vtestps
CPUID Flag: AVX
Category: Logical

Description

Compute the bitwise AND of 256 bits (representing single-precision (32-bit) floating-point elements) in "a" and "b", producing an intermediate 256-bit value, and set "ZF" to 1 if the sign bit of each 32-bit element in the intermediate value is zero, otherwise set "ZF" to 0. Compute the bitwise NOT of "a" and then AND with "b", producing an intermediate value, and set "CF" to 1 if the sign bit of each 32-bit element in the intermediate value is zero, otherwise set "CF" to 0. Return 1 if both the "ZF" and "CF" values are zero, otherwise return 0.

Operation

tmp[255:0] := a[255:0] AND b[255:0]
IF (tmp[31] == tmp[63] == tmp[95] == tmp[127] == tmp[159] == tmp[191] == tmp[223] == tmp[255]  == 0)
    ZF := 1
ELSE
    ZF := 0
FI
tmp[255:0] := (NOT a[255:0]) AND b[255:0]
IF (tmp[31] == tmp[63] == tmp[95] == tmp[127] == tmp[159] == tmp[191] == tmp[223] == tmp[255]  == 0)
    CF := 1
ELSE
    CF := 0
FI
IF (ZF == 0 && CF == 0)
    dst := 1
ELSE
    dst := 0
FI

Performance

Architecture | Latency | Throughput | μops
Ivy Bridge | 2 | 1 |
Haswell | 2 | 1 |
Broadwell | 2 | 1 |
Skylake | 3 | 1 |


_mm256_testnzc_si256

int _mm256_testnzc_si256( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: vptest
CPUID Flag: AVX
Category: Logical

Description

Compute the bitwise AND of 256 bits (representing integer data) in "a" and "b", and set "ZF" to 1 if the result is zero, otherwise set "ZF" to 0. Compute the bitwise NOT of "a" and then AND with "b", and set "CF" to 1 if the result is zero, otherwise set "CF" to 0. Return 1 if both the "ZF" and "CF" values are zero, otherwise return 0.

Operation

IF (a[255:0] AND b[255:0] == 0)
    ZF := 1
ELSE
    ZF := 0
FI
IF ((NOT a[255:0]) AND b[255:0] == 0)
    CF := 1
ELSE
    CF := 0
FI
IF (ZF == 0 && CF == 0)
    dst := 1
ELSE
    dst := 0
FI

Performance

Architecture | Latency | Throughput | μops
Ryzen | 4 | 2 | 3
Haswell | 2 | 1 | 2
Broadwell | 2 | 1 | 2
Skylake | 3 | 1 | 2
Knights Landing | 9 | 8 | 4


_mm256_testz_pd

int _mm256_testz_pd( __m256d a, __m256d b )

Synopsis

#include "immintrin.h"
Instruction: vtestpd
CPUID Flag: AVX
Category: Logical

Description

Compute the bitwise AND of 256 bits (representing double-precision (64-bit) floating-point elements) in "a" and "b", producing an intermediate 256-bit value, and set "ZF" to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set "ZF" to 0. Compute the bitwise NOT of "a" and then AND with "b", producing an intermediate value, and set "CF" to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set "CF" to 0. Return the "ZF" value.

Operation

tmp[255:0] := a[255:0] AND b[255:0]
IF (tmp[63] == tmp[127] == tmp[191] == tmp[255] == 0)
    ZF := 1
ELSE
    ZF := 0
FI
tmp[255:0] := (NOT a[255:0]) AND b[255:0]
IF (tmp[63] == tmp[127] == tmp[191] == tmp[255] == 0)
    CF := 1
ELSE
    CF := 0
FI
dst := ZF


_mm256_testz_ps

int _mm256_testz_ps( __m256 a, __m256 b )

Synopsis

#include "immintrin.h"
Instruction: vtestps
CPUID Flag: AVX
Category: Logical

Description

Compute the bitwise AND of 256 bits (representing single-precision (32-bit) floating-point elements) in "a" and "b", producing an intermediate 256-bit value, and set "ZF" to 1 if the sign bit of each 32-bit element in the intermediate value is zero, otherwise set "ZF" to 0. Compute the bitwise NOT of "a" and then AND with "b", producing an intermediate value, and set "CF" to 1 if the sign bit of each 32-bit element in the intermediate value is zero, otherwise set "CF" to 0. Return the "ZF" value.

Operation

tmp[255:0] := a[255:0] AND b[255:0]
IF (tmp[31] == tmp[63] == tmp[95] == tmp[127] == tmp[159] == tmp[191] == tmp[223] == tmp[255] == 0)
    ZF := 1
ELSE
    ZF := 0
FI
tmp[255:0] := (NOT a[255:0]) AND b[255:0]
IF (tmp[31] == tmp[63] == tmp[95] == tmp[127] == tmp[159] == tmp[191] == tmp[223] == tmp[255] == 0)
    CF := 1
ELSE
    CF := 0
FI
dst := ZF

Performance

Architecture | Latency | Throughput | μops
Ivy Bridge | 2 | 1 |
Haswell | 2 | 1 |
Broadwell | 2 | 1 |
Skylake | 3 | 1 |


_mm256_testz_si256

int _mm256_testz_si256( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: vptest
CPUID Flag: AVX
Category: Logical

Description

Compute the bitwise AND of 256 bits (representing integer data) in "a" and "b", and set "ZF" to 1 if the result is zero, otherwise set "ZF" to 0. Compute the bitwise NOT of "a" and then AND with "b", and set "CF" to 1 if the result is zero, otherwise set "CF" to 0. Return the "ZF" value.

Operation

IF (a[255:0] AND b[255:0] == 0)
    ZF := 1
ELSE
    ZF := 0
FI
IF ((NOT a[255:0]) AND b[255:0] == 0)
    CF := 1
ELSE
    CF := 0
FI
RETURN ZF

Performance

Architecture | Latency | Throughput | μops
Ryzen | 4 | 2 | 3
Haswell | 2 | 1 | 2
Broadwell | 2 | 1 | 2
Skylake | 3 | 1 | 2
Knights Landing | 9 | 8 | 4


_mm256_trunc_pd

__m256d _mm256_trunc_pd( __m256d a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Miscellaneous

Description

Truncate the packed double-precision (64-bit) floating-point elements in "a", and store the results as packed double-precision floating-point elements in "dst". This intrinsic may generate the "roundpd"/"vroundpd" instruction.

Operation

FOR j := 0 to 3
    i := j*64
    dst[i+63:i] := TRUNCATE(a[i+63:i])
ENDFOR
dst[MAX:256] := 0


_mm256_trunc_ps

__m256 _mm256_trunc_ps( __m256 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Miscellaneous

Description

Truncate the packed single-precision (32-bit) floating-point elements in "a", and store the results as packed single-precision floating-point elements in "dst". This intrinsic may generate the "roundps"/"vroundps" instruction.

Operation

FOR j := 0 to 7
    i := j*32
    dst[i+31:i] := TRUNCATE(a[i+31:i])
ENDFOR
dst[MAX:256] := 0


_mm256_udiv_epi32

__m256i _mm256_udiv_epi32( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Arithmetic

Description

Divide packed unsigned 32-bit integers in "a" by packed elements in "b", and store the truncated results in "dst".

Operation

FOR j := 0 to 7
    i := 32*j
    dst[i+31:i] := TRUNCATE(a[i+31:i] / b[i+31:i])
ENDFOR
dst[MAX:256] := 0


_mm256_udivrem_epi32

__m256i _mm256_udivrem_epi32( __m256i * mem_addr, __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Arithmetic

Description

Divide packed unsigned 32-bit integers in "a" by packed elements in "b", store the truncated results in "dst", and store the remainders as packed unsigned 32-bit integers into memory at "mem_addr".

Operation

FOR j := 0 to 7
    i := 32*j
    dst[i+31:i] := TRUNCATE(a[i+31:i] / b[i+31:i])
    MEM[mem_addr+i+31:mem_addr+i] := REMAINDER(a[i+31:i] / b[i+31:i])
ENDFOR
dst[MAX:256] := 0


_mm256_undefined_pd

__m256d _mm256_undefined_pd( void )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: General Support

Description

Return vector of type __m256d with undefined elements.


_mm256_undefined_ps

__m256 _mm256_undefined_ps( void )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: General Support

Description

Return vector of type __m256 with undefined elements.


_mm256_undefined_si256

__m256i _mm256_undefined_si256( void )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: General Support

Description

Return vector of type __m256i with undefined elements.


_mm256_unpackhi_epi16

__m256i _mm256_unpackhi_epi16( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: vpunpckhwd
CPUID Flag: AVX2
Category: Swizzle

Description

Unpack and interleave 16-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst".

Operation

DEFINE INTERLEAVE_HIGH_WORDS(src1[127:0], src2[127:0]) {
    dst[15:0] := src1[79:64]
    dst[31:16] := src2[79:64]
    dst[47:32] := src1[95:80]
    dst[63:48] := src2[95:80]
    dst[79:64] := src1[111:96]
    dst[95:80] := src2[111:96]
    dst[111:96] := src1[127:112]
    dst[127:112] := src2[127:112]
    RETURN dst[127:0]
}
dst[127:0] := INTERLEAVE_HIGH_WORDS(a[127:0], b[127:0])
dst[255:128] := INTERLEAVE_HIGH_WORDS(a[255:128], b[255:128])
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 11-14 | 9 | 5
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm256_unpackhi_epi32

__m256i _mm256_unpackhi_epi32( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: vpunpckhdq
CPUID Flag: AVX2
Category: Swizzle

Description

Unpack and interleave 32-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst".

Operation

DEFINE INTERLEAVE_HIGH_DWORDS(src1[127:0], src2[127:0]) {
    dst[31:0] := src1[95:64]
    dst[63:32] := src2[95:64]
    dst[95:64] := src1[127:96]
    dst[127:96] := src2[127:96]
    RETURN dst[127:0]
}
dst[127:0] := INTERLEAVE_HIGH_DWORDS(a[127:0], b[127:0])
dst[255:128] := INTERLEAVE_HIGH_DWORDS(a[255:128], b[255:128])
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 4-7 | 2 | 1
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm256_unpackhi_epi64

__m256i _mm256_unpackhi_epi64( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: vpunpckhqdq
CPUID Flag: AVX2
Category: Swizzle

Description

Unpack and interleave 64-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst".

Operation

DEFINE INTERLEAVE_HIGH_QWORDS(src1[127:0], src2[127:0]) {
    dst[63:0] := src1[127:64]
    dst[127:64] := src2[127:64]
    RETURN dst[127:0]
}
dst[127:0] := INTERLEAVE_HIGH_QWORDS(a[127:0], b[127:0])
dst[255:128] := INTERLEAVE_HIGH_QWORDS(a[255:128], b[255:128])
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 1 | 2
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 4-7 | 2 | 1
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm256_unpackhi_epi8

__m256i _mm256_unpackhi_epi8( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: vpunpckhbw
CPUID Flag: AVX2
Category: Swizzle

Description

Unpack and interleave 8-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst".

Operation

DEFINE INTERLEAVE_HIGH_BYTES(src1[127:0], src2[127:0]) {
    dst[7:0] := src1[71:64]
    dst[15:8] := src2[71:64]
    dst[23:16] := src1[79:72]
    dst[31:24] := src2[79:72]
    dst[39:32] := src1[87:80]
    dst[47:40] := src2[87:80]
    dst[55:48] := src1[95:88]
    dst[63:56] := src2[95:88]
    dst[71:64] := src1[103:96]
    dst[79:72] := src2[103:96]
    dst[87:80] := src1[111:104]
    dst[95:88] := src2[111:104]
    dst[103:96] := src1[119:112]
    dst[111:104] := src2[119:112]
    dst[119:112] := src1[127:120]
    dst[127:120] := src2[127:120]
    RETURN dst[127:0]
}
dst[127:0] := INTERLEAVE_HIGH_BYTES(a[127:0], b[127:0])
dst[255:128] := INTERLEAVE_HIGH_BYTES(a[255:128], b[255:128])
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 11-14 | 9 | 5
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm256_unpackhi_pd

__m256d _mm256_unpackhi_pd( __m256d a, __m256d b )

Synopsis

#include "immintrin.h"
Instruction: vunpckhpd
CPUID Flag: AVX
Category: Swizzle

Description

Unpack and interleave double-precision (64-bit) floating-point elements from the high half of each 128-bit lane in "a" and "b", and store the results in "dst".

Operation

DEFINE INTERLEAVE_HIGH_QWORDS(src1[127:0], src2[127:0]) {
    dst[63:0] := src1[127:64]
    dst[127:64] := src2[127:64]
    RETURN dst[127:0]
}
dst[127:0] := INTERLEAVE_HIGH_QWORDS(a[127:0], b[127:0])
dst[255:128] := INTERLEAVE_HIGH_QWORDS(a[255:128], b[255:128])
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 1 | 2
Jaguar | 2 | 1 | 2
Sandy Bridge | 1 | 1 | 1
Ivy Bridge | 1 | 1 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 4-7 | 2 | 1
Ivy Bridge | 1 | 1 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm256_unpackhi_ps

__m256 _mm256_unpackhi_ps( __m256 a, __m256 b )

Synopsis

#include "immintrin.h"
Instruction: vunpckhps
CPUID Flag: AVX
Category: Swizzle

Description

Unpack and interleave single-precision (32-bit) floating-point elements from the high half of each 128-bit lane in "a" and "b", and store the results in "dst".

Operation

DEFINE INTERLEAVE_HIGH_DWORDS(src1[127:0], src2[127:0]) {
    dst[31:0] := src1[95:64]
    dst[63:32] := src2[95:64]
    dst[95:64] := src1[127:96]
    dst[127:96] := src2[127:96]
    RETURN dst[127:0]
}
dst[127:0] := INTERLEAVE_HIGH_DWORDS(a[127:0], b[127:0])
dst[255:128] := INTERLEAVE_HIGH_DWORDS(a[255:128], b[255:128])
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 1 | 2
Jaguar | 2 | 1 | 2
Sandy Bridge | 1 | 1 | 1
Ivy Bridge | 1 | 1 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 4-7 | 2 | 1
Ivy Bridge | 1 | 1 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm256_unpacklo_epi16

__m256i _mm256_unpacklo_epi16( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: vpunpcklwd
CPUID Flag: AVX2
Category: Swizzle

Description

Unpack and interleave 16-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst".

Operation

DEFINE INTERLEAVE_WORDS(src1[127:0], src2[127:0]) {
    dst[15:0] := src1[15:0]
    dst[31:16] := src2[15:0]
    dst[47:32] := src1[31:16]
    dst[63:48] := src2[31:16]
    dst[79:64] := src1[47:32]
    dst[95:80] := src2[47:32]
    dst[111:96] := src1[63:48]
    dst[127:112] := src2[63:48]
    RETURN dst[127:0]
}
dst[127:0] := INTERLEAVE_WORDS(a[127:0], b[127:0])
dst[255:128] := INTERLEAVE_WORDS(a[255:128], b[255:128])
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 11-14 | 9 | 5
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm256_unpacklo_epi32

__m256i _mm256_unpacklo_epi32( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: vpunpckldq
CPUID Flag: AVX2
Category: Swizzle

Description

Unpack and interleave 32-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst".

Operation

DEFINE INTERLEAVE_DWORDS(src1[127:0], src2[127:0]) {
    dst[31:0] := src1[31:0]
    dst[63:32] := src2[31:0]
    dst[95:64] := src1[63:32]
    dst[127:96] := src2[63:32]
    RETURN dst[127:0]
}
dst[127:0] := INTERLEAVE_DWORDS(a[127:0], b[127:0])
dst[255:128] := INTERLEAVE_DWORDS(a[255:128], b[255:128])
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 4-7 | 2 | 1
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm256_unpacklo_epi64

__m256i _mm256_unpacklo_epi64( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: vpunpcklqdq
CPUID Flag: AVX2
Category: Swizzle

Description

Unpack and interleave 64-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst".

Operation

DEFINE INTERLEAVE_QWORDS(src1[127:0], src2[127:0]) {
    dst[63:0] := src1[63:0]
    dst[127:64] := src2[63:0]
    RETURN dst[127:0]
}
dst[127:0] := INTERLEAVE_QWORDS(a[127:0], b[127:0])
dst[255:128] := INTERLEAVE_QWORDS(a[255:128], b[255:128])
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 1 | 2
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 4-7 | 2 | 1
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm256_unpacklo_epi8

__m256i _mm256_unpacklo_epi8( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: vpunpcklbw
CPUID Flag: AVX2
Category: Swizzle

Description

Unpack and interleave 8-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst".

Operation

DEFINE INTERLEAVE_BYTES(src1[127:0], src2[127:0]) {
    dst[7:0] := src1[7:0]
    dst[15:8] := src2[7:0]
    dst[23:16] := src1[15:8]
    dst[31:24] := src2[15:8]
    dst[39:32] := src1[23:16]
    dst[47:40] := src2[23:16]
    dst[55:48] := src1[31:24]
    dst[63:56] := src2[31:24]
    dst[71:64] := src1[39:32]
    dst[79:72] := src2[39:32]
    dst[87:80] := src1[47:40]
    dst[95:88] := src2[47:40]
    dst[103:96] := src1[55:48]
    dst[111:104] := src2[55:48]
    dst[119:112] := src1[63:56]
    dst[127:120] := src2[63:56]
    RETURN dst[127:0]
}
dst[127:0] := INTERLEAVE_BYTES(a[127:0], b[127:0])
dst[255:128] := INTERLEAVE_BYTES(a[255:128], b[255:128])
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 11-14 | 9 | 5
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm256_unpacklo_pd

__m256d _mm256_unpacklo_pd( __m256d a, __m256d b )

Synopsis

#include "immintrin.h"
Instruction: vunpcklpd
CPUID Flag: AVX
Category: Swizzle

Description

Unpack and interleave double-precision (64-bit) floating-point elements from the low half of each 128-bit lane in "a" and "b", and store the results in "dst".

Operation

DEFINE INTERLEAVE_QWORDS(src1[127:0], src2[127:0]) {
    dst[63:0] := src1[63:0]
    dst[127:64] := src2[63:0]
    RETURN dst[127:0]
}
dst[127:0] := INTERLEAVE_QWORDS(a[127:0], b[127:0])
dst[255:128] := INTERLEAVE_QWORDS(a[255:128], b[255:128])
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 1 | 2
Jaguar | 2 | 1 | 2
Sandy Bridge | 1 | 1 | 1
Ivy Bridge | 1 | 1 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 4-7 | 2 | 1
Ivy Bridge | 1 | 1 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm256_unpacklo_ps

__m256 _mm256_unpacklo_ps( __m256 a, __m256 b )

Synopsis

#include "immintrin.h"
Instruction: vunpcklps
CPUID Flag: AVX
Category: Swizzle

Description

Unpack and interleave single-precision (32-bit) floating-point elements from the low half of each 128-bit lane in "a" and "b", and store the results in "dst".

Operation

DEFINE INTERLEAVE_DWORDS(src1[127:0], src2[127:0]) {
    dst[31:0] := src1[31:0]
    dst[63:32] := src2[31:0]
    dst[95:64] := src1[63:32]
    dst[127:96] := src2[63:32]
    RETURN dst[127:0]
}
dst[127:0] := INTERLEAVE_DWORDS(a[127:0], b[127:0])
dst[255:128] := INTERLEAVE_DWORDS(a[255:128], b[255:128])
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 1 | 2
Jaguar | 2 | 1 | 2
Sandy Bridge | 1 | 1 | 1
Ivy Bridge | 1 | 1 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 1 | 1
Knights Landing | 4-7 | 2 | 1
Ivy Bridge | 1 | 1 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 1 |


_mm256_urem_epi32

__m256i _mm256_urem_epi32( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Arithmetic

Description

Divide packed unsigned 32-bit integers in "a" by packed elements in "b", and store the remainders as packed unsigned 32-bit integers in "dst".

Operation

FOR j := 0 to 7
    i := 32*j
    dst[i+31:i] := REMAINDER(a[i+31:i] / b[i+31:i])
ENDFOR
dst[MAX:256] := 0


_mm256_xor_pd

__m256d _mm256_xor_pd( __m256d a, __m256d b )

Synopsis

#include "immintrin.h"
Instruction: vxorpd
CPUID Flag: AVX
Category: Logical

Description

Compute the bitwise XOR of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst".

Operation

FOR j := 0 to 3
    i := j*64
    dst[i+63:i] := a[i+63:i] XOR b[i+63:i]
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 2
Sandy Bridge | 1 | 1 | 1
Ivy Bridge | 1 | 1 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 0.33 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 1 | 1 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 0.33 |


_mm256_xor_ps

__m256 _mm256_xor_ps( __m256 a, __m256 b )

Synopsis

#include "immintrin.h"
Instruction: vxorps
CPUID Flag: AVX
Category: Logical

Description

Compute the bitwise XOR of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst".

Operation

FOR j := 0 to 7
    i := j*32
    dst[i+31:i] := a[i+31:i] XOR b[i+31:i]
ENDFOR
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 2
Sandy Bridge | 1 | 1 | 1
Ivy Bridge | 1 | 1 | 1
Haswell | 1 | 1 | 1
Broadwell | 1 | 1 | 1
Skylake | 1 | 0.33 | 1
Knights Landing | 2 | 0.5 | 1
Ivy Bridge | 1 | 1 |
Haswell | 1 | 1 |
Broadwell | 1 | 1 |
Skylake | 1 | 0.33 |


_mm256_xor_si256

__m256i _mm256_xor_si256( __m256i a, __m256i b )

Synopsis

#include "immintrin.h"
Instruction: vpxor
CPUID Flag: AVX2
Category: Logical

Description

Compute the bitwise XOR of 256 bits (representing integer data) in "a" and "b", and store the result in "dst".

Operation

dst[255:0] := (a[255:0] XOR b[255:0])
dst[MAX:256] := 0

Performance

Architecture | Latency | Throughput | μops
Ryzen | 1 | 0.5 | 2
Haswell | 1 | 0.33 | 1
Broadwell | 1 | 0.33 | 1
Skylake | 1 | 0.33 | 1
Knights Landing | 2 | 0.5 | 1
Haswell | 1 | 0.33 |
Broadwell | 1 | 0.33 |
Skylake | 1 | 0.33 |


_mm256_zeroall

void _mm256_zeroall( void )

Synopsis

#include "immintrin.h"
Instruction: vzeroall
CPUID Flag: AVX
Category: General Support

Description

Zero the contents of all XMM or YMM registers.

Operation

YMM0[MAX:0] := 0
YMM1[MAX:0] := 0
YMM2[MAX:0] := 0
YMM3[MAX:0] := 0
YMM4[MAX:0] := 0
YMM5[MAX:0] := 0
YMM6[MAX:0] := 0
YMM7[MAX:0] := 0
IF _64_BIT_MODE
    YMM8[MAX:0] := 0
    YMM9[MAX:0] := 0
    YMM10[MAX:0] := 0
    YMM11[MAX:0] := 0
    YMM12[MAX:0] := 0
    YMM13[MAX:0] := 0
    YMM14[MAX:0] := 0
    YMM15[MAX:0] := 0
FI

Performance

Architecture | Latency | Throughput | μops
Ryzen |  | 6 | 18
Jaguar |  | 58 | 41
Sandy Bridge |  | 11 | 12
Ivy Bridge |  | 11 | 12
Haswell |  | 10 | 12
Broadwell |  | 10 | 12
Skylake |  | 12 | 25
Knights Landing |  | 30 | 11
Ivy Bridge |  | 9 |
Haswell |  | 8 |
Broadwell |  | 8 |
Skylake |  | 12 |


_mm256_zeroupper

void _mm256_zeroupper( void )

Synopsis

#include "immintrin.h"
Instruction: vzeroupper
CPUID Flag: AVX
Category: General Support

Description

Zero the upper 128 bits of all YMM registers; the lower 128-bits of the registers are unmodified.

Operation

YMM0[MAX:128] := 0
YMM1[MAX:128] := 0
YMM2[MAX:128] := 0
YMM3[MAX:128] := 0
YMM4[MAX:128] := 0
YMM5[MAX:128] := 0
YMM6[MAX:128] := 0
YMM7[MAX:128] := 0
IF _64_BIT_MODE
    YMM8[MAX:128] := 0
    YMM9[MAX:128] := 0
    YMM10[MAX:128] := 0
    YMM11[MAX:128] := 0
    YMM12[MAX:128] := 0
    YMM13[MAX:128] := 0
    YMM14[MAX:128] := 0
    YMM15[MAX:128] := 0
FI

Performance

Architecture | Latency | Throughput | μops
Ryzen |  | 4 | 10
Jaguar |  | 30 | 21
Sandy Bridge | 2 | 1 | 4
Ivy Bridge |  | 1 | 4
Haswell |  | 1 | 4
Broadwell |  | 1 | 4
Skylake |  | 1 | 4
Knights Landing |  | 30 | 11
Ivy Bridge | 0 | 1 |
Haswell | 0 | 1 |
Broadwell | 0 | 1 |
Skylake | 0 | 1 |


_mm256_zextpd128_pd256

__m256d _mm256_zextpd128_pd256( __m128d a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Cast

Description

Casts vector of type __m128d to type __m256d; the upper 128 bits of the result are zeroed. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.


_mm256_zextps128_ps256

__m256 _mm256_zextps128_ps256( __m128 a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Cast

Description

Casts vector of type __m128 to type __m256; the upper 128 bits of the result are zeroed. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.


_mm256_zextsi128_si256

__m256i _mm256_zextsi128_si256( __m128i a )

Synopsis

#include "immintrin.h"
Instruction: N/A
CPUID Flag: AVX
Category: Cast

Description

Casts vector of type __m128i to type __m256i; the upper 128 bits of the result are zeroed. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.


_movdir64b

void _movdir64b( void* dst, const void* src )

Synopsis

#include "immintrin.h"
Instruction: MOVDIR64B
CPUID Flag: MOVDIR64B
Category: Store

Description

Move 64-byte (512-bit) value using direct store from source memory address "src" to destination memory address "dst".

Operation

dst[511:0] := src[511:0]


_mulx_u32

unsigned int _mulx_u32( unsigned int a, unsigned int b, unsigned int* hi )

Synopsis

#include "immintrin.h"
Instruction: mulx
CPUID Flag: BMI2
Category: Arithmetic

Description

Multiply unsigned 32-bit integers "a" and "b", store the low 32-bits of the result in "dst", and store the high 32-bits in "hi". This does not read or write arithmetic flags.

Operation

dst[31:0] := (a * b)[31:0]
hi[31:0] := (a * b)[63:32]

Performance

Architecture | Latency | Throughput | μops
Haswell | 4 | 1 |
Broadwell | 4 | 1 |
Skylake | 4 | 1 |


_mulx_u64

unsigned __int64 _mulx_u64( unsigned __int64 a, unsigned __int64 b, unsigned __int64* hi )

Synopsis

#include "immintrin.h"
Instruction: mulx
CPUID Flag: BMI2
Category: Arithmetic

Description

Multiply unsigned 64-bit integers "a" and "b", store the low 64-bits of the result in "dst", and store the high 64-bits in "hi". This does not read or write arithmetic flags.

Operation

dst[63:0] := (a * b)[63:0]
hi[63:0] := (a * b)[127:64]

Performance

Architecture | Latency | Throughput | μops
Haswell | 4 | 1 |
Broadwell | 4 | 1 |
Skylake | 4 | 1 |


_pconfig_u32

unsigned int _pconfig_u32( const int a, size_t* __data )

Synopsis

#include "immintrin.h"
Instruction: pconfig
CPUID Flag: PCONFIG
Category: Miscellaneous

Description

Invoke the PCONFIG leaf function specified by "a". The "__data" array contains 3 32-bit elements that may act as input, output, or be unused, depending on the semantics of the specified leaf function; these correspond to rbx, rcx, and rdx. May return the value in eax, depending on the semantics of the specified leaf function.


_pdep_u32

unsigned int _pdep_u32( unsigned int a, unsigned int mask )

Synopsis

#include "immintrin.h"
Instruction: pdep
CPUID Flag: BMI2
Category: Bit Manipulation

Description

Deposit contiguous low bits from unsigned 32-bit integer "a" to "dst" at the corresponding bit locations specified by "mask"; all other bits in "dst" are set to zero.

Operation

tmp := a
dst := 0
m := 0
k := 0
DO WHILE m < 32
    IF mask[m] == 1
        dst[m] := tmp[k]
        k := k + 1
    FI
    m := m + 1
OD

Performance

Architecture | Latency | Throughput | μops
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 3 | 1 |


_pdep_u64

unsigned __int64 _pdep_u64( unsigned __int64 a, unsigned __int64 mask )

Synopsis

#include "immintrin.h"
Instruction: pdep
CPUID Flag: BMI2
Category: Bit Manipulation

Description

Deposit contiguous low bits from unsigned 64-bit integer "a" to "dst" at the corresponding bit locations specified by "mask"; all other bits in "dst" are set to zero.

Operation

tmp := a
dst := 0
m := 0
k := 0
DO WHILE m < 64
    IF mask[m] == 1
        dst[m] := tmp[k]
        k := k + 1
    FI
    m := m + 1
OD

Performance

Architecture | Latency | Throughput | μops
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 3 | 1 |


_pext_u32

unsigned int _pext_u32( unsigned int a, unsigned int mask )

Synopsis

#include "immintrin.h"
Instruction: pext
CPUID Flag: BMI2
Category: Bit Manipulation

Description

Extract bits from unsigned 32-bit integer "a" at the corresponding bit locations specified by "mask" to contiguous low bits in "dst"; the remaining upper bits in "dst" are set to zero.

Operation

tmp := a
dst := 0
m := 0
k := 0
DO WHILE m < 32
    IF mask[m] == 1
        dst[k] := tmp[m]
        k := k + 1
    FI
    m := m + 1
OD

Performance

Architecture | Latency | Throughput | μops
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 3 | 1 |


_pext_u64

unsigned __int64 _pext_u64( unsigned __int64 a, unsigned __int64 mask )

Synopsis

#include "immintrin.h"
Instruction: pext
CPUID Flag: BMI2
Category: Bit Manipulation

Description

Extract bits from unsigned 64-bit integer "a" at the corresponding bit locations specified by "mask" to contiguous low bits in "dst"; the remaining upper bits in "dst" are set to zero.

Operation

tmp := a
dst := 0
m := 0
k := 0
DO WHILE m < 64
    IF mask[m] == 1
        dst[k] := tmp[m]
        k := k + 1
    FI
    m := m + 1
OD

Performance

Architecture | Latency | Throughput | μops
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 3 | 1 |


_popcnt32

int _popcnt32( int a )

Synopsis

#include "immintrin.h"
Instruction: popcnt
CPUID Flag: POPCNT
Category: Bit Manipulation

Description

Count the number of bits set to 1 in 32-bit integer "a", and return that count in "dst".

Operation

dst := 0
FOR i := 0 to 31
    IF a[i]
        dst := dst + 1
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 3 | 1 |


_popcnt64

int _popcnt64( __int64 a )

Synopsis

#include "immintrin.h"
Instruction: popcnt
CPUID Flag: POPCNT
Category: Bit Manipulation

Description

Count the number of bits set to 1 in 64-bit integer "a", and return that count in "dst".

Operation

dst := 0
FOR i := 0 to 63
    IF a[i]
        dst := dst + 1
    FI
ENDFOR

Performance

Architecture | Latency | Throughput | μops
Ivy Bridge | 3 | 1 |
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 3 | 1 |


_ptwrite32

void _ptwrite32( unsigned int a )

Synopsis

#include "immintrin.h"
Instruction: ptwrite
Category: Miscellaneous

Description

Insert the 32-bit data from "a" into a Processor Trace stream via a PTW packet. The PTW packet will be inserted if tracing is currently enabled and ptwrite is currently enabled. The current IP will also be inserted via a FUP packet if FUPonPTW is enabled.


_ptwrite64

void _ptwrite64( unsigned __int64 a )

Synopsis

#include "immintrin.h"
Instruction: ptwrite
Category: Miscellaneous

Description

Insert the 64-bit data from "a" into a Processor Trace stream via a PTW packet. The PTW packet will be inserted if tracing is currently enabled and ptwrite is currently enabled. The current IP will also be inserted via a FUP packet if FUPonPTW is enabled.


_rdpid_u32

unsigned int _rdpid_u32( void )

Synopsis

#include "immintrin.h"
Instruction: rdpid
CPUID Flag: RDPID
Category: General Support

Description

Copy the IA32_TSC_AUX MSR (signature value) into "dst".

Operation

dst[31:0] := IA32_TSC_AUX[31:0]


_rdpmc

__int64 _rdpmc( int a )

Synopsis

#include "immintrin.h"
Instruction: rdpmc
Category: General Support

Description

Read the Performance Monitor Counter (PMC) specified by "a", and store up to 64-bits in "dst". The width of performance counters is implementation specific.

Operation

dst[63:0] := ReadPMC(a)


_rdrand16_step

int _rdrand16_step( unsigned short* val )

Synopsis

#include "immintrin.h"
Instruction: rdrand
CPUID Flag: RDRAND
Category: Random

Description

Read a hardware generated 16-bit random value and store the result in "val". Return 1 if a random value was generated, and 0 otherwise.

Operation

IF HW_RND_GEN.ready == 1
    val[15:0] := HW_RND_GEN.data
    dst := 1
ELSE
    val[15:0] := 0
    dst := 0
FI

Performance

Architecture | Latency | Throughput | μops
Ryzen |  | ~1200 | 13
Ivy Bridge |  | 104-117 | 13
Haswell |  | ~320 | 17
Broadwell |  | ~230 | 16
Skylake |  | ~460 | 16
Knights Landing |  | 200 | 17
Ivy Bridge | <200 | <200 |
Haswell | Varies | ~250 |
Broadwell | Varies | ~250 |
Skylake | Varies | <300 |


_rdrand32_step

int _rdrand32_step( unsigned int* val )

Synopsis

#include "immintrin.h"
Instruction: rdrand
CPUID Flag: RDRAND
Category: Random

Description

Read a hardware generated 32-bit random value and store the result in "val". Return 1 if a random value was generated, and 0 otherwise.

Operation

IF HW_RND_GEN.ready == 1
    val[31:0] := HW_RND_GEN.data
    dst := 1
ELSE
    val[31:0] := 0
    dst := 0
FI

Performance

Architecture | Latency | Throughput | μops
Ryzen |  | ~1200 | 13
Ivy Bridge |  | 104-117 | 13
Haswell |  | ~320 | 17
Broadwell |  | ~230 | 16
Skylake |  | ~460 | 16
Knights Landing |  | 200 | 17
Ivy Bridge | <200 | <200 |
Haswell | Varies | ~250 |
Broadwell | Varies | ~250 |
Skylake | Varies | <300 |


_rdrand64_step

int _rdrand64_step( unsigned __int64* val )

Synopsis

#include "immintrin.h"
Instruction: rdrand
CPUID Flag: RDRAND
Category: Random

Description

Read a hardware generated 64-bit random value and store the result in "val". Return 1 if a random value was generated, and 0 otherwise.

Operation

IF HW_RND_GEN.ready == 1
    val[63:0] := HW_RND_GEN.data
    dst := 1
ELSE
    val[63:0] := 0
    dst := 0
FI

Performance

Architecture | Latency | Throughput | μops
Ryzen |  | ~1200 | 13
Ivy Bridge |  | 104-117 | 13
Haswell |  | ~320 | 17
Broadwell |  | ~230 | 16
Skylake |  | ~460 | 16
Knights Landing |  | 200 | 17
Ivy Bridge | <200 | <200 |
Haswell | Varies | ~250 |
Broadwell | Varies | ~250 |
Skylake | Varies | <300 |


_rdseed16_step

int _rdseed16_step( unsigned short * val )

Synopsis

#include "immintrin.h"
Instruction: rdseed
CPUID Flag: RDSEED
Category: Random

Description

Read a 16-bit NIST SP800-90B and SP800-90C compliant random value and store in "val". Return 1 if a random value was generated, and 0 otherwise.

Operation

IF HW_NRND_GEN.ready == 1
    val[15:0] := HW_NRND_GEN.data
    dst := 1
ELSE
    val[15:0] := 0
    dst := 0
FI

Performance

Architecture | Latency | Throughput | μops
Ryzen |  | ~1200 | 13
Broadwell |  | ~230 | 16
Skylake |  | ~460 | 16
Knights Landing |  | 200 | 17


_rdseed32_step

int _rdseed32_step( unsigned int * val )

Synopsis

#include "immintrin.h"
Instruction: rdseed
CPUID Flag: RDSEED
Category: Random

Description

Read a 32-bit NIST SP800-90B and SP800-90C compliant random value and store in "val". Return 1 if a random value was generated, and 0 otherwise.

Operation

IF HW_NRND_GEN.ready == 1
    val[31:0] := HW_NRND_GEN.data
    dst := 1
ELSE
    val[31:0] := 0
    dst := 0
FI

Performance

Architecture | Latency | Throughput | μops
Ryzen |  | ~1200 | 13
Broadwell |  | ~230 | 16
Skylake |  | ~460 | 16
Knights Landing |  | 200 | 17


_rdseed64_step

int _rdseed64_step( unsigned __int64 * val )

Synopsis

#include "immintrin.h"
Instruction: rdseed
CPUID Flag: RDSEED
Category: Random

Description

Read a 64-bit NIST SP800-90B and SP800-90C compliant random value and store in "val". Return 1 if a random value was generated, and 0 otherwise.

Operation

IF HW_NRND_GEN.ready == 1
    val[63:0] := HW_NRND_GEN.data
    dst := 1
ELSE
    val[63:0] := 0
    dst := 0
FI

Performance

Architecture | Latency | Throughput | μops
Ryzen |  | ~1200 | 13
Broadwell |  | ~230 | 16
Skylake |  | ~460 | 16
Knights Landing |  | 200 | 17


_rdsspd_i32

__int32 _rdsspd_i32( void )

Synopsis

#include "immintrin.h"
Instruction: rdsspd
Category: Miscellaneous

Description

Read the low 32-bits of the current shadow stack pointer, and store the result in "dst".

Operation

dst := SSP[31:0]


_rdsspq_i64

__int64 _rdsspq_i64( void )

Synopsis

#include "immintrin.h"
Instruction: rdsspq
Category: Miscellaneous

Description

Read the current shadow stack pointer, and store the result in "dst".

Operation

dst := SSP[63:0]


_rdtsc

__int64 _rdtsc( void )

Synopsis

#include "immintrin.h"
Instruction: rdtsc
CPUID Flag: TSC
Category: General Support

Description

Copy the current 64-bit value of the processor's time-stamp counter into "dst".

Operation

dst[63:0] := TimeStampCounter


_readfsbase_u32

unsigned int _readfsbase_u32()

Synopsis

#include "immintrin.h"
Instruction: rdfsbase
CPUID Flag: FSGSBASE
Category: General Support

Description

Read the FS segment base register and store the 32-bit result in "dst".

Operation

dst[31:0] := FS_Segment_Base_Register
dst[63:32] := 0


_readfsbase_u64

unsigned __int64 _readfsbase_u64()

Synopsis

#include "immintrin.h"
Instruction: rdfsbase
CPUID Flag: FSGSBASE
Category: General Support

Description

Read the FS segment base register and store the 64-bit result in "dst".

Operation

dst[63:0] := FS_Segment_Base_Register


_readgsbase_u32

unsigned int _readgsbase_u32()

Synopsis

#include "immintrin.h"
Instruction: rdgsbase
CPUID Flag: FSGSBASE
Category: General Support

Description

Read the GS segment base register and store the 32-bit result in "dst".

Operation

dst[31:0] := GS_Segment_Base_Register
dst[63:32] := 0


_readgsbase_u64

unsigned __int64 _readgsbase_u64()

Synopsis

#include "immintrin.h"
Instruction: rdgsbase
CPUID Flag: FSGSBASE
Category: General Support

Description

Read the GS segment base register and store the 64-bit result in "dst".

Operation

dst[63:0] := GS_Segment_Base_Register


_rotl

unsigned int _rotl( unsigned int a, int shift )

Synopsis

#include "immintrin.h"
Instruction: rol
Category: Shift

Description

Shift the bits of unsigned 32-bit integer "a" left by the number of bits specified in "shift", rotating the most-significant bit to the least-significant bit location, and store the unsigned result in "dst".

Operation

dst := a
count := shift AND 31
DO WHILE (count > 0)
    tmp[0] := dst[31]
    dst := (dst << 1) OR tmp[0]
    count := count - 1
OD


_rotl64

unsigned __int64 _rotl64( unsigned __int64 a, int shift )

Synopsis

#include "immintrin.h"
Instruction: rol
Category: Shift

Description

Shift the bits of unsigned 64-bit integer "a" left by the number of bits specified in "shift", rotating the most-significant bit to the least-significant bit location, and store the unsigned result in "dst".

Operation

dst := a
count := shift AND 63
DO WHILE (count > 0)
    tmp[0] := dst[63]
    dst := (dst << 1) OR tmp[0]
    count := count - 1
OD


_rotr

unsigned int _rotr( unsigned int a, int shift )

Synopsis

#include "immintrin.h"
Instruction: ror
Category: Shift

Description

Shift the bits of unsigned 32-bit integer "a" right by the number of bits specified in "shift", rotating the least-significant bit to the most-significant bit location, and store the unsigned result in "dst".

Operation

dst := a
count := shift AND 31
DO WHILE (count > 0)
    tmp[31] := dst[0]
    dst := (dst >> 1) OR tmp[31]
    count := count - 1
OD


_rotr64

unsigned __int64 _rotr64( unsigned __int64 a, int shift )

Synopsis

#include "immintrin.h"
Instruction: ror
Category: Shift

Description

Shift the bits of unsigned 64-bit integer "a" right by the number of bits specified in "shift", rotating the least-significant bit to the most-significant bit location, and store the unsigned result in "dst".

Operation

dst := a
count := shift AND 63
DO WHILE (count > 0)
    tmp[63] := dst[0]
    dst := (dst >> 1) OR tmp[63]
    count := count - 1
OD


_rotwl

unsigned short _rotwl( unsigned short a, int shift )

Synopsis

#include "immintrin.h"
Instruction: rol
Category: Shift

Description

Shift the bits of unsigned 16-bit integer "a" left by the number of bits specified in "shift", rotating the most-significant bit to the least-significant bit location, and store the unsigned result in "dst".

Operation

dst := a
count := shift AND 15
DO WHILE (count > 0)
    tmp[0] := dst[15]
    dst := (dst << 1) OR tmp[0]
    count := count - 1
OD


_rotwr

unsigned short _rotwr( unsigned short a, int shift )

Synopsis

#include "immintrin.h"
Instruction: ror
Category: Shift

Description

Shift the bits of unsigned 16-bit integer "a" right by the number of bits specified in "shift", rotating the least-significant bit to the most-significant bit location, and store the unsigned result in "dst".

Operation

dst := a
count := shift AND 15
DO WHILE (count > 0)
    tmp[15] := dst[0]
    dst := (dst >> 1) OR tmp[15]
    count := count - 1
OD


_rstorssp

void _rstorssp( void * p )

Synopsis

#include "immintrin.h"
Instruction: rstorssp
Category: Miscellaneous

Description

Restore the saved shadow stack pointer from the shadow stack restore token previously created on shadow stack by saveprevssp.


_saveprevssp

void _saveprevssp( void )

Synopsis

#include "immintrin.h"
Instruction: saveprevssp
Category: Miscellaneous

Description

Save the previous shadow stack pointer context.


_setssbsy

void _setssbsy( void )

Synopsis

#include "immintrin.h"
Instruction: setssbsy
Category: Miscellaneous

Description

Mark shadow stack pointed to by IA32_PL0_SSP as busy.


_storebe_i16

void _storebe_i16( void * ptr, short data )

Synopsis

#include "immintrin.h"
Instruction: movbe
CPUID Flag: MOVBE
Category: Store

Description

Perform a bit swap operation of the 16 bits in "data", and store the results to memory.

Operation

addr := MEM[ptr]
FOR j := 0 to 1
    i := j*8
    addr[i+7:i] := data[15-i:15-i-7]
ENDFOR


_storebe_i32

void _storebe_i32( void * ptr, int data )

Synopsis

#include "immintrin.h"
Instruction: movbe
CPUID Flag: MOVBE
Category: Store

Description

Perform a bit swap operation of the 32 bits in "data", and store the results to memory.

Operation

addr := MEM[ptr]
FOR j := 0 to 3
    i := j*8
    addr[i+7:i] := data[31-i:31-i-7]
ENDFOR


_storebe_i64

void _storebe_i64( void * ptr, __int64 data )

Synopsis

#include "immintrin.h"
Instruction: movbe
CPUID Flag: MOVBE
Category: Store

Description

Perform a bit swap operation of the 64 bits in "data", and store the results to memory.

Operation

addr := MEM[ptr]
FOR j := 0 to 7
    i := j*8
    addr[i+7:i] := data[63-i:63-i-7]
ENDFOR


_subborrow_u32

unsigned char _subborrow_u32( unsigned char b_in, unsigned int a, unsigned int b, unsigned int * out )

Synopsis

#include "immintrin.h"
Instruction: sbb
Category: Arithmetic

Description

Add unsigned 8-bit borrow "b_in" (carry flag) to unsigned 32-bit integer "b", and subtract the result from unsigned 32-bit integer "a". Store the unsigned 32-bit result in "out", and the carry-out in "dst" (carry or overflow flag).

Operation

out[31:0] := (a[31:0] - (b[31:0] + b_in))
dst := carry_out


_subborrow_u64

unsigned char _subborrow_u64( unsigned char b_in, unsigned __int64 a, unsigned __int64 b, unsigned __int64 * out )

Synopsis

#include "immintrin.h"
Instruction: sbb
Category: Arithmetic

Description

Add unsigned 8-bit borrow "b_in" (carry flag) to unsigned 64-bit integer "b", and subtract the result from unsigned 64-bit integer "a". Store the unsigned 64-bit result in "out", and the carry-out in "dst" (carry or overflow flag).

Operation

out[63:0] := (a[63:0] - (b[63:0] + b_in))
dst := carry_out


_tpause

int _tpause( size_t ctrl, unsigned __int64 counter )

Synopsis

#include "immintrin.h"
Instruction: TPAUSE
CPUID Flag: WAITPKG
Category: Miscellaneous

Description

Directs the processor to enter an implementation-dependent optimized state until the TSC reaches or exceeds the value specified in "counter". Bit 0 of "ctrl" selects between a lower power (cleared) or faster wakeup (set) optimized state. Returns the carry flag (CF).


_tzcnt_u32

unsigned int _tzcnt_u32( unsigned int a )

Synopsis

#include "immintrin.h"
Instruction: tzcnt
CPUID Flag: BMI1
Category: Bit Manipulation

Description

Count the number of trailing zero bits in unsigned 32-bit integer "a", and return that count in "dst".

Operation

tmp := 0
dst := 0
DO WHILE ((tmp < 32) AND a[tmp] == 0)
    tmp := tmp + 1
    dst := dst + 1
OD

Performance

Architecture | Latency | Throughput | μops
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 3 | 1 |


_tzcnt_u64

unsigned __int64 _tzcnt_u64( unsigned __int64 a )

Synopsis

#include "immintrin.h"
Instruction: tzcnt
CPUID Flag: BMI1
Category: Bit Manipulation

Description

Count the number of trailing zero bits in unsigned 64-bit integer "a", and return that count in "dst".

Operation

tmp := 0
dst := 0
DO WHILE ((tmp < 64) AND a[tmp] == 0)
    tmp := tmp + 1
    dst := dst + 1
OD

Performance

Architecture | Latency | Throughput | μops
Haswell | 3 | 1 |
Broadwell | 3 | 1 |
Skylake | 3 | 1 |


_umonitor

void _umonitor( void* a )

Synopsis

#include "immintrin.h"
Instruction: UMONITOR
CPUID Flag: WAITPKG
Category: Miscellaneous

Description

Sets up a linear address range to be monitored by hardware and activates the monitor. The address range should be a writeback memory caching type. The address is contained in "a".


_umwait

int _umwait( size_t ctrl, unsigned __int64 counter )

Synopsis

#include "immintrin.h"
Instruction: UMWAIT
CPUID Flag: WAITPKG
Category: Miscellaneous

Description

Directs the processor to enter an implementation-dependent optimized state while monitoring a range of addresses. The instruction wakes up when the TSC reaches or exceeds the value specified in "counter" (if the monitoring hardware did not trigger beforehand). Bit 0 of "ctrl" selects between a lower power (cleared) or faster wakeup (set) optimized state. Returns the carry flag (CF).


_wbinvd

void _wbinvd( void )

Synopsis

#include "immintrin.h"
Instruction: wbinvd
Category: Miscellaneous

Description

Write back and flush internal caches. Initiate writing-back and flushing of external caches.


_wbnoinvd

void _wbnoinvd( void )

Synopsis

#include "immintrin.h"
Instruction: WBNOINVD
CPUID Flag: WBNOINVD
Category: Miscellaneous

Description

Write back and do not flush internal caches. Initiate writing-back without flushing of external caches.


_writefsbase_u32

void _writefsbase_u32( unsigned int a )

Synopsis

#include "immintrin.h"
Instruction: wrfsbase
CPUID Flag: FSGSBASE
Category: General Support

Description

Write the unsigned 32-bit integer "a" to the FS segment base register.

Operation

FS_Segment_Base_Register[31:0] := a[31:0]
FS_Segment_Base_Register[63:32] := 0


_writefsbase_u64

void _writefsbase_u64( unsigned __int64 a )

Synopsis

#include "immintrin.h"
Instruction: wrfsbase
CPUID Flag: FSGSBASE
Category: General Support

Description

Write the unsigned 64-bit integer "a" to the FS segment base register.

Operation

FS_Segment_Base_Register[63:0] := a[63:0]


_writegsbase_u32

void _writegsbase_u32( unsigned int a )

Synopsis

#include "immintrin.h"
Instruction: wrgsbase
CPUID Flag: FSGSBASE
Category: General Support

Description

Write the unsigned 32-bit integer "a" to the GS segment base register.

Operation

GS_Segment_Base_Register[31:0] := a[31:0]
GS_Segment_Base_Register[63:32] := 0


_writegsbase_u64

void _writegsbase_u64( unsigned __int64 a )

Synopsis

#include "immintrin.h"
Instruction: wrgsbase
CPUID Flag: FSGSBASE
Category: General Support

Description

Write the unsigned 64-bit integer "a" to the GS segment base register.

Operation

GS_Segment_Base_Register[63:0] := a[63:0]


_wrssd

void _wrssd( __int32 val, void * p )

Synopsis

#include "immintrin.h"
Instruction: wrssd
Category: Miscellaneous

Description

Write 32-bit value in "val" to a shadow stack page in memory specified by "p".


_wrssq

void _wrssq( __int64 val, void * p )

Synopsis

#include "immintrin.h"
Instruction: wrssq
Category: Miscellaneous

Description

Write 64-bit value in "val" to a shadow stack page in memory specified by "p".


_wrussd

void _wrussd( __int32 val, void * p )

Synopsis

#include "immintrin.h"
Instruction: wrussd
Category: Miscellaneous

Description

Write 32-bit value in "val" to a user shadow stack page in memory specified by "p".


_wrussq

void _wrussq( __int64 val, void * p )

Synopsis

#include "immintrin.h"
Instruction: wrussq
Category: Miscellaneous

Description

Write 64-bit value in "val" to a user shadow stack page in memory specified by "p".


_xabort

void _xabort( const unsigned int imm8 )

Synopsis

#include "immintrin.h"
Instruction: xabort
CPUID Flag: RTM
Category: General Support

Description

Force an RTM abort. The EAX register is updated to reflect an XABORT instruction caused the abort, and the "imm8" parameter will be provided in bits [31:24] of EAX. Following an RTM abort, the logical processor resumes execution at the fallback address computed through the outermost XBEGIN instruction.

Operation

IF RTM_ACTIVE == 0
    // nop
ELSE
    // restore architectural register state
    // discard memory updates performed in transaction
    // update EAX with status and imm8 value
    eax[31:24] := imm8[7:0]
    RTM_NEST_COUNT := 0
    RTM_ACTIVE := 0
    IF _64_BIT_MODE
        RIP := fallbackRIP
    ELSE
        EIP := fallbackEIP
    FI
FI


_xbegin

unsigned int _xbegin( void )

Synopsis

#include "immintrin.h"
Instruction: xbegin
CPUID Flag: RTM
Category: General Support

Description

Specify the start of an RTM code region. If the logical processor was not already in transactional execution, then this call causes the logical processor to transition into transactional execution. On an RTM abort, the logical processor discards all architectural register and memory updates performed during the RTM execution, restores architectural state, and starts execution beginning at the fallback address computed from the outermost XBEGIN instruction. Return status of ~0 (0xFFFF) if continuing inside transaction; all other codes are aborts.

Operation

IF RTM_NEST_COUNT < MAX_RTM_NEST_COUNT
    RTM_NEST_COUNT := RTM_NEST_COUNT + 1
    IF RTM_NEST_COUNT == 1
        IF _64_BIT_MODE
            fallbackRIP := RIP
        ELSE IF _32_BIT_MODE
            fallbackEIP := EIP
        FI

        RTM_ACTIVE := 1
        // enter RTM execution, record register state, start tracking memory state
    FI
ELSE
    // RTM abort (see _xabort)
FI


_xend

void _xend( void )

Synopsis

#include "immintrin.h"
Instruction: xend
CPUID Flag: RTM
Category: General Support

Description

Specify the end of an RTM code region. If this corresponds to the outermost scope, the logical processor will attempt to commit the logical processor state atomically. If the commit fails, the logical processor will perform an RTM abort.

Operation

IF RTM_ACTIVE == 1
    RTM_NEST_COUNT := RTM_NEST_COUNT - 1
    IF RTM_NEST_COUNT == 0
        // try to commit transaction
        IF FAIL_TO_COMMIT_TRANSACTION
            // RTM abort (see _xabort)
        ELSE
            RTM_ACTIVE := 0
        FI
    FI
FI


_xgetbv

unsigned __int64 _xgetbv( unsigned int a )

Synopsis

#include "immintrin.h"
Instruction: xgetbv
CPUID Flag: XSAVE
Category: OS-Targeted

Description

Copy up to 64-bits from the value of the extended control register (XCR) specified by "a" into "dst". Currently only XFEATURE_ENABLED_MASK XCR is supported.

Operation

dst[63:0] := XCR[a]


_xrstor

void _xrstor( void * mem_addr, unsigned __int64 rs_mask )

Synopsis

#include "immintrin.h"
Instruction: xrstor
CPUID Flag: XSAVE
Category: OS-Targeted

Description

Perform a full or partial restore of the enabled processor states using the state information stored in memory at "mem_addr". State is restored based on bits [62:0] in "rs_mask", "XCR0", and "mem_addr.HEADER.XSTATE_BV". "mem_addr" must be aligned on a 64-byte boundary.

Operation

st_mask := mem_addr.HEADER.XSTATE_BV[62:0]
FOR i := 0 to 62
    IF (rs_mask[i] AND XCR0[i])
        IF st_mask[i]
            CASE (i) OF
            0: ProcessorState[x87_FPU] := mem_addr.FPUSSESave_Area[FPU]
            1: ProcessorState[SSE] := mem_addr.FPUSSESaveArea[SSE]
            DEFAULT: ProcessorState[i] := mem_addr.Ext_Save_Area[i]
            ESAC
        ELSE
            // ProcessorExtendedState := Processor Supplied Values
            CASE (i) OF
            1: MXCSR := mem_addr.FPUSSESave_Area[SSE]
            ESAC
        FI
    FI
    i := i + 1
ENDFOR


_xrstor64

void _xrstor64( void * mem_addr, unsigned __int64 rs_mask )

Synopsis

#include "immintrin.h"
Instruction: xrstor64
CPUID Flag: XSAVE
Category: OS-Targeted

Description

Perform a full or partial restore of the enabled processor states using the state information stored in memory at "mem_addr". State is restored based on bits [62:0] in "rs_mask", "XCR0", and "mem_addr.HEADER.XSTATE_BV". "mem_addr" must be aligned on a 64-byte boundary.

Operation

st_mask := mem_addr.HEADER.XSTATE_BV[62:0]
FOR i := 0 to 62
    IF (rs_mask[i] AND XCR0[i])
        IF st_mask[i]
            CASE (i) OF
            0: ProcessorState[x87_FPU] := mem_addr.FPUSSESave_Area[FPU]
            1: ProcessorState[SSE] := mem_addr.FPUSSESaveArea[SSE]
            DEFAULT: ProcessorState[i] := mem_addr.Ext_Save_Area[i]
            ESAC
        ELSE
            // ProcessorExtendedState := Processor Supplied Values
            CASE (i) OF
            1: MXCSR := mem_addr.FPUSSESave_Area[SSE]
            ESAC
        FI
    FI
    i := i + 1
ENDFOR


_xrstors

void _xrstors( const void * mem_addr, unsigned __int64 rs_mask )

Synopsis

#include "immintrin.h"
Instruction: xrstors
CPUID Flags: XSAVE
Category: OS-Targeted

Description

Perform a full or partial restore of the enabled processor states using the state information stored in memory at "mem_addr". xrstors differs from xrstor in that it can restore state components corresponding to bits set in the IA32_XSS MSR; xrstors cannot restore from an xsave area in which the extended region is in the standard form. State is restored based on bits [62:0] in "rs_mask", "XCR0", and "mem_addr.HEADER.XSTATE_BV". "mem_addr" must be aligned on a 64-byte boundary.

Operation

st_mask := mem_addr.HEADER.XSTATE_BV[62:0]
FOR i := 0 to 62
    IF (rs_mask[i] AND XCR0[i])
        IF st_mask[i]
            CASE (i) OF
            0: ProcessorState[x87_FPU] := mem_addr.FPUSSESave_Area[FPU]
            1: ProcessorState[SSE] := mem_addr.FPUSSESaveArea[SSE]
            DEFAULT: ProcessorState[i] := mem_addr.Ext_Save_Area[i]
            ESAC
        ELSE
            // ProcessorExtendedState := Processor Supplied Values
            CASE (i) OF
            1: MXCSR := mem_addr.FPUSSESave_Area[SSE]
            ESAC
        FI
    FI
    i := i + 1
ENDFOR


_xrstors64

void _xrstors64( const void * mem_addr, unsigned __int64 rs_mask )

Synopsis

#include "immintrin.h"
Instruction: xrstors64
CPUID Flags: XSAVE
Category: OS-Targeted

Description

Perform a full or partial restore of the enabled processor states using the state information stored in memory at "mem_addr". xrstors differs from xrstor in that it can restore state components corresponding to bits set in the IA32_XSS MSR; xrstors cannot restore from an xsave area in which the extended region is in the standard form. State is restored based on bits [62:0] in "rs_mask", "XCR0", and "mem_addr.HEADER.XSTATE_BV". "mem_addr" must be aligned on a 64-byte boundary.

Operation

st_mask := mem_addr.HEADER.XSTATE_BV[62:0]
FOR i := 0 to 62
    IF (rs_mask[i] AND XCR0[i])
        IF st_mask[i]
            CASE (i) OF
            0: ProcessorState[x87_FPU] := mem_addr.FPUSSESave_Area[FPU]
            1: ProcessorState[SSE] := mem_addr.FPUSSESaveArea[SSE]
            DEFAULT: ProcessorState[i] := mem_addr.Ext_Save_Area[i]
            ESAC
        ELSE
            // ProcessorExtendedState := Processor Supplied Values
            CASE (i) OF
            1: MXCSR := mem_addr.FPUSSESave_Area[SSE]
            ESAC
        FI
    FI
    i := i + 1
ENDFOR


_xsave

void _xsave( void * mem_addr, unsigned __int64 save_mask )

Synopsis

#include "immintrin.h"
Instruction: xsave
CPUID Flag: XSAVE
Category: OS-Targeted

Description

Perform a full or partial save of the enabled processor states to memory at "mem_addr". State is saved based on bits [62:0] in "save_mask" and "XCR0". "mem_addr" must be aligned on a 64-byte boundary.

Operation

mask[62:0] := save_mask[62:0] AND XCR0[62:0]
FOR i := 0 to 62
    IF mask[i]
        CASE (i) OF
        0: mem_addr.FPUSSESave_Area[FPU] := ProcessorState[x87_FPU]
        1: mem_addr.FPUSSESaveArea[SSE] := ProcessorState[SSE]
        DEFAULT: mem_addr.Ext_Save_Area[i] := ProcessorState[i]
        ESAC
        mem_addr.HEADER.XSTATE_BV[i] := INIT_FUNCTION[i]
    FI
    i := i + 1
ENDFOR


_xsave64

void _xsave64( void * mem_addr, unsigned __int64 save_mask )

Synopsis

#include "immintrin.h"
Instruction: xsave64
CPUID Flag: XSAVE
Category: OS-Targeted

Description

Perform a full or partial save of the enabled processor states to memory at "mem_addr". State is saved based on bits [62:0] in "save_mask" and "XCR0". "mem_addr" must be aligned on a 64-byte boundary.

Operation

mask[62:0] := save_mask[62:0] AND XCR0[62:0]
FOR i := 0 to 62
    IF mask[i]
        CASE (i) OF
        0: mem_addr.FPUSSESave_Area[FPU] := ProcessorState[x87_FPU]
        1: mem_addr.FPUSSESaveArea[SSE] := ProcessorState[SSE]
        DEFAULT: mem_addr.Ext_Save_Area[i] := ProcessorState[i]
        ESAC
        mem_addr.HEADER.XSTATE_BV[i] := INIT_FUNCTION[i]
    FI
    i := i + 1
ENDFOR


_xsavec

void _xsavec( void * mem_addr, unsigned __int64 save_mask )

Synopsis

#include "immintrin.h"
Instruction: xsavec
CPUID Flags: XSAVE
Category: OS-Targeted

Description

Perform a full or partial save of the enabled processor states to memory at "mem_addr"; xsavec differs from xsave in that it uses compaction and that it may use init optimization. State is saved based on bits [62:0] in "save_mask" and "XCR0". "mem_addr" must be aligned on a 64-byte boundary.

Operation

mask[62:0] := save_mask[62:0] AND XCR0[62:0]
FOR i := 0 to 62
    IF mask[i]
        CASE (i) OF
        0: mem_addr.FPUSSESave_Area[FPU] := ProcessorState[x87_FPU]
        1: mem_addr.FPUSSESaveArea[SSE] := ProcessorState[SSE]
        DEFAULT: mem_addr.Ext_Save_Area[i] := ProcessorState[i]
        ESAC
        mem_addr.HEADER.XSTATE_BV[i] := INIT_FUNCTION[i]
    FI
    i := i + 1
ENDFOR


_xsavec64

void _xsavec64( void * mem_addr, unsigned __int64 save_mask )

Synopsis

#include "immintrin.h"
Instruction: xsavec64
CPUID Flags: XSAVE
Category: OS-Targeted

Description

Perform a full or partial save of the enabled processor states to memory at "mem_addr"; xsavec differs from xsave in that it uses compaction and that it may use init optimization. State is saved based on bits [62:0] in "save_mask" and "XCR0". "mem_addr" must be aligned on a 64-byte boundary.

Operation

mask[62:0] := save_mask[62:0] AND XCR0[62:0]
FOR i := 0 to 62
    IF mask[i]
        CASE (i) OF
        0: mem_addr.FPUSSESave_Area[FPU] := ProcessorState[x87_FPU]
        1: mem_addr.FPUSSESaveArea[SSE] := ProcessorState[SSE]
        DEFAULT: mem_addr.Ext_Save_Area[i] := ProcessorState[i]
        ESAC
        mem_addr.HEADER.XSTATE_BV[i] := INIT_FUNCTION[i]
    FI
    i := i + 1
ENDFOR


_xsaveopt

void _xsaveopt( void * mem_addr, unsigned __int64 save_mask )

Synopsis

#include "immintrin.h"
Instruction: xsaveopt
CPUID Flags: XSAVE
Category: OS-Targeted

Description

Perform a full or partial save of the enabled processor states to memory at "mem_addr". State is saved based on bits [62:0] in "save_mask" and "XCR0". "mem_addr" must be aligned on a 64-byte boundary. The hardware may optimize the manner in which data is saved. The performance of this instruction will be equal to or better than using the XSAVE instruction.

Operation

mask[62:0] := save_mask[62:0] AND XCR0[62:0]
FOR i := 0 to 62
    IF mask[i]
        CASE (i) OF
        0: mem_addr.FPUSSESave_Area[FPU] := ProcessorState[x87_FPU]
        1: mem_addr.FPUSSESaveArea[SSE] := ProcessorState[SSE]
        2: mem_addr.EXT_SAVE_Area2[YMM] := ProcessorState[YMM]
        DEFAULT: mem_addr.Ext_Save_Area[i] := ProcessorState[i]
        ESAC
        mem_addr.HEADER.XSTATE_BV[i] := INIT_FUNCTION[i]
    FI
    i := i + 1
ENDFOR


_xsaveopt64

void _xsaveopt64( void * mem_addr, unsigned __int64 save_mask )

Synopsis

#include "immintrin.h"
Instruction: xsaveopt64
CPUID Flags: XSAVE
Category: OS-Targeted

Description

Perform a full or partial save of the enabled processor states to memory at "mem_addr". State is saved based on bits [62:0] in "save_mask" and "XCR0". "mem_addr" must be aligned on a 64-byte boundary. The hardware may optimize the manner in which data is saved. The performance of this instruction will be equal to or better than using the XSAVE64 instruction.

Operation

mask[62:0] := save_mask[62:0] AND XCR0[62:0]
FOR i := 0 to 62
    IF mask[i]
        CASE (i) OF
        0: mem_addr.FPUSSESave_Area[FPU] := ProcessorState[x87_FPU]
        1: mem_addr.FPUSSESaveArea[SSE] := ProcessorState[SSE]
        2: mem_addr.EXT_SAVE_Area2[YMM] := ProcessorState[YMM]
        DEFAULT: mem_addr.Ext_Save_Area[i] := ProcessorState[i]
        ESAC
        mem_addr.HEADER.XSTATE_BV[i] := INIT_FUNCTION[i]
    FI
    i := i + 1
ENDFOR


_xsaves

void _xsaves( void * mem_addr, unsigned __int64 save_mask )

Synopsis

#include "immintrin.h"
Instruction: xsaves
CPUID Flags: XSAVE
Category: OS-Targeted

Description

Perform a full or partial save of the enabled processor states to memory at "mem_addr"; xsaves differs from xsave in that it can save state components corresponding to bits set in IA32_XSS MSR and that it may use the modified optimization. State is saved based on bits [62:0] in "save_mask" and "XCR0". "mem_addr" must be aligned on a 64-byte boundary.

Operation

mask[62:0] := save_mask[62:0] AND XCR0[62:0]
FOR i := 0 to 62
    IF mask[i]
        CASE (i) OF
        0: mem_addr.FPUSSESave_Area[FPU] := ProcessorState[x87_FPU]
        1: mem_addr.FPUSSESaveArea[SSE] := ProcessorState[SSE]
        DEFAULT: mem_addr.Ext_Save_Area[i] := ProcessorState[i]
        ESAC
        mem_addr.HEADER.XSTATE_BV[i] := INIT_FUNCTION[i]
    FI
    i := i + 1
ENDFOR


_xsaves64

void _xsaves64( void * mem_addr, unsigned __int64 save_mask )

Synopsis

#include "immintrin.h"
Instruction: xsavec64
CPUID Flags: XSAVE
Category: OS-Targeted

Description

Perform a full or partial save of the enabled processor states to memory at "mem_addr"; xsaves differs from xsave in that it can save state components corresponding to bits set in IA32_XSS MSR and that it may use the modified optimization. State is saved based on bits [62:0] in "save_mask" and "XCR0". "mem_addr" must be aligned on a 64-byte boundary.

Operation

mask[62:0] := save_mask[62:0] AND XCR0[62:0]
FOR i := 0 to 62
    IF mask[i]
        CASE (i) OF
        0: mem_addr.FPUSSESave_Area[FPU] := ProcessorState[x87_FPU]
        1: mem_addr.FPUSSESaveArea[SSE] := ProcessorState[SSE]
        DEFAULT: mem_addr.Ext_Save_Area[i] := ProcessorState[i]
        ESAC
        mem_addr.HEADER.XSTATE_BV[i] := INIT_FUNCTION[i]
    FI
    i := i + 1
ENDFOR


_xsetbv

void _xsetbv( unsigned int a, unsigned __int64 val )

Synopsis

#include "immintrin.h"
Instruction: xsetbv
CPUID Flag: XSAVE
Category: OS-Targeted

Description

Copy 64-bits from "val" to the extended control register (XCR) specified by "a". Currently only XFEATURE_ENABLED_MASK XCR is supported.

Operation

XCR[a] := val[63:0]


_xtest

unsigned char _xtest( void )

Synopsis

#include "immintrin.h"
Instruction: xtest
CPUID Flag: RTM
Category: General Support

Description

Query the transactional execution status, return 1 if inside a transactionally executing RTM or HLE region, and return 0 otherwise.

Operation

IF (RTM_ACTIVE == 1 OR HLE_ACTIVE == 1)
    dst := 1
ELSE
    dst := 0
FI


Technologies

  • AVX
  • AVX2
  • FMA
  • MMX
  • SSE
  • SSE2
  • SSE3
  • SSE4.1
  • SSE4.2
  • SSSE3
  • SVML
  • Other


AVX

A B C D E F H I L M O P R S T U X Z

A

  • _mm256_add_pd Add packed double-precision floating-point elements in "a" and "b"
  • _mm256_add_ps Add packed single-precision floating-point elements in "a" and "b"
  • _mm256_addsub_pd Alternatively add and subtract packed double-precision floating-point elements in "a" to/from packed elements in "b"
  • _mm256_addsub_ps Alternatively add and subtract packed single-precision floating-point elements in "a" to/from packed elements in "b"
  • _mm256_and_pd Compute the bitwise AND of packed double-precision floating-point elements in "a" and "b"
  • _mm256_and_ps Compute the bitwise AND of packed single-precision floating-point elements in "a" and "b"
  • _mm256_andnot_pd Compute the bitwise NOT of packed double-precision floating-point elements in "a" and then AND with "b"
  • _mm256_andnot_ps Compute the bitwise NOT of packed single-precision floating-point elements in "a" and then AND with "b"

B

  • _mm256_blend_pd Blend packed double-precision floating-point elements from "a" and "b" using control mask "imm8"
  • _mm256_blend_ps Blend packed single-precision floating-point elements from "a" and "b" using control mask "imm8"
  • _mm256_blendv_pd Blend packed double-precision floating-point elements from "a" and "b" using "mask"
  • _mm256_blendv_ps Blend packed single-precision floating-point elements from "a" and "b" using "mask"
  • _mm256_broadcast_pd Broadcast 128 bits from memory (composed of 2 packed double-precision floating-point elements) to all elements of "dst"
  • _mm256_broadcast_ps Broadcast 128 bits from memory (composed of 4 packed single-precision floating-point elements) to all elements of "dst"
  • _mm256_broadcast_sd Broadcast a double-precision floating-point element from memory to all elements of "dst"
  • _mm256_broadcast_ss Broadcast a single-precision floating-point element from memory to all elements of "dst"
  • _mm_broadcast_ss Broadcast a single-precision floating-point element from memory to all elements of "dst"

C

  • _mm256_castpd_ps Cast vector of type __m256d to type __m256. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.
  • _mm256_castpd_si256 Casts vector of type __m256d to type __m256i. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.
  • _mm256_castpd128_pd256 Casts vector of type __m128d to type __m256d; the upper 128 bits of the result are undefined
  • _mm256_castpd256_pd128 Casts vector of type __m256d to type __m128d. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.
  • _mm256_castps_pd Cast vector of type __m256 to type __m256d. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.
  • _mm256_castps_si256 Casts vector of type __m256 to type __m256i. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.
  • _mm256_castps128_ps256 Casts vector of type __m128 to type __m256; the upper 128 bits of the result are undefined
  • _mm256_castps256_ps128 Casts vector of type __m256 to type __m128. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.
  • _mm256_castsi128_si256 Casts vector of type __m128i to type __m256i; the upper 128 bits of the result are undefined
  • _mm256_castsi256_pd Casts vector of type __m256i to type __m256d. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.
  • _mm256_castsi256_ps Casts vector of type __m256i to type __m256. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.
  • _mm256_castsi256_si128 Casts vector of type __m256i to type __m128i. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.
  • _mm256_ceil_pd Round the packed double-precision floating-point elements in "a" up to an integer value
  • _mm256_ceil_ps Round the packed single-precision floating-point elements in "a" up to an integer value
  • _mm_cmp_pd Compare packed double-precision floating-point elements in "a" and "b"
  • _mm256_cmp_pd Compare packed double-precision floating-point elements in "a" and "b"
  • _mm_cmp_ps Compare packed single-precision floating-point elements in "a" and "b"
  • _mm256_cmp_ps Compare packed single-precision floating-point elements in "a" and "b"
  • _mm_cmp_sd Compare the lower double-precision floating-point element in "a" and "b"
  • _mm_cmp_ss Compare the lower single-precision floating-point element in "a" and "b"
  • _mm256_cvtepi32_pd Convert packed 32-bit integers in "a" to packed double-precision floating-point elements
  • _mm256_cvtepi32_ps Convert packed 32-bit integers in "a" to packed single-precision floating-point elements
  • _mm256_cvtpd_epi32 Convert packed double-precision floating-point elements in "a" to packed 32-bit integers
  • _mm256_cvtpd_ps Convert packed double-precision floating-point elements in "a" to packed single-precision floating-point elements
  • _mm256_cvtps_epi32 Convert packed single-precision floating-point elements in "a" to packed 32-bit integers
  • _mm256_cvtps_pd Convert packed single-precision floating-point elements in "a" to packed double-precision floating-point elements
  • _mm256_cvtss_f32 Copy the lower single-precision floating-point element of "a" to "dst"
  • _mm256_cvttpd_epi32 Convert packed double-precision floating-point elements in "a" to packed 32-bit integers with truncation
  • _mm256_cvttps_epi32 Convert packed single-precision floating-point elements in "a" to packed 32-bit integers with truncation

D

  • _mm256_div_pd Divide packed double-precision floating-point elements in "a" by packed elements in "b"
  • _mm256_div_ps Divide packed single-precision floating-point elements in "a" by packed elements in "b"
  • _mm256_dp_ps Conditionally multiply the packed single-precision floating-point elements in "a" and "b" using the high 4 bits in "imm8", sum the four products, and conditionally store the sum in "dst" using the low 4 bits of "imm8"

E

  • _mm256_extract_epi32 Extract a 32-bit integer from "a", selected with "index", and store the result in "dst"
  • _mm256_extract_epi64 Extract a 64-bit integer from "a", selected with "index", and store the result in "dst"
  • _mm256_extractf128_pd Extract 128 bits (composed of 2 packed double-precision floating-point elements) from "a", selected with "imm8"
  • _mm256_extractf128_ps Extract 128 bits (composed of 4 packed single-precision floating-point elements) from "a", selected with "imm8"
  • _mm256_extractf128_si256 Extract 128 bits (composed of integer data) from "a", selected with "imm8"

F

  • _mm256_floor_pd Round the packed double-precision floating-point elements in "a" down to an integer value
  • _mm256_floor_ps Round the packed single-precision floating-point elements in "a" down to an integer value

H

  • _mm256_hadd_pd Horizontally add adjacent pairs of double-precision floating-point elements in "a" and "b", and pack the results in "dst"
  • _mm256_hadd_ps Horizontally add adjacent pairs of single-precision floating-point elements in "a" and "b", and pack the results in "dst"
  • _mm256_hsub_pd Horizontally subtract adjacent pairs of double-precision floating-point elements in "a" and "b", and pack the results in "dst"
  • _mm256_hsub_ps Horizontally add adjacent pairs of single-precision floating-point elements in "a" and "b", and pack the results in "dst"

I

  • _mm256_insert_epi8 Copy "a" to "dst", and insert the 8-bit integer "i" into "dst" at the location specified by "index"
  • _mm256_insert_epi16 Copy "a" to "dst", and insert the 16-bit integer "i" into "dst" at the location specified by "index"
  • _mm256_insert_epi32 Copy "a" to "dst", and insert the 32-bit integer "i" into "dst" at the location specified by "index"
  • _mm256_insert_epi64 Copy "a" to "dst", and insert the 64-bit integer "i" into "dst" at the location specified by "index"
  • _mm256_insertf128_pd Copy "a" to "dst", then insert 128 bits (composed of 2 packed double-precision floating-point elements) from "b" into "dst" at the location specified by "imm8"
  • _mm256_insertf128_ps Copy "a" to "dst", then insert 128 bits (composed of 4 packed single-precision floating-point elements) from "b" into "dst" at the location specified by "imm8"
  • _mm256_insertf128_si256 Copy "a" to "dst", then insert 128 bits from "b" into "dst" at the location specified by "imm8"

L

  • _mm256_lddqu_si256 Load 256-bits of integer data from unaligned memory into "dst". This intrinsic may perform better than "_mm256_loadu_si256" when the data crosses a cache line boundary.
  • _mm256_load_pd Load 256-bits (composed of 4 packed double-precision floating-point elements) from memory into "dst"
  • _mm256_load_ps Load 256-bits (composed of 8 packed single-precision floating-point elements) from memory into "dst"
  • _mm256_load_si256 Load 256-bits of integer data from memory into "dst". "mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.
  • _mm256_loadu_pd Load 256-bits (composed of 4 packed double-precision floating-point elements) from memory into "dst"
  • _mm256_loadu_ps Load 256-bits (composed of 8 packed single-precision floating-point elements) from memory into "dst"
  • _mm256_loadu_si256 Load 256-bits of integer data from memory into "dst". "mem_addr" does not need to be aligned on any particular boundary.
  • _mm256_loadu2_m128 Load two 128-bit values (composed of 4 packed single-precision floating-point elements) from memory, and combine them into a 256-bit value in "dst"
  • _mm256_loadu2_m128d Load two 128-bit values (composed of 2 packed double-precision floating-point elements) from memory, and combine them into a 256-bit value in "dst"
  • _mm256_loadu2_m128i Load two 128-bit values (composed of integer data) from memory, and combine them into a 256-bit value in "dst"

M

  • _mm256_maskload_pd Load packed double-precision floating-point elements from memory into "dst" using "mask" (elements are zeroed out when the high bit of the corresponding element is not set)
  • _mm_maskload_pd Load packed double-precision floating-point elements from memory into "dst" using "mask" (elements are zeroed out when the high bit of the corresponding element is not set)
  • _mm256_maskload_ps Load packed single-precision floating-point elements from memory into "dst" using "mask" (elements are zeroed out when the high bit of the corresponding element is not set)
  • _mm_maskload_ps Load packed single-precision floating-point elements from memory into "dst" using "mask" (elements are zeroed out when the high bit of the corresponding element is not set)
  • _mm256_maskstore_pd Store packed double-precision floating-point elements from "a" into memory using "mask"
  • _mm_maskstore_pd Store packed double-precision floating-point elements from "a" into memory using "mask"
  • _mm256_maskstore_ps Store packed single-precision floating-point elements from "a" into memory using "mask"
  • _mm_maskstore_ps Store packed single-precision floating-point elements from "a" into memory using "mask"
  • _mm256_max_pd Compare packed double-precision floating-point elements in "a" and "b", and store packed maximum values in "dst"
  • _mm256_max_ps Compare packed single-precision floating-point elements in "a" and "b", and store packed maximum values in "dst"
  • _mm256_min_pd Compare packed double-precision floating-point elements in "a" and "b", and store packed minimum values in "dst"
  • _mm256_min_ps Compare packed single-precision floating-point elements in "a" and "b", and store packed minimum values in "dst"
  • _mm256_movedup_pd Duplicate even-indexed double-precision floating-point elements from "a"
  • _mm256_movehdup_ps Duplicate odd-indexed single-precision floating-point elements from "a"
  • _mm256_moveldup_ps Duplicate even-indexed single-precision floating-point elements from "a"
  • _mm256_movemask_pd Set each bit of mask "dst" based on the most significant bit of the corresponding packed double-precision floating-point element in "a"
  • _mm256_movemask_ps Set each bit of mask "dst" based on the most significant bit of the corresponding packed single-precision floating-point element in "a"
  • _mm256_mul_pd Multiply packed double-precision floating-point elements in "a" and "b"
  • _mm256_mul_ps Multiply packed single-precision floating-point elements in "a" and "b"

O

  • _mm256_or_pd Compute the bitwise OR of packed double-precision floating-point elements in "a" and "b"
  • _mm256_or_ps Compute the bitwise OR of packed single-precision floating-point elements in "a" and "b"

P

  • _mm256_permute_pd Shuffle double-precision floating-point elements in "a" within 128-bit lanes using the control in "imm8"
  • _mm_permute_pd Shuffle double-precision floating-point elements in "a" using the control in "imm8"
  • _mm256_permute_ps Shuffle single-precision floating-point elements in "a" within 128-bit lanes using the control in "imm8"
  • _mm_permute_ps Shuffle single-precision floating-point elements in "a" using the control in "imm8"
  • _mm256_permute2f128_pd Shuffle 128-bits (composed of 2 packed double-precision floating-point elements) selected by "imm8" from "a" and "b"
  • _mm256_permute2f128_ps Shuffle 128-bits (composed of 4 packed single-precision floating-point elements) selected by "imm8" from "a" and "b"
  • _mm256_permute2f128_si256 Shuffle 128-bits (composed of integer data) selected by "imm8" from "a" and "b"
  • _mm256_permutevar_pd Shuffle double-precision floating-point elements in "a" within 128-bit lanes using the control in "b"
  • _mm_permutevar_pd Shuffle double-precision floating-point elements in "a" using the control in "b"
  • _mm256_permutevar_ps Shuffle single-precision floating-point elements in "a" within 128-bit lanes using the control in "b"
  • _mm_permutevar_ps Shuffle single-precision floating-point elements in "a" using the control in "b"

R

  • _mm256_rcp_ps Compute the approximate reciprocal of packed single-precision floating-point elements in "a"
  • _mm256_round_pd Round the packed double-precision floating-point elements in "a" using the "rounding" parameter
  • _mm256_round_ps Round the packed single-precision floating-point elements in "a" using the "rounding" parameter
  • _mm256_rsqrt_ps Compute the approximate reciprocal square root of packed single-precision floating-point elements in "a"

S

  • _mm256_set_epi8 Set packed 8-bit integers in "dst" with the supplied values in reverse order
  • _mm256_set_epi16 Set packed 16-bit integers in "dst" with the supplied values.
  • _mm256_set_epi32 Set packed 32-bit integers in "dst" with the supplied values.
  • _mm256_set_epi64x Set packed 64-bit integers in "dst" with the supplied values.
  • _mm256_set_m128 Set packed __m256 vector "dst" with the supplied values.
  • _mm256_set_m128d Set packed __m256d vector "dst" with the supplied values.
  • _mm256_set_m128i Set packed __m256i vector "dst" with the supplied values.
  • _mm256_set_pd Set packed double-precision floating-point elements in "dst" with the supplied values
  • _mm256_set_ps Set packed single-precision floating-point elements in "dst" with the supplied values
  • _mm256_set1_epi8 Broadcast 8-bit integer "a" to all elements of "dst". This intrinsic may generate the "vpbroadcastb".
  • _mm256_set1_epi16 Broadcast 16-bit integer "a" to all all elements of "dst". This intrinsic may generate the "vpbroadcastw".
  • _mm256_set1_epi32 Broadcast 32-bit integer "a" to all elements of "dst". This intrinsic may generate the "vpbroadcastd".
  • _mm256_set1_epi64x Broadcast 64-bit integer "a" to all elements of "dst". This intrinsic may generate the "vpbroadcastq".
  • _mm256_set1_pd Broadcast double-precision floating-point value "a" to all elements of "dst"
  • _mm256_set1_ps Broadcast single-precision floating-point value "a" to all elements of "dst"
  • _mm256_setr_epi8 Set packed 8-bit integers in "dst" with the supplied values in reverse order
  • _mm256_setr_epi16 Set packed 16-bit integers in "dst" with the supplied values in reverse order
  • _mm256_setr_epi32 Set packed 32-bit integers in "dst" with the supplied values in reverse order
  • _mm256_setr_epi64x Set packed 64-bit integers in "dst" with the supplied values in reverse order
  • _mm256_setr_m128 Set packed __m256 vector "dst" with the supplied values.
  • _mm256_setr_m128d Set packed __m256d vector "dst" with the supplied values.
  • _mm256_setr_m128i Set packed __m256i vector "dst" with the supplied values.
  • _mm256_setr_pd Set packed double-precision floating-point elements in "dst" with the supplied values in reverse order
  • _mm256_setr_ps Set packed single-precision floating-point elements in "dst" with the supplied values in reverse order
  • _mm256_setzero_pd Return vector of type __m256d with all elements set to zero.
  • _mm256_setzero_ps Return vector of type __m256 with all elements set to zero.
  • _mm256_setzero_si256 Return vector of type __m256i with all elements set to zero.
  • _mm256_shuffle_pd Shuffle double-precision floating-point elements within 128-bit lanes using the control in "imm8"
  • _mm256_shuffle_ps Shuffle single-precision floating-point elements in "a" within 128-bit lanes using the control in "imm8"
  • _mm256_sqrt_pd Compute the square root of packed double-precision floating-point elements in "a"
  • _mm256_sqrt_ps Compute the square root of packed single-precision floating-point elements in "a"
  • _mm256_store_pd Store 256-bits (composed of 4 packed double-precision floating-point elements) from "a" into memory
  • _mm256_store_ps Store 256-bits (composed of 8 packed single-precision floating-point elements) from "a" into memory
  • _mm256_store_si256 Store 256-bits of integer data from "a" into memory. "mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.
  • _mm256_storeu_pd Store 256-bits (composed of 4 packed double-precision floating-point elements) from "a" into memory
  • _mm256_storeu_ps Store 256-bits (composed of 8 packed single-precision floating-point elements) from "a" into memory
  • _mm256_storeu_si256 Store 256-bits of integer data from "a" into memory. "mem_addr" does not need to be aligned on any particular boundary.
  • _mm256_storeu2_m128 Store the high and low 128-bit halves (each composed of 4 packed single-precision floating-point elements) from "a" into memory two different 128-bit locations
  • _mm256_storeu2_m128d Store the high and low 128-bit halves (each composed of 2 packed double-precision floating-point elements) from "a" into memory two different 128-bit locations
  • _mm256_storeu2_m128i Store the high and low 128-bit halves (each composed of integer data) from "a" into memory two different 128-bit locations
  • _mm256_stream_pd Store 256-bits (composed of 4 packed double-precision floating-point elements) from "a" into memory using a non-temporal memory hint
  • _mm256_stream_ps Store 256-bits (composed of 8 packed single-precision floating-point elements) from "a" into memory using a non-temporal memory hint
  • _mm256_stream_si256 Store 256-bits of integer data from "a" into memory using a non-temporal memory hint
  • _mm256_sub_pd Subtract packed double-precision floating-point elements in "b" from packed double-precision floating-point elements in "a"
  • _mm256_sub_ps Subtract packed single-precision floating-point elements in "b" from packed single-precision floating-point elements in "a"

T

  • _mm256_testc_pd Compute the bitwise AND of 256 bits (representing double-precision floating-point elements) in "a" and "b", producing an intermediate 256-bit value, and set "ZF" to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set "ZF" to 0
  • _mm_testc_pd Compute the bitwise AND of 128 bits (representing double-precision floating-point elements) in "a" and "b", producing an intermediate 128-bit value, and set "ZF" to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set "ZF" to 0
  • _mm256_testc_ps Compute the bitwise AND of 256 bits (representing single-precision floating-point elements) in "a" and "b", producing an intermediate 256-bit value, and set "ZF" to 1 if the sign bit of each 32-bit element in the intermediate value is zero, otherwise set "ZF" to 0
  • _mm_testc_ps Compute the bitwise AND of 128 bits (representing single-precision floating-point elements) in "a" and "b", producing an intermediate 128-bit value, and set "ZF" to 1 if the sign bit of each 32-bit element in the intermediate value is zero, otherwise set "ZF" to 0
  • _mm256_testc_si256 Compute the bitwise AND of 256 bits (representing integer data) in "a" and "b", and set "ZF" to 1 if the result is zero, otherwise set "ZF" to 0
  • _mm256_testnzc_pd Compute the bitwise AND of 256 bits (representing double-precision floating-point elements) in "a" and "b", producing an intermediate 256-bit value, and set "ZF" to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set "ZF" to 0
  • _mm_testnzc_pd Compute the bitwise AND of 128 bits (representing double-precision floating-point elements) in "a" and "b", producing an intermediate 128-bit value, and set "ZF" to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set "ZF" to 0
  • _mm256_testnzc_ps Compute the bitwise AND of 256 bits (representing single-precision floating-point elements) in "a" and "b", producing an intermediate 256-bit value, and set "ZF" to 1 if the sign bit of each 32-bit element in the intermediate value is zero, otherwise set "ZF" to 0
  • _mm_testnzc_ps Compute the bitwise AND of 128 bits (representing single-precision floating-point elements) in "a" and "b", producing an intermediate 128-bit value, and set "ZF" to 1 if the sign bit of each 32-bit element in the intermediate value is zero, otherwise set "ZF" to 0
  • _mm256_testnzc_si256 Compute the bitwise AND of 256 bits (representing integer data) in "a" and "b", and set "ZF" to 1 if the result is zero, otherwise set "ZF" to 0
  • _mm256_testz_pd Compute the bitwise AND of 256 bits (representing double-precision floating-point elements) in "a" and "b", producing an intermediate 256-bit value, and set "ZF" to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set "ZF" to 0
  • _mm_testz_pd Compute the bitwise AND of 128 bits (representing double-precision floating-point elements) in "a" and "b", producing an intermediate 128-bit value, and set "ZF" to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set "ZF" to 0
  • _mm256_testz_ps Compute the bitwise AND of 256 bits (representing single-precision floating-point elements) in "a" and "b", producing an intermediate 256-bit value, and set "ZF" to 1 if the sign bit of each 32-bit element in the intermediate value is zero, otherwise set "ZF" to 0
  • _mm_testz_ps Compute the bitwise AND of 128 bits (representing single-precision floating-point elements) in "a" and "b", producing an intermediate 128-bit value, and set "ZF" to 1 if the sign bit of each 32-bit element in the intermediate value is zero, otherwise set "ZF" to 0
  • _mm256_testz_si256 Compute the bitwise AND of 256 bits (representing integer data) in "a" and "b", and set "ZF" to 1 if the result is zero, otherwise set "ZF" to 0

U

  • _mm256_undefined_pd Return vector of type __m256d with undefined elements.
  • _mm256_undefined_ps Return vector of type __m256 with undefined elements.
  • _mm256_undefined_si256 Return vector of type __m256i with undefined elements.
  • _mm256_unpackhi_pd Unpack and interleave double-precision floating-point elements from the high half of each 128-bit lane in "a" and "b"
  • _mm256_unpackhi_ps Unpack and interleave single-precision floating-point elements from the high half of each 128-bit lane in "a" and "b"
  • _mm256_unpacklo_pd Unpack and interleave double-precision floating-point elements from the low half of each 128-bit lane in "a" and "b"
  • _mm256_unpacklo_ps Unpack and interleave single-precision floating-point elements from the low half of each 128-bit lane in "a" and "b"

X

  • _mm256_xor_pd Compute the bitwise XOR of packed double-precision floating-point elements in "a" and "b"
  • _mm256_xor_ps Compute the bitwise XOR of packed single-precision floating-point elements in "a" and "b"

Z

  • _mm256_zeroall Zero the contents of all XMM or YMM registers.
  • _mm256_zeroupper Zero the upper 128 bits of all YMM registers; the lower 128-bits of the registers are unmodified
  • _mm256_zextpd128_pd256 Casts vector of type __m128d to type __m256d; the upper 128 bits of the result are zeroed
  • _mm256_zextps128_ps256 Casts vector of type __m128 to type __m256; the upper 128 bits of the result are zeroed
  • _mm256_zextsi128_si256 Casts vector of type __m128i to type __m256i; the upper 128 bits of the result are zeroed


AVX2

A B C E H I M O P S U X

A

  • _mm256_abs_epi8 Compute the absolute value of packed 8-bit integers in "a", and store the unsigned results in "dst"
  • _mm256_abs_epi16 Compute the absolute value of packed 16-bit integers in "a", and store the unsigned results in "dst"
  • _mm256_abs_epi32 Compute the absolute value of packed 32-bit integers in "a", and store the unsigned results in "dst"
  • _mm256_add_epi8 Add packed 8-bit integers in "a" and "b", and store the results in "dst"
  • _mm256_add_epi16 Add packed 16-bit integers in "a" and "b", and store the results in "dst"
  • _mm256_add_epi32 Add packed 32-bit integers in "a" and "b", and store the results in "dst"
  • _mm256_add_epi64 Add packed 64-bit integers in "a" and "b", and store the results in "dst"
  • _mm256_adds_epi8 Add packed 8-bit integers in "a" and "b" using saturation, and store the results in "dst"
  • _mm256_adds_epi16 Add packed 16-bit integers in "a" and "b" using saturation, and store the results in "dst"
  • _mm256_adds_epu8 Add packed unsigned 8-bit integers in "a" and "b" using saturation
  • _mm256_adds_epu16 Add packed unsigned 16-bit integers in "a" and "b" using saturation
  • _mm256_alignr_epi8 Concatenate pairs of 16-byte blocks in "a" and "b" into a 32-byte temporary result, shift the result right by "count" bytes, and store the low 16 bytes in "dst"
  • _mm256_and_si256 Compute the bitwise AND of 256 bits (representing integer data) in "a" and "b"
  • _mm256_andnot_si256 Compute the bitwise NOT of 256 bits (representing integer data) in "a" and then AND with "b"
  • _mm256_avg_epu8 Average packed unsigned 8-bit integers in "a" and "b", and store the results in "dst"
  • _mm256_avg_epu16 Average packed unsigned 16-bit integers in "a" and "b", and store the results in "dst"

B

  • _mm256_blend_epi16 Blend packed 16-bit integers from "a" and "b" within 128-bit lanes using control mask "imm8"
  • _mm_blend_epi32 Blend packed 32-bit integers from "a" and "b" using control mask "imm8"
  • _mm256_blend_epi32 Blend packed 32-bit integers from "a" and "b" using control mask "imm8"
  • _mm256_blendv_epi8 Blend packed 8-bit integers from "a" and "b" using "mask", and store the results in "dst"
  • _mm_broadcastb_epi8 Broadcast the low packed 8-bit integer from "a" to all elements of "dst"
  • _mm256_broadcastb_epi8 Broadcast the low packed 8-bit integer from "a" to all elements of "dst"
  • _mm_broadcastd_epi32 Broadcast the low packed 32-bit integer from "a" to all elements of "dst"
  • _mm256_broadcastd_epi32 Broadcast the low packed 32-bit integer from "a" to all elements of "dst"
  • _mm_broadcastq_epi64 Broadcast the low packed 64-bit integer from "a" to all elements of "dst"
  • _mm256_broadcastq_epi64 Broadcast the low packed 64-bit integer from "a" to all elements of "dst"
  • _mm_broadcastsd_pd Broadcast the low double-precision floating-point element from "a" to all elements of "dst"
  • _mm256_broadcastsd_pd Broadcast the low double-precision floating-point element from "a" to all elements of "dst"
  • _mm_broadcastsi128_si256 Broadcast 128 bits of integer data from "a" to all 128-bit lanes in "dst"
  • _mm256_broadcastsi128_si256 Broadcast 128 bits of integer data from "a" to all 128-bit lanes in "dst"
  • _mm_broadcastss_ps Broadcast the low single-precision floating-point element from "a" to all elements of "dst"
  • _mm256_broadcastss_ps Broadcast the low single-precision floating-point element from "a" to all elements of "dst"
  • _mm_broadcastw_epi16 Broadcast the low packed 16-bit integer from "a" to all elements of "dst"
  • _mm256_broadcastw_epi16 Broadcast the low packed 16-bit integer from "a" to all elements of "dst"
  • _mm256_bslli_epi128 Shift 128-bit lanes in "a" left by "imm8" bytes while shifting in zeros
  • _mm256_bsrli_epi128 Shift 128-bit lanes in "a" right by "imm8" bytes while shifting in zeros

C

  • _mm256_cmpeq_epi8 Compare packed 8-bit integers in "a" and "b" for equality, and store the results in "dst"
  • _mm256_cmpeq_epi16 Compare packed 16-bit integers in "a" and "b" for equality, and store the results in "dst"
  • _mm256_cmpeq_epi32 Compare packed 32-bit integers in "a" and "b" for equality, and store the results in "dst"
  • _mm256_cmpeq_epi64 Compare packed 64-bit integers in "a" and "b" for equality, and store the results in "dst"
  • _mm256_cmpgt_epi8 Compare packed 8-bit integers in "a" and "b" for greater-than, and store the results in "dst"
  • _mm256_cmpgt_epi16 Compare packed 16-bit integers in "a" and "b" for greater-than, and store the results in "dst"
  • _mm256_cmpgt_epi32 Compare packed 32-bit integers in "a" and "b" for greater-than, and store the results in "dst"
  • _mm256_cmpgt_epi64 Compare packed 64-bit integers in "a" and "b" for greater-than, and store the results in "dst"
  • _mm256_cvtepi16_epi32 Sign extend packed 16-bit integers in "a" to packed 32-bit integers
  • _mm256_cvtepi16_epi64 Sign extend packed 16-bit integers in "a" to packed 64-bit integers
  • _mm256_cvtepi32_epi64 Sign extend packed 32-bit integers in "a" to packed 64-bit integers
  • _mm256_cvtepi8_epi16 Sign extend packed 8-bit integers in "a" to packed 16-bit integers
  • _mm256_cvtepi8_epi32 Sign extend packed 8-bit integers in "a" to packed 32-bit integers
  • _mm256_cvtepi8_epi64 Sign extend packed 8-bit integers in the low 8 bytes of "a" to packed 64-bit integers
  • _mm256_cvtepu16_epi32 Zero extend packed unsigned 16-bit integers in "a" to packed 32-bit integers
  • _mm256_cvtepu16_epi64 Zero extend packed unsigned 16-bit integers in "a" to packed 64-bit integers
  • _mm256_cvtepu32_epi64 Zero extend packed unsigned 32-bit integers in "a" to packed 64-bit integers
  • _mm256_cvtepu8_epi16 Zero extend packed unsigned 8-bit integers in "a" to packed 16-bit integers
  • _mm256_cvtepu8_epi32 Zero extend packed unsigned 8-bit integers in "a" to packed 32-bit integers
  • _mm256_cvtepu8_epi64 Zero extend packed unsigned 8-bit integers in the low 8 byte sof "a" to packed 64-bit integers
  • _mm256_cvtsd_f64 Copy the lower double-precision floating-point element of "a" to "dst"
  • _mm256_cvtsi256_si32 Copy the lower 32-bit integer in "a" to "dst".

E

  • _mm256_extract_epi8 Extract an 8-bit integer from "a", selected with "index", and store the result in "dst"
  • _mm256_extract_epi16 Extract a 16-bit integer from "a", selected with "index", and store the result in "dst"
  • _mm256_extracti128_si256 Extract 128 bits (composed of integer data) from "a", selected with "imm8"

H

  • _mm256_hadd_epi16 Horizontally add adjacent pairs of 16-bit integers in "a" and "b", and pack the signed 16-bit results in "dst"
  • _mm256_hadd_epi32 Horizontally add adjacent pairs of 32-bit integers in "a" and "b", and pack the signed 32-bit results in "dst"
  • _mm256_hadds_epi16 Horizontally add adjacent pairs of 16-bit integers in "a" and "b" using saturation, and pack the signed 16-bit results in "dst"
  • _mm256_hsub_epi16 Horizontally subtract adjacent pairs of 16-bit integers in "a" and "b", and pack the signed 16-bit results in "dst"
  • _mm256_hsub_epi32 Horizontally subtract adjacent pairs of 32-bit integers in "a" and "b", and pack the signed 32-bit results in "dst"
  • _mm256_hsubs_epi16 Horizontally subtract adjacent pairs of 16-bit integers in "a" and "b" using saturation, and pack the signed 16-bit results in "dst"

I

  • _mm_i32gather_epi32 Gather 32-bit integers from memory using 32-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.
  • _mm256_i32gather_epi32 Gather 32-bit integers from memory using 32-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.
  • _mm_i32gather_epi64 Gather 64-bit integers from memory using 32-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.
  • _mm256_i32gather_epi64 Gather 64-bit integers from memory using 32-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.
  • _mm_i32gather_pd Gather double-precision floating-point elements from memory using 32-bit indices
  • _mm256_i32gather_pd Gather double-precision floating-point elements from memory using 32-bit indices
  • _mm_i32gather_ps Gather single-precision floating-point elements from memory using 32-bit indices
  • _mm256_i32gather_ps Gather single-precision floating-point elements from memory using 32-bit indices
  • _mm_i64gather_epi32 Gather 32-bit integers from memory using 64-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.
  • _mm256_i64gather_epi32 Gather 32-bit integers from memory using 64-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.
  • _mm_i64gather_epi64 Gather 64-bit integers from memory using 64-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.
  • _mm256_i64gather_epi64 Gather 64-bit integers from memory using 64-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.
  • _mm_i64gather_pd Gather double-precision floating-point elements from memory using 64-bit indices
  • _mm256_i64gather_pd Gather double-precision floating-point elements from memory using 64-bit indices
  • _mm_i64gather_ps Gather single-precision floating-point elements from memory using 64-bit indices
  • _mm256_i64gather_ps Gather single-precision floating-point elements from memory using 64-bit indices
  • _mm256_inserti128_si256 Copy "a" to "dst", then insert 128 bits (composed of integer data) from "b" into "dst" at the location specified by "imm8"

M

  • _mm256_madd_epi16 Multiply packed signed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers
  • _mm256_maddubs_epi16 Vertically multiply each unsigned 8-bit integer from "a" with the corresponding signed 8-bit integer from "b", producing intermediate signed 16-bit integers
  • _mm_mask_i32gather_epi32 Gather 32-bit integers from memory using 32-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8.
  • _mm256_mask_i32gather_epi32 Gather 32-bit integers from memory using 32-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8.
  • _mm_mask_i32gather_epi64 Gather 64-bit integers from memory using 32-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8.
  • _mm256_mask_i32gather_epi64 Gather 64-bit integers from memory using 32-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8.
  • _mm_mask_i32gather_pd Gather double-precision floating-point elements from memory using 32-bit indices
  • _mm256_mask_i32gather_pd Gather double-precision floating-point elements from memory using 32-bit indices
  • _mm_mask_i32gather_ps Gather single-precision floating-point elements from memory using 32-bit indices
  • _mm256_mask_i32gather_ps Gather single-precision floating-point elements from memory using 32-bit indices
  • _mm_mask_i64gather_epi32 Gather 32-bit integers from memory using 64-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8.
  • _mm256_mask_i64gather_epi32 Gather 32-bit integers from memory using 64-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8.
  • _mm_mask_i64gather_epi64 Gather 64-bit integers from memory using 64-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8.
  • _mm256_mask_i64gather_epi64 Gather 64-bit integers from memory using 64-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8.
  • _mm_mask_i64gather_pd Gather double-precision floating-point elements from memory using 64-bit indices
  • _mm256_mask_i64gather_pd Gather double-precision floating-point elements from memory using 64-bit indices
  • _mm_mask_i64gather_ps Gather single-precision floating-point elements from memory using 64-bit indices
  • _mm256_mask_i64gather_ps Gather single-precision floating-point elements from memory using 64-bit indices
  • _mm_maskload_epi32 Load packed 32-bit integers from memory into "dst" using "mask" (elements are zeroed out when the highest bit is not set in the corresponding element)
  • _mm256_maskload_epi32 Load packed 32-bit integers from memory into "dst" using "mask" (elements are zeroed out when the highest bit is not set in the corresponding element)
  • _mm_maskload_epi64 Load packed 64-bit integers from memory into "dst" using "mask" (elements are zeroed out when the highest bit is not set in the corresponding element)
  • _mm256_maskload_epi64 Load packed 64-bit integers from memory into "dst" using "mask" (elements are zeroed out when the highest bit is not set in the corresponding element)
  • _mm_maskstore_epi32 Store packed 32-bit integers from "a" into memory using "mask" (elements are not stored when the highest bit is not set in the corresponding element)
  • _mm256_maskstore_epi32 Store packed 32-bit integers from "a" into memory using "mask" (elements are not stored when the highest bit is not set in the corresponding element)
  • _mm_maskstore_epi64 Store packed 64-bit integers from "a" into memory using "mask" (elements are not stored when the highest bit is not set in the corresponding element)
  • _mm256_maskstore_epi64 Store packed 64-bit integers from "a" into memory using "mask" (elements are not stored when the highest bit is not set in the corresponding element)
  • _mm256_max_epi8 Compare packed 8-bit integers in "a" and "b", and store packed maximum values in "dst"
  • _mm256_max_epi16 Compare packed 16-bit integers in "a" and "b", and store packed maximum values in "dst"
  • _mm256_max_epi32 Compare packed 32-bit integers in "a" and "b", and store packed maximum values in "dst"
  • _mm256_max_epu8 Compare packed unsigned 8-bit integers in "a" and "b", and store packed maximum values in "dst"
  • _mm256_max_epu16 Compare packed unsigned 16-bit integers in "a" and "b", and store packed maximum values in "dst"
  • _mm256_max_epu32 Compare packed unsigned 32-bit integers in "a" and "b", and store packed maximum values in "dst"
  • _mm256_min_epi8 Compare packed 8-bit integers in "a" and "b", and store packed minimum values in "dst"
  • _mm256_min_epi16 Compare packed 16-bit integers in "a" and "b", and store packed minimum values in "dst"
  • _mm256_min_epi32 Compare packed 32-bit integers in "a" and "b", and store packed minimum values in "dst"
  • _mm256_min_epu8 Compare packed unsigned 8-bit integers in "a" and "b", and store packed minimum values in "dst"
  • _mm256_min_epu16 Compare packed unsigned 16-bit integers in "a" and "b", and store packed minimum values in "dst"
  • _mm256_min_epu32 Compare packed unsigned 32-bit integers in "a" and "b", and store packed minimum values in "dst"
  • _mm256_movemask_epi8 Create mask from the most significant bit of each 8-bit element in "a"
  • _mm256_mpsadbw_epu8 Compute the sum of absolute differences (SADs) of quadruplets of unsigned 8-bit integers in "a" compared to those in "b", and store the 16-bit results in "dst"
  • _mm256_mul_epi32 Multiply the low 32-bit integers from each packed 64-bit element in "a" and "b", and store the signed 64-bit results in "dst"
  • _mm256_mul_epu32 Multiply the low unsigned 32-bit integers from each packed 64-bit element in "a" and "b", and store the unsigned 64-bit results in "dst"
  • _mm256_mulhi_epi16 Multiply the packed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst"
  • _mm256_mulhi_epu16 Multiply the packed unsigned 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst"
  • _mm256_mulhrs_epi16 Multiply packed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers
  • _mm256_mullo_epi16 Multiply the packed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the low 16 bits of the intermediate integers in "dst"
  • _mm256_mullo_epi32 Multiply the packed 32-bit integers in "a" and "b", producing intermediate 64-bit integers, and store the low 32 bits of the intermediate integers in "dst"

O

  • _mm256_or_si256 Compute the bitwise OR of 256 bits (representing integer data) in "a" and "b"

P

  • _mm256_packs_epi16 Convert packed 16-bit integers from "a" and "b" to packed 8-bit integers using signed saturation
  • _mm256_packs_epi32 Convert packed 32-bit integers from "a" and "b" to packed 16-bit integers using signed saturation
  • _mm256_packus_epi16 Convert packed 16-bit integers from "a" and "b" to packed 8-bit integers using unsigned saturation
  • _mm256_packus_epi32 Convert packed 32-bit integers from "a" and "b" to packed 16-bit integers using unsigned saturation
  • _mm256_permute2x128_si256 Shuffle 128-bits (composed of integer data) selected by "imm8" from "a" and "b"
  • _mm256_permute4x64_epi64 Shuffle 64-bit integers in "a" across lanes using the control in "imm8"
  • _mm256_permute4x64_pd Shuffle double-precision floating-point elements in "a" across lanes using the control in "imm8"
  • _mm256_permutevar8x32_epi32 Shuffle 32-bit integers in "a" across lanes using the corresponding index in "idx"
  • _mm256_permutevar8x32_ps Shuffle single-precision floating-point elements in "a" across lanes using the corresponding index in "idx"

S

  • _mm256_sad_epu8 Compute the absolute differences of packed unsigned 8-bit integers in "a" and "b", then horizontally sum each consecutive 8 differences to produce four unsigned 16-bit integers, and pack these unsigned 16-bit integers in the low 16 bits of 64-bit elements in "dst"
  • _mm256_shuffle_epi8 Shuffle 8-bit integers in "a" within 128-bit lanes according to shuffle control mask in the corresponding 8-bit element of "b"
  • _mm256_shuffle_epi32 Shuffle 32-bit integers in "a" within 128-bit lanes using the control in "imm8"
  • _mm256_shufflehi_epi16 Shuffle 16-bit integers in the high 64 bits of 128-bit lanes of "a" using the control in "imm8"
  • _mm256_shufflelo_epi16 Shuffle 16-bit integers in the low 64 bits of 128-bit lanes of "a" using the control in "imm8"
  • _mm256_sign_epi8 Negate packed 8-bit integers in "a" when the corresponding signed 8-bit integer in "b" is negative
  • _mm256_sign_epi16 Negate packed 16-bit integers in "a" when the corresponding signed 16-bit integer in "b" is negative
  • _mm256_sign_epi32 Negate packed 32-bit integers in "a" when the corresponding signed 32-bit integer in "b" is negative
  • _mm256_sll_epi16 Shift packed 16-bit integers in "a" left by "count" while shifting in zeros
  • _mm256_sll_epi32 Shift packed 32-bit integers in "a" left by "count" while shifting in zeros
  • _mm256_sll_epi64 Shift packed 64-bit integers in "a" left by "count" while shifting in zeros
  • _mm256_slli_epi16 Shift packed 16-bit integers in "a" left by "imm8" while shifting in zeros
  • _mm256_slli_epi32 Shift packed 32-bit integers in "a" left by "imm8" while shifting in zeros
  • _mm256_slli_epi64 Shift packed 64-bit integers in "a" left by "imm8" while shifting in zeros
  • _mm256_slli_si256 Shift 128-bit lanes in "a" left by "imm8" bytes while shifting in zeros
  • _mm_sllv_epi32 Shift packed 32-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros
  • _mm256_sllv_epi32 Shift packed 32-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros
  • _mm_sllv_epi64 Shift packed 64-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros
  • _mm256_sllv_epi64 Shift packed 64-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros
  • _mm256_sra_epi16 Shift packed 16-bit integers in "a" right by "count" while shifting in sign bits
  • _mm256_sra_epi32 Shift packed 32-bit integers in "a" right by "count" while shifting in sign bits
  • _mm256_srai_epi16 Shift packed 16-bit integers in "a" right by "imm8" while shifting in sign bits
  • _mm256_srai_epi32 Shift packed 32-bit integers in "a" right by "imm8" while shifting in sign bits
  • _mm_srav_epi32 Shift packed 32-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits
  • _mm256_srav_epi32 Shift packed 32-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits
  • _mm256_srl_epi16 Shift packed 16-bit integers in "a" right by "count" while shifting in zeros
  • _mm256_srl_epi32 Shift packed 32-bit integers in "a" right by "count" while shifting in zeros
  • _mm256_srl_epi64 Shift packed 64-bit integers in "a" right by "count" while shifting in zeros
  • _mm256_srli_epi16 Shift packed 16-bit integers in "a" right by "imm8" while shifting in zeros
  • _mm256_srli_epi32 Shift packed 32-bit integers in "a" right by "imm8" while shifting in zeros
  • _mm256_srli_epi64 Shift packed 64-bit integers in "a" right by "imm8" while shifting in zeros
  • _mm256_srli_si256 Shift 128-bit lanes in "a" right by "imm8" bytes while shifting in zeros
  • _mm_srlv_epi32 Shift packed 32-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros
  • _mm256_srlv_epi32 Shift packed 32-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros
  • _mm_srlv_epi64 Shift packed 64-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros
  • _mm256_srlv_epi64 Shift packed 64-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros
  • _mm256_stream_load_si256 Load 256-bits of integer data from memory into "dst" using a non-temporal memory hint
  • _mm256_sub_epi8 Subtract packed 8-bit integers in "b" from packed 8-bit integers in "a"
  • _mm256_sub_epi16 Subtract packed 16-bit integers in "b" from packed 16-bit integers in "a"
  • _mm256_sub_epi32 Subtract packed 32-bit integers in "b" from packed 32-bit integers in "a"
  • _mm256_sub_epi64 Subtract packed 64-bit integers in "b" from packed 64-bit integers in "a"
  • _mm256_subs_epi8 Subtract packed 8-bit integers in "b" from packed 8-bit integers in "a" using saturation
  • _mm256_subs_epi16 Subtract packed 16-bit integers in "b" from packed 16-bit integers in "a" using saturation
  • _mm256_subs_epu8 Subtract packed unsigned 8-bit integers in "b" from packed unsigned 8-bit integers in "a" using saturation
  • _mm256_subs_epu16 Subtract packed unsigned 16-bit integers in "b" from packed unsigned 16-bit integers in "a" using saturation

U

  • _mm256_unpackhi_epi8 Unpack and interleave 8-bit integers from the high half of each 128-bit lane in "a" and "b"
  • _mm256_unpackhi_epi16 Unpack and interleave 16-bit integers from the high half of each 128-bit lane in "a" and "b"
  • _mm256_unpackhi_epi32 Unpack and interleave 32-bit integers from the high half of each 128-bit lane in "a" and "b"
  • _mm256_unpackhi_epi64 Unpack and interleave 64-bit integers from the high half of each 128-bit lane in "a" and "b"
  • _mm256_unpacklo_epi8 Unpack and interleave 8-bit integers from the low half of each 128-bit lane in "a" and "b"
  • _mm256_unpacklo_epi16 Unpack and interleave 16-bit integers from the low half of each 128-bit lane in "a" and "b"
  • _mm256_unpacklo_epi32 Unpack and interleave 32-bit integers from the low half of each 128-bit lane in "a" and "b"
  • _mm256_unpacklo_epi64 Unpack and interleave 64-bit integers from the low half of each 128-bit lane in "a" and "b"

X

  • _mm256_xor_si256 Compute the bitwise XOR of 256 bits (representing integer data) in "a" and "b"


FMA

M N

M

  • _mm_fmadd_pd Multiply packed double-precision floating-point elements in "a" and "b", add the intermediate result to packed elements in "c"
  • _mm256_fmadd_pd Multiply packed double-precision floating-point elements in "a" and "b", add the intermediate result to packed elements in "c"
  • _mm_fmadd_ps Multiply packed single-precision floating-point elements in "a" and "b", add the intermediate result to packed elements in "c"
  • _mm256_fmadd_ps Multiply packed single-precision floating-point elements in "a" and "b", add the intermediate result to packed elements in "c"
  • _mm_fmadd_sd Multiply the lower double-precision floating-point elements in "a" and "b", and add the intermediate result to the lower element in "c"
  • _mm_fmadd_ss Multiply the lower single-precision floating-point elements in "a" and "b", and add the intermediate result to the lower element in "c"
  • _mm_fmaddsub_pd Multiply packed double-precision floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result
  • _mm256_fmaddsub_pd Multiply packed double-precision floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result
  • _mm_fmaddsub_ps Multiply packed single-precision floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result
  • _mm256_fmaddsub_ps Multiply packed single-precision floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result
  • _mm_fmsub_pd Multiply packed double-precision floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result
  • _mm256_fmsub_pd Multiply packed double-precision floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result
  • _mm_fmsub_ps Multiply packed single-precision floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result
  • _mm256_fmsub_ps Multiply packed single-precision floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result
  • _mm_fmsub_sd Multiply the lower double-precision floating-point elements in "a" and "b", and subtract the lower element in "c" from the intermediate result
  • _mm_fmsub_ss Multiply the lower single-precision floating-point elements in "a" and "b", and subtract the lower element in "c" from the intermediate result
  • _mm_fmsubadd_pd Multiply packed double-precision floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result
  • _mm256_fmsubadd_pd Multiply packed double-precision floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result
  • _mm_fmsubadd_ps Multiply packed single-precision floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result
  • _mm256_fmsubadd_ps Multiply packed single-precision floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result

N

  • _mm_fnmadd_pd Multiply packed double-precision floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c"
  • _mm256_fnmadd_pd Multiply packed double-precision floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c"
  • _mm_fnmadd_ps Multiply packed single-precision floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c"
  • _mm256_fnmadd_ps Multiply packed single-precision floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c"
  • _mm_fnmadd_sd Multiply the lower double-precision floating-point elements in "a" and "b", and add the negated intermediate result to the lower element in "c"
  • _mm_fnmadd_ss Multiply the lower single-precision floating-point elements in "a" and "b", and add the negated intermediate result to the lower element in "c"
  • _mm_fnmsub_pd Multiply packed double-precision floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result
  • _mm256_fnmsub_pd Multiply packed double-precision floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result
  • _mm_fnmsub_ps Multiply packed single-precision floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result
  • _mm256_fnmsub_ps Multiply packed single-precision floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result
  • _mm_fnmsub_sd Multiply the lower double-precision floating-point elements in "a" and "b", and subtract the lower element in "c" from the negated intermediate result
  • _mm_fnmsub_ss Multiply the lower single-precision floating-point elements in "a" and "b", and subtract the lower element in "c" from the negated intermediate result


MMX

A C E F M O P S T U X

A

  • _mm_add_pi8 Add packed 8-bit integers in "a" and "b", and store the results in "dst"
  • _mm_add_pi16 Add packed 16-bit integers in "a" and "b", and store the results in "dst"
  • _mm_add_pi32 Add packed 32-bit integers in "a" and "b", and store the results in "dst"
  • _mm_adds_pi8 Add packed 8-bit integers in "a" and "b" using saturation, and store the results in "dst"
  • _mm_adds_pi16 Add packed 16-bit integers in "a" and "b" using saturation, and store the results in "dst"
  • _mm_adds_pu8 Add packed unsigned 8-bit integers in "a" and "b" using saturation
  • _mm_adds_pu16 Add packed unsigned 16-bit integers in "a" and "b" using saturation
  • _mm_and_si64 Compute the bitwise AND of 64 bits (representing integer data) in "a" and "b"
  • _mm_andnot_si64 Compute the bitwise NOT of 64 bits (representing integer data) in "a" and then AND with "b"

C

  • _mm_cmpeq_pi8 Compare packed 8-bit integers in "a" and "b" for equality, and store the results in "dst"
  • _mm_cmpeq_pi16 Compare packed 16-bit integers in "a" and "b" for equality, and store the results in "dst"
  • _mm_cmpeq_pi32 Compare packed 32-bit integers in "a" and "b" for equality, and store the results in "dst"
  • _mm_cmpgt_pi8 Compare packed 8-bit integers in "a" and "b" for greater-than, and store the results in "dst"
  • _mm_cmpgt_pi16 Compare packed 16-bit integers in "a" and "b" for greater-than, and store the results in "dst"
  • _mm_cmpgt_pi32 Compare packed 32-bit integers in "a" and "b" for greater-than, and store the results in "dst"
  • _mm_cvtm64_si64 Copy 64-bit integer "a" to "dst".
  • _mm_cvtsi32_si64 Copy 32-bit integer "a" to the lower elements of "dst", and zero the upper element of "dst"
  • _mm_cvtsi64_m64 Copy 64-bit integer "a" to "dst".
  • _mm_cvtsi64_si32 Copy the lower 32-bit integer in "a" to "dst".

E

  • _m_empty Empty the MMX state, which marks the x87 FPU registers as available for use by x87 instructions
  • _mm_empty Empty the MMX state, which marks the x87 FPU registers as available for use by x87 instructions

F

  • _m_from_int Copy 32-bit integer "a" to the lower elements of "dst", and zero the upper element of "dst"
  • _m_from_int64 Copy 64-bit integer "a" to "dst".

M

  • _mm_madd_pi16 Multiply packed 16-bit integers in "a" and "b", producing intermediate 32-bit integers
  • _mm_mulhi_pi16 Multiply the packed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst"
  • _mm_mullo_pi16 Multiply the packed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the low 16 bits of the intermediate integers in "dst"

O

  • _mm_or_si64 Compute the bitwise OR of 64 bits (representing integer data) in "a" and "b"

P

  • _mm_packs_pi16 Convert packed 16-bit integers from "a" and "b" to packed 8-bit integers using signed saturation
  • _mm_packs_pi32 Convert packed 32-bit integers from "a" and "b" to packed 16-bit integers using signed saturation
  • _mm_packs_pu16 Convert packed 16-bit integers from "a" and "b" to packed 8-bit integers using unsigned saturation
  • _m_packssdw Convert packed 32-bit integers from "a" and "b" to packed 16-bit integers using signed saturation
  • _m_packsswb Convert packed 16-bit integers from "a" and "b" to packed 8-bit integers using signed saturation
  • _m_packuswb Convert packed 16-bit integers from "a" and "b" to packed 8-bit integers using unsigned saturation
  • _m_paddb Add packed 8-bit integers in "a" and "b", and store the results in "dst"
  • _m_paddd Add packed 32-bit integers in "a" and "b", and store the results in "dst"
  • _m_paddsb Add packed 8-bit integers in "a" and "b" using saturation, and store the results in "dst"
  • _m_paddsw Add packed 16-bit integers in "a" and "b" using saturation, and store the results in "dst"
  • _m_paddusb Add packed unsigned 8-bit integers in "a" and "b" using saturation
  • _m_paddusw Add packed unsigned 16-bit integers in "a" and "b" using saturation
  • _m_paddw Add packed 16-bit integers in "a" and "b", and store the results in "dst"
  • _m_pand Compute the bitwise AND of 64 bits (representing integer data) in "a" and "b"
  • _m_pandn Compute the bitwise NOT of 64 bits (representing integer data) in "a" and then AND with "b"
  • _m_pcmpeqb Compare packed 8-bit integers in "a" and "b" for equality, and store the results in "dst"
  • _m_pcmpeqd Compare packed 32-bit integers in "a" and "b" for equality, and store the results in "dst"
  • _m_pcmpeqw Compare packed 16-bit integers in "a" and "b" for equality, and store the results in "dst"
  • _m_pcmpgtb Compare packed 8-bit integers in "a" and "b" for greater-than, and store the results in "dst"
  • _m_pcmpgtd Compare packed 32-bit integers in "a" and "b" for greater-than, and store the results in "dst"
  • _m_pcmpgtw Compare packed 16-bit integers in "a" and "b" for greater-than, and store the results in "dst"
  • _m_pmaddwd Multiply packed 16-bit integers in "a" and "b", producing intermediate 32-bit integers
  • _m_pmulhw Multiply the packed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst"
  • _m_pmullw Multiply the packed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the low 16 bits of the intermediate integers in "dst"
  • _m_por Compute the bitwise OR of 64 bits (representing integer data) in "a" and "b"
  • _m_pslld Shift packed 32-bit integers in "a" left by "count" while shifting in zeros
  • _m_pslldi Shift packed 32-bit integers in "a" left by "imm8" while shifting in zeros
  • _m_psllq Shift 64-bit integer "a" left by "count" while shifting in zeros, and store the result in "dst"
  • _m_psllqi Shift 64-bit integer "a" left by "imm8" while shifting in zeros, and store the result in "dst"
  • _m_psllw Shift packed 16-bit integers in "a" left by "count" while shifting in zeros
  • _m_psllwi Shift packed 16-bit integers in "a" left by "imm8" while shifting in zeros
  • _m_psrad Shift packed 32-bit integers in "a" right by "count" while shifting in sign bits
  • _m_psradi Shift packed 32-bit integers in "a" right by "imm8" while shifting in sign bits
  • _m_psraw Shift packed 16-bit integers in "a" right by "count" while shifting in sign bits
  • _m_psrawi Shift packed 16-bit integers in "a" right by "imm8" while shifting in sign bits
  • _m_psrld Shift packed 32-bit integers in "a" right by "count" while shifting in zeros
  • _m_psrldi Shift packed 32-bit integers in "a" right by "imm8" while shifting in zeros
  • _m_psrlq Shift 64-bit integer "a" right by "count" while shifting in zeros
  • _m_psrlqi Shift 64-bit integer "a" right by "imm8" while shifting in zeros, and store the result in "dst"
  • _m_psrlw Shift packed 16-bit integers in "a" right by "count" while shifting in zeros
  • _m_psrlwi Shift packed 16-bit integers in "a" right by "imm8" while shifting in zeros
  • _m_psubb Subtract packed 8-bit integers in "b" from packed 8-bit integers in "a"
  • _m_psubd Subtract packed 32-bit integers in "b" from packed 32-bit integers in "a"
  • _m_psubsb Subtract packed 8-bit integers in "b" from packed 8-bit integers in "a" using saturation
  • _m_psubsw Subtract packed 16-bit integers in "b" from packed 16-bit integers in "a" using saturation
  • _m_psubusb Subtract packed unsigned 8-bit integers in "b" from packed unsigned 8-bit integers in "a" using saturation
  • _m_psubusw Subtract packed unsigned 16-bit integers in "b" from packed unsigned 16-bit integers in "a" using saturation
  • _m_psubw Subtract packed 16-bit integers in "b" from packed 16-bit integers in "a"
  • _m_punpckhbw Unpack and interleave 8-bit integers from the high half of "a" and "b"
  • _m_punpckhdq Unpack and interleave 32-bit integers from the high half of "a" and "b"
  • _m_punpckhwd Unpack and interleave 16-bit integers from the high half of "a" and "b"
  • _m_punpcklbw Unpack and interleave 8-bit integers from the low half of "a" and "b"
  • _m_punpckldq Unpack and interleave 32-bit integers from the low half of "a" and "b"
  • _m_punpcklwd Unpack and interleave 16-bit integers from the low half of "a" and "b"
  • _m_pxor Compute the bitwise OR of 64 bits (representing integer data) in "a" and "b"

S

  • _mm_set_pi8 Set packed 8-bit integers in "dst" with the supplied values in reverse order
  • _mm_set_pi16 Set packed 16-bit integers in "dst" with the supplied values.
  • _mm_set_pi32 Set packed 32-bit integers in "dst" with the supplied values.
  • _mm_set1_pi8 Broadcast 8-bit integer "a" to all elements of "dst".
  • _mm_set1_pi16 Broadcast 16-bit integer "a" to all all elements of "dst".
  • _mm_set1_pi32 Broadcast 32-bit integer "a" to all elements of "dst".
  • _mm_setr_pi8 Set packed 8-bit integers in "dst" with the supplied values in reverse order
  • _mm_setr_pi16 Set packed 16-bit integers in "dst" with the supplied values in reverse order
  • _mm_setr_pi32 Set packed 32-bit integers in "dst" with the supplied values in reverse order
  • _mm_setzero_si64 Return vector of type __m64 with all elements set to zero.
  • _mm_sll_pi16 Shift packed 16-bit integers in "a" left by "count" while shifting in zeros
  • _mm_sll_pi32 Shift packed 32-bit integers in "a" left by "count" while shifting in zeros
  • _mm_sll_si64 Shift 64-bit integer "a" left by "count" while shifting in zeros, and store the result in "dst"
  • _mm_slli_pi16 Shift packed 16-bit integers in "a" left by "imm8" while shifting in zeros
  • _mm_slli_pi32 Shift packed 32-bit integers in "a" left by "imm8" while shifting in zeros
  • _mm_slli_si64 Shift 64-bit integer "a" left by "imm8" while shifting in zeros, and store the result in "dst"
  • _mm_sra_pi16 Shift packed 16-bit integers in "a" right by "count" while shifting in sign bits
  • _mm_sra_pi32 Shift packed 32-bit integers in "a" right by "count" while shifting in sign bits
  • _mm_srai_pi16 Shift packed 16-bit integers in "a" right by "imm8" while shifting in sign bits
  • _mm_srai_pi32 Shift packed 32-bit integers in "a" right by "imm8" while shifting in sign bits
  • _mm_srl_pi16 Shift packed 16-bit integers in "a" right by "count" while shifting in zeros
  • _mm_srl_pi32 Shift packed 32-bit integers in "a" right by "count" while shifting in zeros
  • _mm_srl_si64 Shift 64-bit integer "a" right by "count" while shifting in zeros
  • _mm_srli_pi16 Shift packed 16-bit integers in "a" right by "imm8" while shifting in zeros
  • _mm_srli_pi32 Shift packed 32-bit integers in "a" right by "imm8" while shifting in zeros
  • _mm_srli_si64 Shift 64-bit integer "a" right by "imm8" while shifting in zeros, and store the result in "dst"
  • _mm_sub_pi8 Subtract packed 8-bit integers in "b" from packed 8-bit integers in "a"
  • _mm_sub_pi16 Subtract packed 16-bit integers in "b" from packed 16-bit integers in "a"
  • _mm_sub_pi32 Subtract packed 32-bit integers in "b" from packed 32-bit integers in "a"
  • _mm_subs_pi8 Subtract packed 8-bit integers in "b" from packed 8-bit integers in "a" using saturation
  • _mm_subs_pi16 Subtract packed 16-bit integers in "b" from packed 16-bit integers in "a" using saturation
  • _mm_subs_pu8 Subtract packed unsigned 8-bit integers in "b" from packed unsigned 8-bit integers in "a" using saturation
  • _mm_subs_pu16 Subtract packed unsigned 16-bit integers in "b" from packed unsigned 16-bit integers in "a" using saturation

T

  • _m_to_int Copy the lower 32-bit integer in "a" to "dst".
  • _m_to_int64 Copy 64-bit integer "a" to "dst".

U

  • _mm_unpackhi_pi8 Unpack and interleave 8-bit integers from the high half of "a" and "b"
  • _mm_unpackhi_pi16 Unpack and interleave 16-bit integers from the high half of "a" and "b"
  • _mm_unpackhi_pi32 Unpack and interleave 32-bit integers from the high half of "a" and "b"
  • _mm_unpacklo_pi8 Unpack and interleave 8-bit integers from the low half of "a" and "b"
  • _mm_unpacklo_pi16 Unpack and interleave 16-bit integers from the low half of "a" and "b"
  • _mm_unpacklo_pi32 Unpack and interleave 32-bit integers from the low half of "a" and "b"

X

  • _mm_xor_si64 Compute the bitwise XOR of 64 bits (representing integer data) in "a" and "b"


SSE

A C D E F G I L M O P R S T U X

A

  • _mm_add_ps Add packed single-precision floating-point elements in "a" and "b"
  • _mm_add_ss Add the lower single-precision floating-point element in "a" and "b"
  • _mm_and_ps Compute the bitwise AND of packed single-precision floating-point elements in "a" and "b"
  • _mm_andnot_ps Compute the bitwise NOT of packed single-precision floating-point elements in "a" and then AND with "b"
  • _mm_avg_pu8 Average packed unsigned 8-bit integers in "a" and "b", and store the results in "dst"
  • _mm_avg_pu16 Average packed unsigned 16-bit integers in "a" and "b", and store the results in "dst"

C

  • _mm_cmpeq_ps Compare packed single-precision floating-point elements in "a" and "b" for equality
  • _mm_cmpeq_ss Compare the lower single-precision floating-point elements in "a" and "b" for equality
  • _mm_cmpge_ps Compare packed single-precision floating-point elements in "a" and "b" for greater-than-or-equal
  • _mm_cmpge_ss Compare the lower single-precision floating-point elements in "a" and "b" for greater-than-or-equal
  • _mm_cmpgt_ps Compare packed single-precision floating-point elements in "a" and "b" for greater-than
  • _mm_cmpgt_ss Compare the lower single-precision floating-point elements in "a" and "b" for greater-than
  • _mm_cmple_ps Compare packed single-precision floating-point elements in "a" and "b" for less-than-or-equal
  • _mm_cmple_ss Compare the lower single-precision floating-point elements in "a" and "b" for less-than-or-equal
  • _mm_cmplt_ps Compare packed single-precision floating-point elements in "a" and "b" for less-than
  • _mm_cmplt_ss Compare the lower single-precision floating-point elements in "a" and "b" for less-than
  • _mm_cmpneq_ps Compare packed single-precision floating-point elements in "a" and "b" for not-equal
  • _mm_cmpneq_ss Compare the lower single-precision floating-point elements in "a" and "b" for not-equal
  • _mm_cmpnge_ps Compare packed single-precision floating-point elements in "a" and "b" for not-greater-than-or-equal
  • _mm_cmpnge_ss Compare the lower single-precision floating-point elements in "a" and "b" for not-greater-than-or-equal
  • _mm_cmpngt_ps Compare packed single-precision floating-point elements in "a" and "b" for not-greater-than
  • _mm_cmpngt_ss Compare the lower single-precision floating-point elements in "a" and "b" for not-greater-than
  • _mm_cmpnle_ps Compare packed single-precision floating-point elements in "a" and "b" for not-less-than-or-equal
  • _mm_cmpnle_ss Compare the lower single-precision floating-point elements in "a" and "b" for not-less-than-or-equal
  • _mm_cmpnlt_ps Compare packed single-precision floating-point elements in "a" and "b" for not-less-than
  • _mm_cmpnlt_ss Compare the lower single-precision floating-point elements in "a" and "b" for not-less-than
  • _mm_cmpord_ps Compare packed single-precision floating-point elements in "a" and "b" to see if neither is NaN
  • _mm_cmpord_ss Compare the lower single-precision floating-point elements in "a" and "b" to see if neither is NaN
  • _mm_cmpunord_ps Compare packed single-precision floating-point elements in "a" and "b" to see if either is NaN
  • _mm_cmpunord_ss Compare the lower single-precision floating-point elements in "a" and "b" to see if either is NaN
  • _mm_comieq_ss Compare the lower single-precision floating-point element in "a" and "b" for equality
  • _mm_comige_ss Compare the lower single-precision floating-point element in "a" and "b" for greater-than-or-equal
  • _mm_comigt_ss Compare the lower single-precision floating-point element in "a" and "b" for greater-than
  • _mm_comile_ss Compare the lower single-precision floating-point element in "a" and "b" for less-than-or-equal
  • _mm_comilt_ss Compare the lower single-precision floating-point element in "a" and "b" for less-than
  • _mm_comineq_ss Compare the lower single-precision floating-point element in "a" and "b" for not-equal
  • _mm_cvt_pi2ps Convert packed 32-bit integers in "b" to packed single-precision floating-point elements
  • _mm_cvt_ps2pi Convert packed single-precision floating-point elements in "a" to packed 32-bit integers
  • _mm_cvt_si2ss Convert the 32-bit integer "b" to a single-precision floating-point element
  • _mm_cvt_ss2si Convert the lower single-precision floating-point element in "a" to a 32-bit integer
  • _mm_cvtpi16_ps Convert packed 16-bit integers in "a" to packed single-precision floating-point elements
  • _mm_cvtpi32_ps Convert packed 32-bit integers in "b" to packed single-precision floating-point elements
  • _mm_cvtpi32x2_ps Convert packed 32-bit integers in "a" to packed single-precision floating-point elements
  • _mm_cvtpi8_ps Convert the lower packed 8-bit integers in "a" to packed single-precision floating-point elements
  • _mm_cvtps_pi8 Convert packed single-precision floating-point elements in "a" to packed 8-bit integers
  • _mm_cvtps_pi16 Convert packed single-precision floating-point elements in "a" to packed 16-bit integers
  • _mm_cvtps_pi32 Convert packed single-precision floating-point elements in "a" to packed 32-bit integers
  • _mm_cvtpu16_ps Convert packed unsigned 16-bit integers in "a" to packed single-precision floating-point elements
  • _mm_cvtpu8_ps Convert the lower packed unsigned 8-bit integers in "a" to packed single-precision floating-point elements
  • _mm_cvtsi32_ss Convert the 32-bit integer "b" to a single-precision floating-point element
  • _mm_cvtsi64_ss Convert the 64-bit integer "b" to a single-precision floating-point element
  • _mm_cvtss_f32 Copy the lower single-precision floating-point element of "a" to "dst"
  • _mm_cvtss_si32 Convert the lower single-precision floating-point element in "a" to a 32-bit integer
  • _mm_cvtss_si64 Convert the lower single-precision floating-point element in "a" to a 64-bit integer
  • _mm_cvtt_ps2pi Convert packed single-precision floating-point elements in "a" to packed 32-bit integers with truncation
  • _mm_cvtt_ss2si Convert the lower single-precision floating-point element in "a" to a 32-bit integer with truncation
  • _mm_cvttps_pi32 Convert packed single-precision floating-point elements in "a" to packed 32-bit integers with truncation
  • _mm_cvttss_si32 Convert the lower single-precision floating-point element in "a" to a 32-bit integer with truncation
  • _mm_cvttss_si64 Convert the lower single-precision floating-point element in "a" to a 64-bit integer with truncation

D

  • _mm_div_ps Divide packed single-precision floating-point elements in "a" by packed elements in "b"
  • _mm_div_ss Divide the lower single-precision floating-point element in "a" by the lower single-precision floating-point element in "b"

E

  • _mm_extract_pi16 Extract a 16-bit integer from "a", selected with "imm8", and store the result in the lower element of "dst"

F

  • _mm_free Free aligned memory that was allocated with "_mm_malloc".

G

  • _MM_GET_EXCEPTION_MASK Macro: Get the exception mask bits from the MXCSR control and status register
  • _MM_GET_EXCEPTION_STATE Macro: Get the exception state bits from the MXCSR control and status register
  • _MM_GET_FLUSH_ZERO_MODE Macro: Get the flush zero bits from the MXCSR control and status register
  • _MM_GET_ROUNDING_MODE Macro: Get the rounding mode bits from the MXCSR control and status register
  • _mm_getcsr Get the unsigned 32-bit value of the MXCSR control and status register

I

  • _mm_insert_pi16 Copy "a" to "dst", and insert the 16-bit integer "i" into "dst" at the location specified by "imm8"

L

  • _mm_load_ps Load 128-bits (composed of 4 packed single-precision floating-point elements) from memory into "dst"
  • _mm_load_ps1 Load a single-precision floating-point element from memory into all elements of "dst"
  • _mm_load_ss Load a single-precision floating-point element from memory into the lower of "dst", and zero the upper 3 elements
  • _mm_load1_ps Load a single-precision floating-point element from memory into all elements of "dst"
  • _mm_loadh_pi Load 2 single-precision floating-point elements from memory into the upper 2 elements of "dst", and copy the lower 2 elements from "a" to "dst"
  • _mm_loadl_pi Load 2 single-precision floating-point elements from memory into the lower 2 elements of "dst", and copy the upper 2 elements from "a" to "dst"
  • _mm_loadr_ps Load 4 single-precision floating-point elements from memory into "dst" in reverse order
  • _mm_loadu_ps Load 128-bits (composed of 4 packed single-precision floating-point elements) from memory into "dst"
  • _mm_loadu_si16 Load unaligned 16-bit integer from memory into the first element of "dst"
  • _mm_loadu_si64 Load unaligned 64-bit integer from memory into the first element of "dst"

M

  • _mm_malloc Allocate "size" bytes of memory, aligned to the alignment specified in "align"
  • _mm_maskmove_si64 Conditionally store 8-bit integer elements from "a" into memory using "mask" (elements are not stored when the highest bit is not set in the corresponding element) and a non-temporal memory hint
  • _m_maskmovq Conditionally store 8-bit integer elements from "a" into memory using "mask" (elements are not stored when the highest bit is not set in the corresponding element)
  • _mm_max_pi16 Compare packed 16-bit integers in "a" and "b", and store packed maximum values in "dst"
  • _mm_max_ps Compare packed single-precision floating-point elements in "a" and "b", and store packed maximum values in "dst"
  • _mm_max_pu8 Compare packed unsigned 8-bit integers in "a" and "b", and store packed maximum values in "dst"
  • _mm_max_ss Compare the lower single-precision floating-point elements in "a" and "b", store the maximum value in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst"
  • _mm_min_pi16 Compare packed 16-bit integers in "a" and "b", and store packed minimum values in "dst"
  • _mm_min_ps Compare packed single-precision floating-point elements in "a" and "b", and store packed minimum values in "dst"
  • _mm_min_pu8 Compare packed unsigned 8-bit integers in "a" and "b", and store packed minimum values in "dst"
  • _mm_min_ss Compare the lower single-precision floating-point elements in "a" and "b", store the minimum value in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst"
  • _mm_move_ss Move the lower single-precision floating-point element from "b" to the lower element of "dst", and copy the upper 3 elements from "a" to the upper elements of "dst"
  • _mm_movehl_ps Move the upper 2 single-precision floating-point elements from "b" to the lower 2 elements of "dst", and copy the upper 2 elements from "a" to the upper 2 elements of "dst"
  • _mm_movelh_ps Move the lower 2 single-precision floating-point elements from "b" to the upper 2 elements of "dst", and copy the lower 2 elements from "a" to the lower 2 elements of "dst"
  • _mm_movemask_pi8 Create mask from the most significant bit of each 8-bit element in "a"
  • _mm_movemask_ps Set each bit of mask "dst" based on the most significant bit of the corresponding packed single-precision floating-point element in "a"
  • _mm_mul_ps Multiply packed single-precision floating-point elements in "a" and "b"
  • _mm_mul_ss Multiply the lower single-precision floating-point element in "a" and "b"
  • _mm_mulhi_pu16 Multiply the packed unsigned 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst"

O

  • _mm_or_ps Compute the bitwise OR of packed single-precision floating-point elements in "a" and "b"

P

  • _m_pavgb Average packed unsigned 8-bit integers in "a" and "b", and store the results in "dst"
  • _m_pavgw Average packed unsigned 16-bit integers in "a" and "b", and store the results in "dst"
  • _m_pextrw Extract a 16-bit integer from "a", selected with "imm8", and store the result in the lower element of "dst"
  • _m_pinsrw Copy "a" to "dst", and insert the 16-bit integer "i" into "dst" at the location specified by "imm8"
  • _m_pmaxsw Compare packed 16-bit integers in "a" and "b", and store packed maximum values in "dst"
  • _m_pmaxub Compare packed unsigned 8-bit integers in "a" and "b", and store packed maximum values in "dst"
  • _m_pminsw Compare packed 16-bit integers in "a" and "b", and store packed minimum values in "dst"
  • _m_pminub Compare packed unsigned 8-bit integers in "a" and "b", and store packed minimum values in "dst"
  • _m_pmovmskb Create mask from the most significant bit of each 8-bit element in "a"
  • _m_pmulhuw Multiply the packed unsigned 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst"
  • _mm_prefetch SSE Fetch the line of data from memory that contains address "p" to a location in the cache heirarchy specified by the locality hint "i"
  • _m_psadbw Compute the absolute differences of packed unsigned 8-bit integers in "a" and "b", then horizontally sum each consecutive 8 differences to produce four unsigned 16-bit integers, and pack these unsigned 16-bit integers in the low 16 bits of "dst"
  • _m_pshufw Shuffle 16-bit integers in "a" using the control in "imm8", and store the results in "dst"

R

  • _mm_rcp_ps Compute the approximate reciprocal of packed single-precision floating-point elements in "a"
  • _mm_rcp_ss Compute the approximate reciprocal of the lower single-precision floating-point element in "a"
  • _mm_rsqrt_ps Compute the approximate reciprocal square root of packed single-precision floating-point elements in "a"
  • _mm_rsqrt_ss Compute the approximate reciprocal square root of the lower single-precision floating-point element in "a"

S

  • _mm_sad_pu8 Compute the absolute differences of packed unsigned 8-bit integers in "a" and "b", then horizontally sum each consecutive 8 differences to produce four unsigned 16-bit integers, and pack these unsigned 16-bit integers in the low 16 bits of "dst"
  • _MM_SET_EXCEPTION_MASK Macro: Set the exception mask bits of the MXCSR control and status register to the value in unsigned 32-bit integer "a"
  • _MM_SET_EXCEPTION_STATE Macro: Set the exception state bits of the MXCSR control and status register to the value in unsigned 32-bit integer "a"
  • _MM_SET_FLUSH_ZERO_MODE Macro: Set the flush zero bits of the MXCSR control and status register to the value in unsigned 32-bit integer "a"
  • _mm_set_ps Set packed single-precision floating-point elements in "dst" with the supplied values
  • _mm_set_ps1 Broadcast single-precision floating-point value "a" to all elements of "dst"
  • _MM_SET_ROUNDING_MODE Macro: Set the rounding mode bits of the MXCSR control and status register to the value in unsigned 32-bit integer "a"
  • _mm_set_ss Copy single-precision floating-point element "a" to the lower element of "dst", and zero the upper 3 elements
  • _mm_set1_ps Broadcast single-precision floating-point value "a" to all elements of "dst"
  • _mm_setcsr Set the MXCSR control and status register with the value in unsigned 32-bit integer "a"
  • _mm_setr_ps Set packed single-precision floating-point elements in "dst" with the supplied values in reverse order
  • _mm_setzero_ps Return vector of type __m128 with all elements set to zero.
  • _mm_sfence Perform a serializing operation on all store-to-memory instructions that were issued prior to this instruction
  • _mm_shuffle_pi16 Shuffle 16-bit integers in "a" using the control in "imm8", and store the results in "dst"
  • _mm_shuffle_ps Shuffle single-precision floating-point elements in "a" using the control in "imm8"
  • _mm_sqrt_ps Compute the square root of packed single-precision floating-point elements in "a"
  • _mm_sqrt_ss Compute the square root of the lower single-precision floating-point element in "a"
  • _mm_store_ps Store 128-bits (composed of 4 packed single-precision floating-point elements) from "a" into memory
  • _mm_store_ps1 Store the lower single-precision floating-point element from "a" into 4 contiguous elements in memory
  • _mm_store_ss Store the lower single-precision floating-point element from "a" into memory
  • _mm_store1_ps Store the lower single-precision floating-point element from "a" into 4 contiguous elements in memory
  • _mm_storeh_pi Store the upper 2 single-precision floating-point elements from "a" into memory
  • _mm_storel_pi Store the lower 2 single-precision floating-point elements from "a" into memory
  • _mm_storer_ps Store 4 single-precision floating-point elements from "a" into memory in reverse order
  • _mm_storeu_ps Store 128-bits (composed of 4 packed single-precision floating-point elements) from "a" into memory
  • _mm_storeu_si16 Store 16-bit integer from the first element of "a" into memory. "mem_addr" does not need to be aligned on any particular boundary.
  • _mm_storeu_si64 Store 64-bit integer from the first element of "a" into memory. "mem_addr" does not need to be aligned on any particular boundary.
  • _mm_stream_pi Store 64-bits of integer data from "a" into memory using a non-temporal memory hint
  • _mm_stream_ps Store 128-bits (composed of 4 packed single-precision floating-point elements) from "a" into memory using a non-temporal memory hint
  • _mm_sub_ps Subtract packed single-precision floating-point elements in "b" from packed single-precision floating-point elements in "a"
  • _mm_sub_ss Subtract the lower single-precision floating-point element in "b" from the lower single-precision floating-point element in "a"

T

  • _MM_TRANSPOSE4_PS Macro: Transpose the 4x4 matrix formed by the 4 rows of single-precision floating-point elements in "row0", "row1", "row2", and "row3", and store the transposed matrix in these vectors ("row0" now contains column 0, etc

U

  • _mm_ucomieq_ss Compare the lower single-precision floating-point element in "a" and "b" for equality
  • _mm_ucomige_ss Compare the lower single-precision floating-point element in "a" and "b" for greater-than-or-equal
  • _mm_ucomigt_ss Compare the lower single-precision floating-point element in "a" and "b" for greater-than
  • _mm_ucomile_ss Compare the lower single-precision floating-point element in "a" and "b" for less-than-or-equal
  • _mm_ucomilt_ss Compare the lower single-precision floating-point element in "a" and "b" for less-than
  • _mm_ucomineq_ss Compare the lower single-precision floating-point element in "a" and "b" for not-equal
  • _mm_undefined_ps Return vector of type __m128 with undefined elements.
  • _mm_unpackhi_ps Unpack and interleave single-precision floating-point elements from the high half "a" and "b"
  • _mm_unpacklo_ps Unpack and interleave single-precision floating-point elements from the low half of "a" and "b"

X

  • _mm_xor_ps Compute the bitwise XOR of packed single-precision floating-point elements in "a" and "b"


SSE2

A B C D E I L M O P S U X

A

  • _mm_add_epi8 Add packed 8-bit integers in "a" and "b", and store the results in "dst"
  • _mm_add_epi16 Add packed 16-bit integers in "a" and "b", and store the results in "dst"
  • _mm_add_epi32 Add packed 32-bit integers in "a" and "b", and store the results in "dst"
  • _mm_add_epi64 Add packed 64-bit integers in "a" and "b", and store the results in "dst"
  • _mm_add_pd Add packed double-precision floating-point elements in "a" and "b"
  • _mm_add_sd Add the lower double-precision floating-point element in "a" and "b"
  • _mm_add_si64 Add 64-bit integers "a" and "b", and store the result in "dst".
  • _mm_adds_epi8 Add packed 8-bit integers in "a" and "b" using saturation, and store the results in "dst"
  • _mm_adds_epi16 Add packed 16-bit integers in "a" and "b" using saturation, and store the results in "dst"
  • _mm_adds_epu8 Add packed unsigned 8-bit integers in "a" and "b" using saturation
  • _mm_adds_epu16 Add packed unsigned 16-bit integers in "a" and "b" using saturation
  • _mm_and_pd Compute the bitwise AND of packed double-precision floating-point elements in "a" and "b"
  • _mm_and_si128 Compute the bitwise AND of 128 bits (representing integer data) in "a" and "b"
  • _mm_andnot_pd Compute the bitwise NOT of packed double-precision floating-point elements in "a" and then AND with "b"
  • _mm_andnot_si128 Compute the bitwise NOT of 128 bits (representing integer data) in "a" and then AND with "b"
  • _mm_avg_epu8 Average packed unsigned 8-bit integers in "a" and "b", and store the results in "dst"
  • _mm_avg_epu16 Average packed unsigned 16-bit integers in "a" and "b", and store the results in "dst"

B

  • _mm_bslli_si128 Shift "a" left by "imm8" bytes while shifting in zeros, and store the results in "dst"
  • _mm_bsrli_si128 Shift "a" right by "imm8" bytes while shifting in zeros, and store the results in "dst"

C

  • _mm_castpd_ps Cast vector of type __m128d to type __m128. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.
  • _mm_castpd_si128 Cast vector of type __m128d to type __m128i. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.
  • _mm_castps_pd Cast vector of type __m128 to type __m128d. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.
  • _mm_castps_si128 Cast vector of type __m128 to type __m128i. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.
  • _mm_castsi128_pd Cast vector of type __m128i to type __m128d. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.
  • _mm_castsi128_ps Cast vector of type __m128i to type __m128. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.
  • _mm_clflush Invalidate and flush the cache line that contains "p" from all levels of the cache hierarchy
  • _mm_cmpeq_epi8 Compare packed 8-bit integers in "a" and "b" for equality, and store the results in "dst"
  • _mm_cmpeq_epi16 Compare packed 16-bit integers in "a" and "b" for equality, and store the results in "dst"
  • _mm_cmpeq_epi32 Compare packed 32-bit integers in "a" and "b" for equality, and store the results in "dst"
  • _mm_cmpeq_pd Compare packed double-precision floating-point elements in "a" and "b" for equality
  • _mm_cmpeq_sd Compare the lower double-precision floating-point elements in "a" and "b" for equality
  • _mm_cmpge_pd Compare packed double-precision floating-point elements in "a" and "b" for greater-than-or-equal
  • _mm_cmpge_sd Compare the lower double-precision floating-point elements in "a" and "b" for greater-than-or-equal
  • _mm_cmpgt_epi8 Compare packed 8-bit integers in "a" and "b" for greater-than, and store the results in "dst"
  • _mm_cmpgt_epi16 Compare packed 16-bit integers in "a" and "b" for greater-than, and store the results in "dst"
  • _mm_cmpgt_epi32 Compare packed 32-bit integers in "a" and "b" for greater-than, and store the results in "dst"
  • _mm_cmpgt_pd Compare packed double-precision floating-point elements in "a" and "b" for greater-than
  • _mm_cmpgt_sd Compare the lower double-precision floating-point elements in "a" and "b" for greater-than
  • _mm_cmple_pd Compare packed double-precision floating-point elements in "a" and "b" for less-than-or-equal
  • _mm_cmple_sd Compare the lower double-precision floating-point elements in "a" and "b" for less-than-or-equal
  • _mm_cmplt_epi8 Compare packed 8-bit integers in "a" and "b" for less-than, and store the results in "dst"
  • _mm_cmplt_epi16 Compare packed 16-bit integers in "a" and "b" for less-than, and store the results in "dst"
  • _mm_cmplt_epi32 Compare packed 32-bit integers in "a" and "b" for less-than, and store the results in "dst"
  • _mm_cmplt_pd Compare packed double-precision floating-point elements in "a" and "b" for less-than
  • _mm_cmplt_sd Compare the lower double-precision floating-point elements in "a" and "b" for less-than
  • _mm_cmpneq_pd Compare packed double-precision floating-point elements in "a" and "b" for not-equal
  • _mm_cmpneq_sd Compare the lower double-precision floating-point elements in "a" and "b" for not-equal
  • _mm_cmpnge_pd Compare packed double-precision floating-point elements in "a" and "b" for not-greater-than-or-equal
  • _mm_cmpnge_sd Compare the lower double-precision floating-point elements in "a" and "b" for not-greater-than-or-equal
  • _mm_cmpngt_pd Compare packed double-precision floating-point elements in "a" and "b" for not-greater-than
  • _mm_cmpngt_sd Compare the lower double-precision floating-point elements in "a" and "b" for not-greater-than
  • _mm_cmpnle_pd Compare packed double-precision floating-point elements in "a" and "b" for not-less-than-or-equal
  • _mm_cmpnle_sd Compare the lower double-precision floating-point elements in "a" and "b" for not-less-than-or-equal
  • _mm_cmpnlt_pd Compare packed double-precision floating-point elements in "a" and "b" for not-less-than
  • _mm_cmpnlt_sd Compare the lower double-precision floating-point elements in "a" and "b" for not-less-than
  • _mm_cmpord_pd Compare packed double-precision floating-point elements in "a" and "b" to see if neither is NaN
  • _mm_cmpord_sd Compare the lower double-precision floating-point elements in "a" and "b" to see if neither is NaN
  • _mm_cmpunord_pd Compare packed double-precision floating-point elements in "a" and "b" to see if either is NaN
  • _mm_cmpunord_sd Compare the lower double-precision floating-point elements in "a" and "b" to see if either is NaN
  • _mm_comieq_sd Compare the lower double-precision floating-point element in "a" and "b" for equality
  • _mm_comige_sd Compare the lower double-precision floating-point element in "a" and "b" for greater-than-or-equal
  • _mm_comigt_sd Compare the lower double-precision floating-point element in "a" and "b" for greater-than
  • _mm_comile_sd Compare the lower double-precision floating-point element in "a" and "b" for less-than-or-equal
  • _mm_comilt_sd Compare the lower double-precision floating-point element in "a" and "b" for less-than
  • _mm_comineq_sd Compare the lower double-precision floating-point element in "a" and "b" for not-equal
  • _mm_cvtepi32_pd Convert packed 32-bit integers in "a" to packed double-precision floating-point elements
  • _mm_cvtepi32_ps Convert packed 32-bit integers in "a" to packed single-precision floating-point elements
  • _mm_cvtpd_epi32 Convert packed double-precision floating-point elements in "a" to packed 32-bit integers
  • _mm_cvtpd_pi32 Convert packed double-precision floating-point elements in "a" to packed 32-bit integers
  • _mm_cvtpd_ps Convert packed double-precision floating-point elements in "a" to packed single-precision floating-point elements
  • _mm_cvtpi32_pd Convert packed 32-bit integers in "a" to packed double-precision floating-point elements
  • _mm_cvtps_epi32 Convert packed single-precision floating-point elements in "a" to packed 32-bit integers
  • _mm_cvtps_pd Convert packed single-precision floating-point elements in "a" to packed double-precision floating-point elements
  • _mm_cvtsd_f64 Copy the lower double-precision floating-point element of "a" to "dst"
  • _mm_cvtsd_si32 Convert the lower double-precision floating-point element in "a" to a 32-bit integer
  • _mm_cvtsd_si64 Convert the lower double-precision floating-point element in "a" to a 64-bit integer
  • _mm_cvtsd_si64x Convert the lower double-precision floating-point element in "a" to a 64-bit integer
  • _mm_cvtsd_ss Convert the lower double-precision floating-point element in "b" to a single-precision floating-point element
  • _mm_cvtsi128_si32 Copy the lower 32-bit integer in "a" to "dst".
  • _mm_cvtsi128_si64 Copy the lower 64-bit integer in "a" to "dst".
  • _mm_cvtsi128_si64x Copy the lower 64-bit integer in "a" to "dst".
  • _mm_cvtsi32_sd Convert the 32-bit integer "b" to a double-precision floating-point element
  • _mm_cvtsi32_si128 Copy 32-bit integer "a" to the lower elements of "dst", and zero the upper elements of "dst"
  • _mm_cvtsi64_sd Convert the 64-bit integer "b" to a double-precision floating-point element
  • _mm_cvtsi64_si128 Copy 64-bit integer "a" to the lower element of "dst", and zero the upper element
  • _mm_cvtsi64x_sd Convert the 64-bit integer "b" to a double-precision floating-point element
  • _mm_cvtsi64x_si128 Copy 64-bit integer "a" to the lower element of "dst", and zero the upper element
  • _mm_cvtss_sd Convert the lower single-precision floating-point element in "b" to a double-precision floating-point element
  • _mm_cvttpd_epi32 Convert packed double-precision floating-point elements in "a" to packed 32-bit integers with truncation
  • _mm_cvttpd_pi32 Convert packed double-precision floating-point elements in "a" to packed 32-bit integers with truncation
  • _mm_cvttps_epi32 Convert packed single-precision floating-point elements in "a" to packed 32-bit integers with truncation
  • _mm_cvttsd_si32 Convert the lower double-precision floating-point element in "a" to a 32-bit integer with truncation
  • _mm_cvttsd_si64 Convert the lower double-precision floating-point element in "a" to a 64-bit integer with truncation
  • _mm_cvttsd_si64x Convert the lower double-precision floating-point element in "a" to a 64-bit integer with truncation

D

  • _mm_div_pd Divide packed double-precision floating-point elements in "a" by packed elements in "b"
  • _mm_div_sd Divide the lower double-precision floating-point element in "a" by the lower double-precision floating-point element in "b"

E

  • _mm_extract_epi16 Extract a 16-bit integer from "a", selected with "imm8", and store the result in the lower element of "dst"

I

  • _mm_insert_epi16 Copy "a" to "dst", and insert the 16-bit integer "i" into "dst" at the location specified by "imm8"

L

  • _mm_lfence Perform a serializing operation on all load-from-memory instructions that were issued prior to this instruction
  • _mm_load_pd Load 128-bits (composed of 2 packed double-precision floating-point elements) from memory into "dst"
  • _mm_load_pd1 Load a double-precision floating-point element from memory into both elements of "dst"
  • _mm_load_sd Load a double-precision floating-point element from memory into the lower of "dst", and zero the upper element
  • _mm_load_si128 Load 128-bits of integer data from memory into "dst". "mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.
  • _mm_load1_pd Load a double-precision floating-point element from memory into both elements of "dst"
  • _mm_loadh_pd Load a double-precision floating-point element from memory into the upper element of "dst", and copy the lower element from "a" to "dst"
  • _mm_loadl_epi64 Load 64-bit integer from memory into the first element of "dst".
  • _mm_loadl_pd Load a double-precision floating-point element from memory into the lower element of "dst", and copy the upper element from "a" to "dst"
  • _mm_loadr_pd Load 2 double-precision floating-point elements from memory into "dst" in reverse order
  • _mm_loadu_pd Load 128-bits (composed of 2 packed double-precision floating-point elements) from memory into "dst"
  • _mm_loadu_si32 Load unaligned 32-bit integer from memory into the first element of "dst"
  • _mm_loadu_si128 Load 128-bits of integer data from memory into "dst". "mem_addr" does not need to be aligned on any particular boundary.

M

  • _mm_madd_epi16 Multiply packed signed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers
  • _mm_maskmoveu_si128 Conditionally store 8-bit integer elements from "a" into memory using "mask" (elements are not stored when the highest bit is not set in the corresponding element) and a non-temporal memory hint
  • _mm_max_epi16 Compare packed 16-bit integers in "a" and "b", and store packed maximum values in "dst"
  • _mm_max_epu8 Compare packed unsigned 8-bit integers in "a" and "b", and store packed maximum values in "dst"
  • _mm_max_pd Compare packed double-precision floating-point elements in "a" and "b", and store packed maximum values in "dst"
  • _mm_max_sd Compare the lower double-precision floating-point elements in "a" and "b", store the maximum value in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst"
  • _mm_mfence Perform a serializing operation on all load-from-memory and store-to-memory instructions that were issued prior to this instruction
  • _mm_min_epi16 Compare packed 16-bit integers in "a" and "b", and store packed minimum values in "dst"
  • _mm_min_epu8 Compare packed unsigned 8-bit integers in "a" and "b", and store packed minimum values in "dst"
  • _mm_min_pd Compare packed double-precision floating-point elements in "a" and "b", and store packed minimum values in "dst"
  • _mm_min_sd Compare the lower double-precision floating-point elements in "a" and "b", store the minimum value in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst"
  • _mm_move_epi64 Copy the lower 64-bit integer in "a" to the lower element of "dst", and zero the upper element
  • _mm_move_sd Move the lower double-precision floating-point element from "b" to the lower element of "dst", and copy the upper element from "a" to the upper element of "dst"
  • _mm_movemask_epi8 Create mask from the most significant bit of each 8-bit element in "a"
  • _mm_movemask_pd Set each bit of mask "dst" based on the most significant bit of the corresponding packed double-precision floating-point element in "a"
  • _mm_movepi64_pi64 Copy the lower 64-bit integer in "a" to "dst".
  • _mm_movpi64_epi64 Copy the 64-bit integer "a" to the lower element of "dst", and zero the upper element
  • _mm_mul_epu32 Multiply the low unsigned 32-bit integers from each packed 64-bit element in "a" and "b", and store the unsigned 64-bit results in "dst"
  • _mm_mul_pd Multiply packed double-precision floating-point elements in "a" and "b"
  • _mm_mul_sd Multiply the lower double-precision floating-point element in "a" and "b"
  • _mm_mul_su32 Multiply the low unsigned 32-bit integers from "a" and "b", and store the unsigned 64-bit result in "dst"
  • _mm_mulhi_epi16 Multiply the packed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst"
  • _mm_mulhi_epu16 Multiply the packed unsigned 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst"
  • _mm_mullo_epi16 Multiply the packed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the low 16 bits of the intermediate integers in "dst"

O

  • _mm_or_pd Compute the bitwise OR of packed double-precision floating-point elements in "a" and "b"
  • _mm_or_si128 Compute the bitwise OR of 128 bits (representing integer data) in "a" and "b"

P

  • _mm_packs_epi16 Convert packed 16-bit integers from "a" and "b" to packed 8-bit integers using signed saturation
  • _mm_packs_epi32 Convert packed 32-bit integers from "a" and "b" to packed 16-bit integers using signed saturation
  • _mm_packus_epi16 Convert packed 16-bit integers from "a" and "b" to packed 8-bit integers using unsigned saturation
  • _mm_pause Provide a hint to the processor that the code sequence is a spin-wait loop

S

  • _mm_sad_epu8 Compute the absolute differences of packed unsigned 8-bit integers in "a" and "b", then horizontally sum each consecutive 8 differences to produce two unsigned 16-bit integers, and pack these unsigned 16-bit integers in the low 16 bits of 64-bit elements in "dst"
  • _mm_set_epi8 Set packed 8-bit integers in "dst" with the supplied values in reverse order
  • _mm_set_epi16 Set packed 16-bit integers in "dst" with the supplied values.
  • _mm_set_epi32 Set packed 32-bit integers in "dst" with the supplied values.
  • _mm_set_epi64 Set packed 64-bit integers in "dst" with the supplied values.
  • _mm_set_epi64x Set packed 64-bit integers in "dst" with the supplied values.
  • _mm_set_pd Set packed double-precision floating-point elements in "dst" with the supplied values
  • _mm_set_pd1 Broadcast double-precision floating-point value "a" to all elements of "dst"
  • _mm_set_sd Copy double-precision floating-point element "a" to the lower element of "dst", and zero the upper element
  • _mm_set1_epi8 Broadcast 8-bit integer "a" to all elements of "dst". This intrinsic may generate "vpbroadcastb".
  • _mm_set1_epi16 Broadcast 16-bit integer "a" to all all elements of "dst". This intrinsic may generate "vpbroadcastw".
  • _mm_set1_epi32 Broadcast 32-bit integer "a" to all elements of "dst". This intrinsic may generate "vpbroadcastd".
  • _mm_set1_epi64 Broadcast 64-bit integer "a" to all elements of "dst".
  • _mm_set1_epi64x Broadcast 64-bit integer "a" to all elements of "dst". This intrinsic may generate the "vpbroadcastq".
  • _mm_set1_pd Broadcast double-precision floating-point value "a" to all elements of "dst"
  • _mm_setr_epi8 Set packed 8-bit integers in "dst" with the supplied values in reverse order
  • _mm_setr_epi16 Set packed 16-bit integers in "dst" with the supplied values in reverse order
  • _mm_setr_epi32 Set packed 32-bit integers in "dst" with the supplied values in reverse order
  • _mm_setr_epi64 Set packed 64-bit integers in "dst" with the supplied values in reverse order
  • _mm_setr_pd Set packed double-precision floating-point elements in "dst" with the supplied values in reverse order
  • _mm_setzero_pd Return vector of type __m128d with all elements set to zero.
  • _mm_setzero_si128 Return vector of type __m128i with all elements set to zero.
  • _mm_shuffle_epi32 Shuffle 32-bit integers in "a" using the control in "imm8", and store the results in "dst"
  • _mm_shuffle_pd Shuffle double-precision floating-point elements using the control in "imm8"
  • _mm_shufflehi_epi16 Shuffle 16-bit integers in the high 64 bits of "a" using the control in "imm8"
  • _mm_shufflelo_epi16 Shuffle 16-bit integers in the low 64 bits of "a" using the control in "imm8"
  • _mm_sll_epi16 Shift packed 16-bit integers in "a" left by "count" while shifting in zeros
  • _mm_sll_epi32 Shift packed 32-bit integers in "a" left by "count" while shifting in zeros
  • _mm_sll_epi64 Shift packed 64-bit integers in "a" left by "count" while shifting in zeros
  • _mm_slli_epi16 Shift packed 16-bit integers in "a" left by "imm8" while shifting in zeros
  • _mm_slli_epi32 Shift packed 32-bit integers in "a" left by "imm8" while shifting in zeros
  • _mm_slli_epi64 Shift packed 64-bit integers in "a" left by "imm8" while shifting in zeros
  • _mm_slli_si128 Shift "a" left by "imm8" bytes while shifting in zeros, and store the results in "dst"
  • _mm_sqrt_pd Compute the square root of packed double-precision floating-point elements in "a"
  • _mm_sqrt_sd Compute the square root of the lower double-precision floating-point element in "b"
  • _mm_sra_epi16 Shift packed 16-bit integers in "a" right by "count" while shifting in sign bits
  • _mm_sra_epi32 Shift packed 32-bit integers in "a" right by "count" while shifting in sign bits
  • _mm_srai_epi16 Shift packed 16-bit integers in "a" right by "imm8" while shifting in sign bits
  • _mm_srai_epi32 Shift packed 32-bit integers in "a" right by "imm8" while shifting in sign bits
  • _mm_srl_epi16 Shift packed 16-bit integers in "a" right by "count" while shifting in zeros
  • _mm_srl_epi32 Shift packed 32-bit integers in "a" right by "count" while shifting in zeros
  • _mm_srl_epi64 Shift packed 64-bit integers in "a" right by "count" while shifting in zeros
  • _mm_srli_epi16 Shift packed 16-bit integers in "a" right by "imm8" while shifting in zeros
  • _mm_srli_epi32 Shift packed 32-bit integers in "a" right by "imm8" while shifting in zeros
  • _mm_srli_epi64 Shift packed 64-bit integers in "a" right by "imm8" while shifting in zeros
  • _mm_srli_si128 Shift "a" right by "imm8" bytes while shifting in zeros, and store the results in "dst"
  • _mm_store_pd Store 128-bits (composed of 2 packed double-precision floating-point elements) from "a" into memory
  • _mm_store_pd1 Store the lower double-precision floating-point element from "a" into 2 contiguous elements in memory
  • _mm_store_sd Store the lower double-precision floating-point element from "a" into memory
  • _mm_store_si128 Store 128-bits of integer data from "a" into memory. "mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.
  • _mm_store1_pd Store the lower double-precision floating-point element from "a" into 2 contiguous elements in memory
  • _mm_storeh_pd Store the upper double-precision floating-point element from "a" into memory
  • _mm_storel_epi64 Store 64-bit integer from the first element of "a" into memory.
  • _mm_storel_pd Store the lower double-precision floating-point element from "a" into memory
  • _mm_storer_pd Store 2 double-precision floating-point elements from "a" into memory in reverse order
  • _mm_storeu_pd Store 128-bits (composed of 2 packed double-precision floating-point elements) from "a" into memory
  • _mm_storeu_si32 Store 32-bit integer from the first element of "a" into memory. "mem_addr" does not need to be aligned on any particular boundary.
  • _mm_storeu_si128 Store 128-bits of integer data from "a" into memory. "mem_addr" does not need to be aligned on any particular boundary.
  • _mm_stream_pd Store 128-bits (composed of 2 packed double-precision floating-point elements) from "a" into memory using a non-temporal memory hint
  • _mm_stream_si32 Store 32-bit integer "a" into memory using a non-temporal hint to minimize cache pollution
  • _mm_stream_si64 Store 64-bit integer "a" into memory using a non-temporal hint to minimize cache pollution
  • _mm_stream_si128 Store 128-bits of integer data from "a" into memory using a non-temporal memory hint
  • _mm_sub_epi8 Subtract packed 8-bit integers in "b" from packed 8-bit integers in "a"
  • _mm_sub_epi16 Subtract packed 16-bit integers in "b" from packed 16-bit integers in "a"
  • _mm_sub_epi32 Subtract packed 32-bit integers in "b" from packed 32-bit integers in "a"
  • _mm_sub_epi64 Subtract packed 64-bit integers in "b" from packed 64-bit integers in "a"
  • _mm_sub_pd Subtract packed double-precision floating-point elements in "b" from packed double-precision floating-point elements in "a"
  • _mm_sub_sd Subtract the lower double-precision floating-point element in "b" from the lower double-precision floating-point element in "a"
  • _mm_sub_si64 Subtract 64-bit integer "b" from 64-bit integer "a", and store the result in "dst"
  • _mm_subs_epi8 Subtract packed 8-bit integers in "b" from packed 8-bit integers in "a" using saturation
  • _mm_subs_epi16 Subtract packed 16-bit integers in "b" from packed 16-bit integers in "a" using saturation
  • _mm_subs_epu8 Subtract packed unsigned 8-bit integers in "b" from packed unsigned 8-bit integers in "a" using saturation
  • _mm_subs_epu16 Subtract packed unsigned 16-bit integers in "b" from packed unsigned 16-bit integers in "a" using saturation

U

  • _mm_ucomieq_sd Compare the lower double-precision floating-point element in "a" and "b" for equality
  • _mm_ucomige_sd Compare the lower double-precision floating-point element in "a" and "b" for greater-than-or-equal
  • _mm_ucomigt_sd Compare the lower double-precision floating-point element in "a" and "b" for greater-than
  • _mm_ucomile_sd Compare the lower double-precision floating-point element in "a" and "b" for less-than-or-equal
  • _mm_ucomilt_sd Compare the lower double-precision floating-point element in "a" and "b" for less-than
  • _mm_ucomineq_sd Compare the lower double-precision floating-point element in "a" and "b" for not-equal
  • _mm_undefined_pd Return vector of type __m128d with undefined elements.
  • _mm_undefined_si128 Return vector of type __m128i with undefined elements.
  • _mm_unpackhi_epi8 Unpack and interleave 8-bit integers from the high half of "a" and "b"
  • _mm_unpackhi_epi16 Unpack and interleave 16-bit integers from the high half of "a" and "b"
  • _mm_unpackhi_epi32 Unpack and interleave 32-bit integers from the high half of "a" and "b"
  • _mm_unpackhi_epi64 Unpack and interleave 64-bit integers from the high half of "a" and "b"
  • _mm_unpackhi_pd Unpack and interleave double-precision floating-point elements from the high half of "a" and "b"
  • _mm_unpacklo_epi8 Unpack and interleave 8-bit integers from the low half of "a" and "b"
  • _mm_unpacklo_epi16 Unpack and interleave 16-bit integers from the low half of "a" and "b"
  • _mm_unpacklo_epi32 Unpack and interleave 32-bit integers from the low half of "a" and "b"
  • _mm_unpacklo_epi64 Unpack and interleave 64-bit integers from the low half of "a" and "b"
  • _mm_unpacklo_pd Unpack and interleave double-precision floating-point elements from the low half of "a" and "b"

X

  • _mm_xor_pd Compute the bitwise XOR of packed double-precision floating-point elements in "a" and "b"
  • _mm_xor_si128 Compute the bitwise XOR of 128 bits (representing integer data) in "a" and "b"


SSE3

A H L M

A

  • _mm_addsub_pd Alternatively add and subtract packed double-precision floating-point elements in "a" to/from packed elements in "b"
  • _mm_addsub_ps Alternatively add and subtract packed single-precision floating-point elements in "a" to/from packed elements in "b"

H

  • _mm_hadd_pd Horizontally add adjacent pairs of double-precision floating-point elements in "a" and "b", and pack the results in "dst"
  • _mm_hadd_ps Horizontally add adjacent pairs of single-precision floating-point elements in "a" and "b", and pack the results in "dst"
  • _mm_hsub_pd Horizontally subtract adjacent pairs of double-precision floating-point elements in "a" and "b", and pack the results in "dst"
  • _mm_hsub_ps Horizontally add adjacent pairs of single-precision floating-point elements in "a" and "b", and pack the results in "dst"

L

  • _mm_lddqu_si128 Load 128-bits of integer data from unaligned memory into "dst". This intrinsic may perform better than "_mm_loadu_si128" when the data crosses a cache line boundary.
  • _mm_loaddup_pd Load a double-precision floating-point element from memory into both elements of "dst"

M

  • _mm_movedup_pd Duplicate the low double-precision floating-point element from "a"
  • _mm_movehdup_ps Duplicate odd-indexed single-precision floating-point elements from "a"
  • _mm_moveldup_ps Duplicate even-indexed single-precision floating-point elements from "a"


SSE4.1

B C D E F I M P R S T

B

  • _mm_blend_epi16 Blend packed 16-bit integers from "a" and "b" using control mask "imm8"
  • _mm_blend_pd Blend packed double-precision floating-point elements from "a" and "b" using control mask "imm8"
  • _mm_blend_ps Blend packed single-precision floating-point elements from "a" and "b" using control mask "imm8"
  • _mm_blendv_epi8 Blend packed 8-bit integers from "a" and "b" using "mask", and store the results in "dst"
  • _mm_blendv_pd Blend packed double-precision floating-point elements from "a" and "b" using "mask"
  • _mm_blendv_ps Blend packed single-precision floating-point elements from "a" and "b" using "mask"

C

  • _mm_ceil_pd Round the packed double-precision floating-point elements in "a" up to an integer value
  • _mm_ceil_ps Round the packed single-precision floating-point elements in "a" up to an integer value
  • _mm_ceil_sd Round the lower double-precision floating-point element in "b" up to an integer value
  • _mm_ceil_ss Round the lower single-precision floating-point element in "b" up to an integer value
  • _mm_cmpeq_epi64 Compare packed 64-bit integers in "a" and "b" for equality, and store the results in "dst"
  • _mm_cvtepi16_epi32 Sign extend packed 16-bit integers in "a" to packed 32-bit integers
  • _mm_cvtepi16_epi64 Sign extend packed 16-bit integers in "a" to packed 64-bit integers
  • _mm_cvtepi32_epi64 Sign extend packed 32-bit integers in "a" to packed 64-bit integers
  • _mm_cvtepi8_epi16 Sign extend packed 8-bit integers in "a" to packed 16-bit integers
  • _mm_cvtepi8_epi32 Sign extend packed 8-bit integers in "a" to packed 32-bit integers
  • _mm_cvtepi8_epi64 Sign extend packed 8-bit integers in the low 8 bytes of "a" to packed 64-bit integers
  • _mm_cvtepu16_epi32 Zero extend packed unsigned 16-bit integers in "a" to packed 32-bit integers
  • _mm_cvtepu16_epi64 Zero extend packed unsigned 16-bit integers in "a" to packed 64-bit integers
  • _mm_cvtepu32_epi64 Zero extend packed unsigned 32-bit integers in "a" to packed 64-bit integers
  • _mm_cvtepu8_epi16 Zero extend packed unsigned 8-bit integers in "a" to packed 16-bit integers
  • _mm_cvtepu8_epi32 Zero extend packed unsigned 8-bit integers in "a" to packed 32-bit integers
  • _mm_cvtepu8_epi64 Zero extend packed unsigned 8-bit integers in the low 8 byte sof "a" to packed 64-bit integers

D

  • _mm_dp_pd Conditionally multiply the packed double-precision floating-point elements in "a" and "b" using the high 4 bits in "imm8", sum the four products, and conditionally store the sum in "dst" using the low 4 bits of "imm8"
  • _mm_dp_ps Conditionally multiply the packed single-precision floating-point elements in "a" and "b" using the high 4 bits in "imm8", sum the four products, and conditionally store the sum in "dst" using the low 4 bits of "imm8"

E

  • _mm_extract_epi8 Extract an 8-bit integer from "a", selected with "imm8", and store the result in the lower element of "dst"
  • _mm_extract_epi32 Extract a 32-bit integer from "a", selected with "imm8", and store the result in "dst"
  • _mm_extract_epi64 Extract a 64-bit integer from "a", selected with "imm8", and store the result in "dst"
  • _mm_extract_ps Extract a single-precision floating-point element from "a", selected with "imm8"

F

  • _mm_floor_pd Round the packed double-precision floating-point elements in "a" down to an integer value
  • _mm_floor_ps Round the packed single-precision floating-point elements in "a" down to an integer value
  • _mm_floor_sd Round the lower double-precision floating-point element in "b" down to an integer value
  • _mm_floor_ss Round the lower single-precision floating-point element in "b" down to an integer value

I

  • _mm_insert_epi8 Copy "a" to "dst", and insert the lower 8-bit integer from "i" into "dst" at the location specified by "imm8"
  • _mm_insert_epi32 Copy "a" to "dst", and insert the 32-bit integer "i" into "dst" at the location specified by "imm8"
  • _mm_insert_epi64 Copy "a" to "dst", and insert the 64-bit integer "i" into "dst" at the location specified by "imm8"
  • _mm_insert_ps Copy "a" to "tmp", then insert a single-precision floating-point element from "b" into "tmp" using the control in "imm8"

M

  • _mm_max_epi8 Compare packed 8-bit integers in "a" and "b", and store packed maximum values in "dst"
  • _mm_max_epi32 Compare packed 32-bit integers in "a" and "b", and store packed maximum values in "dst"
  • _mm_max_epu16 Compare packed unsigned 16-bit integers in "a" and "b", and store packed maximum values in "dst"
  • _mm_max_epu32 Compare packed unsigned 32-bit integers in "a" and "b", and store packed maximum values in "dst"
  • _mm_min_epi8 Compare packed 8-bit integers in "a" and "b", and store packed minimum values in "dst"
  • _mm_min_epi32 Compare packed 32-bit integers in "a" and "b", and store packed minimum values in "dst"
  • _mm_min_epu16 Compare packed unsigned 16-bit integers in "a" and "b", and store packed minimum values in "dst"
  • _mm_min_epu32 Compare packed unsigned 32-bit integers in "a" and "b", and store packed minimum values in "dst"
  • _mm_minpos_epu16 Horizontally compute the minimum amongst the packed unsigned 16-bit integers in "a", store the minimum and index in "dst", and zero the remaining bits in "dst"
  • _mm_mpsadbw_epu8 Compute the sum of absolute differences (SADs) of quadruplets of unsigned 8-bit integers in "a" compared to those in "b", and store the 16-bit results in "dst"
  • _mm_mul_epi32 Multiply the low 32-bit integers from each packed 64-bit element in "a" and "b", and store the signed 64-bit results in "dst"
  • _mm_mullo_epi32 Multiply the packed 32-bit integers in "a" and "b", producing intermediate 64-bit integers, and store the low 32 bits of the intermediate integers in "dst"

P

  • _mm_packus_epi32 Convert packed 32-bit integers from "a" and "b" to packed 16-bit integers using unsigned saturation

R

  • _mm_round_pd Round the packed double-precision floating-point elements in "a" using the "rounding" parameter
  • _mm_round_ps Round the packed single-precision floating-point elements in "a" using the "rounding" parameter
  • _mm_round_sd Round the lower double-precision floating-point element in "b" using the "rounding" parameter
  • _mm_round_ss Round the lower single-precision floating-point element in "b" using the "rounding" parameter

S

  • _mm_stream_load_si128 Load 128-bits of integer data from memory into "dst" using a non-temporal memory hint

T

  • _mm_test_all_ones Compute the bitwise NOT of "a" and then AND with a 128-bit vector containing all 1's
  • _mm_test_all_zeros Compute the bitwise AND of 128 bits (representing integer data) in "a" and "mask"
  • _mm_test_mix_ones_zeros Compute the bitwise AND of 128 bits (representing integer data) in "a" and "mask", and set "ZF" to 1 if the result is zero, otherwise set "ZF" to 0
  • _mm_testc_si128 Compute the bitwise AND of 128 bits (representing integer data) in "a" and "b", and set "ZF" to 1 if the result is zero, otherwise set "ZF" to 0
  • _mm_testnzc_si128 Compute the bitwise AND of 128 bits (representing integer data) in "a" and "b", and set "ZF" to 1 if the result is zero, otherwise set "ZF" to 0
  • _mm_testz_si128 Compute the bitwise AND of 128 bits (representing integer data) in "a" and "b", and set "ZF" to 1 if the result is zero, otherwise set "ZF" to 0


SSE4.2

M R

M

  • _mm_cmpestra Compare packed strings in "a" and "b" with lengths "la" and "lb" using the control in "imm8"
  • _mm_cmpestrc Compare packed strings in "a" and "b" with lengths "la" and "lb" using the control in "imm8"
  • _mm_cmpestri Compare packed strings in "a" and "b" with lengths "la" and "lb" using the control in "imm8", and store the generated index in "dst"
  • _mm_cmpestrm Compare packed strings in "a" and "b" with lengths "la" and "lb" using the control in "imm8", and store the generated mask in "dst"
  • _mm_cmpestro Compare packed strings in "a" and "b" with lengths "la" and "lb" using the control in "imm8"
  • _mm_cmpestrs Compare packed strings in "a" and "b" with lengths "la" and "lb" using the control in "imm8"
  • _mm_cmpestrz Compare packed strings in "a" and "b" with lengths "la" and "lb" using the control in "imm8"
  • _mm_cmpgt_epi64 Compare packed 64-bit integers in "a" and "b" for greater-than, and store the results in "dst"
  • _mm_cmpistra Compare packed strings with implicit lengths in "a" and "b" using the control in "imm8"
  • _mm_cmpistrc Compare packed strings with implicit lengths in "a" and "b" using the control in "imm8"
  • _mm_cmpistri Compare packed strings with implicit lengths in "a" and "b" using the control in "imm8", and store the generated index in "dst"
  • _mm_cmpistrm Compare packed strings with implicit lengths in "a" and "b" using the control in "imm8", and store the generated mask in "dst"
  • _mm_cmpistro Compare packed strings with implicit lengths in "a" and "b" using the control in "imm8"
  • _mm_cmpistrs Compare packed strings with implicit lengths in "a" and "b" using the control in "imm8"
  • _mm_cmpistrz Compare packed strings with implicit lengths in "a" and "b" using the control in "imm8"

R

  • _mm_crc32_u8 Starting with the initial value in "crc", accumulates a CRC32 value for unsigned 8-bit integer "v", and stores the result in "dst"
  • _mm_crc32_u16 Starting with the initial value in "crc", accumulates a CRC32 value for unsigned 16-bit integer "v", and stores the result in "dst"
  • _mm_crc32_u32 Starting with the initial value in "crc", accumulates a CRC32 value for unsigned 32-bit integer "v", and stores the result in "dst"
  • _mm_crc32_u64 Starting with the initial value in "crc", accumulates a CRC32 value for unsigned 64-bit integer "v", and stores the result in "dst"


SSSE3

A H M S

A

  • _mm_abs_epi8 Compute the absolute value of packed 8-bit integers in "a", and store the unsigned results in "dst"
  • _mm_abs_epi16 Compute the absolute value of packed 16-bit integers in "a", and store the unsigned results in "dst"
  • _mm_abs_epi32 Compute the absolute value of packed 32-bit integers in "a", and store the unsigned results in "dst"
  • _mm_abs_pi8 Compute the absolute value of packed 8-bit integers in "a", and store the unsigned results in "dst"
  • _mm_abs_pi16 Compute the absolute value of packed 16-bit integers in "a", and store the unsigned results in "dst"
  • _mm_abs_pi32 Compute the absolute value of packed 32-bit integers in "a", and store the unsigned results in "dst"
  • _mm_alignr_epi8 Concatenate 16-byte blocks in "a" and "b" into a 32-byte temporary result, shift the result right by "count" bytes, and store the low 16 bytes in "dst"
  • _mm_alignr_pi8 Concatenate 8-byte blocks in "a" and "b" into a 16-byte temporary result, shift the result right by "count" bytes, and store the low 16 bytes in "dst"

H

  • _mm_hadd_epi16 Horizontally add adjacent pairs of 16-bit integers in "a" and "b", and pack the signed 16-bit results in "dst"
  • _mm_hadd_epi32 Horizontally add adjacent pairs of 32-bit integers in "a" and "b", and pack the signed 32-bit results in "dst"
  • _mm_hadd_pi16 Horizontally add adjacent pairs of 16-bit integers in "a" and "b", and pack the signed 16-bit results in "dst"
  • _mm_hadd_pi32 Horizontally add adjacent pairs of 32-bit integers in "a" and "b", and pack the signed 32-bit results in "dst"
  • _mm_hadds_epi16 Horizontally add adjacent pairs of 16-bit integers in "a" and "b" using saturation, and pack the signed 16-bit results in "dst"
  • _mm_hadds_pi16 Horizontally add adjacent pairs of 16-bit integers in "a" and "b" using saturation, and pack the signed 16-bit results in "dst"
  • _mm_hsub_epi16 Horizontally subtract adjacent pairs of 16-bit integers in "a" and "b", and pack the signed 16-bit results in "dst"
  • _mm_hsub_epi32 Horizontally subtract adjacent pairs of 32-bit integers in "a" and "b", and pack the signed 32-bit results in "dst"
  • _mm_hsub_pi16 Horizontally subtract adjacent pairs of 16-bit integers in "a" and "b", and pack the signed 16-bit results in "dst"
  • _mm_hsub_pi32 Horizontally subtract adjacent pairs of 32-bit integers in "a" and "b", and pack the signed 32-bit results in "dst"
  • _mm_hsubs_epi16 Horizontally subtract adjacent pairs of 16-bit integers in "a" and "b" using saturation, and pack the signed 16-bit results in "dst"
  • _mm_hsubs_pi16 Horizontally subtract adjacent pairs of 16-bit integers in "a" and "b" using saturation, and pack the signed 16-bit results in "dst"

M

  • _mm_maddubs_epi16 Vertically multiply each unsigned 8-bit integer from "a" with the corresponding signed 8-bit integer from "b", producing intermediate signed 16-bit integers
  • _mm_maddubs_pi16 Vertically multiply each unsigned 8-bit integer from "a" with the corresponding signed 8-bit integer from "b", producing intermediate signed 16-bit integers
  • _mm_mulhrs_epi16 Multiply packed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers
  • _mm_mulhrs_pi16 Multiply packed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers

S

  • _mm_shuffle_epi8 Shuffle packed 8-bit integers in "a" according to shuffle control mask in the corresponding 8-bit element of "b"
  • _mm_shuffle_pi8 Shuffle packed 8-bit integers in "a" according to shuffle control mask in the corresponding 8-bit element of "b"
  • _mm_sign_epi8 Negate packed 8-bit integers in "a" when the corresponding signed 8-bit integer in "b" is negative
  • _mm_sign_epi16 Negate packed 16-bit integers in "a" when the corresponding signed 16-bit integer in "b" is negative
  • _mm_sign_epi32 Negate packed 32-bit integers in "a" when the corresponding signed 32-bit integer in "b" is negative
  • _mm_sign_pi8 Negate packed 8-bit integers in "a" when the corresponding signed 8-bit integer in "b" is negative
  • _mm_sign_pi16 Negate packed 16-bit integers in "a" when the corresponding signed 16-bit integer in "b" is negative
  • _mm_sign_pi32 Negate packed 32-bit integers in "a" when the corresponding signed 32-bit integer in "b" is negative


SVML

A C D E H I L P R S T U

A

  • _mm_acos_pd Compute the inverse cosine of packed double-precision floating-point elements in "a" expressed in radians
  • _mm256_acos_pd Compute the inverse cosine of packed double-precision floating-point elements in "a"
  • _mm_acos_ps Compute the inverse cosine of packed single-precision floating-point elements in "a" expressed in radians
  • _mm256_acos_ps Compute the inverse cosine of packed single-precision floating-point elements in "a" expressed in radians
  • _mm_acosh_pd Compute the inverse hyperbolic cosine of packed double-precision floating-point elements in "a" expressed in radians
  • _mm256_acosh_pd Compute the inverse hyperbolic cosine of packed double-precision floating-point elements in "a" expressed in radians
  • _mm_acosh_ps Compute the inverse hyperbolic cosine of packed single-precision floating-point elements in "a" expressed in radians
  • _mm256_acosh_ps Compute the inverse hyperbolic cosine of packed single-precision floating-point elements in "a" expressed in radians
  • _mm_asin_pd Compute the inverse sine of packed double-precision floating-point elements in "a" expressed in radians
  • _mm256_asin_pd Compute the inverse sine of packed double-precision floating-point elements in "a" expressed in radians
  • _mm_asin_ps Compute the inverse sine of packed single-precision floating-point elements in "a" expressed in radians
  • _mm256_asin_ps Compute the inverse sine of packed single-precision floating-point elements in "a" expressed in radians
  • _mm_asinh_pd Compute the inverse hyperbolic sine of packed double-precision floating-point elements in "a" expressed in radians
  • _mm256_asinh_pd Compute the inverse hyperbolic sine of packed double-precision floating-point elements in "a" expressed in radians
  • _mm_asinh_ps Compute the inverse hyperbolic sine of packed single-precision floating-point elements in "a" expressed in radians
  • _mm256_asinh_ps Compute the inverse hyperbolic sine of packed single-precision floating-point elements in "a" expressed in radians
  • _mm_atan_pd Compute the inverse tangent of packed double-precision floating-point elements in "a" expressed in radians
  • _mm256_atan_pd Compute the inverse tangent of packed double-precision floating-point elements in "a" expressed in radians
  • _mm_atan_ps Compute the inverse tangent of packed single-precision floating-point elements in "a" expressed in radians
  • _mm256_atan_ps Compute the inverse tangent of packed single-precision floating-point elements in "a" expressed in radians
  • _mm_atan2_pd Compute the inverse tangent of packed double-precision floating-point elements in "a" divided by packed elements in "b"
  • _mm256_atan2_pd Compute the inverse tangent of packed double-precision floating-point elements in "a" divided by packed elements in "b"
  • _mm_atan2_ps Compute the inverse tangent of packed single-precision floating-point elements in "a" divided by packed elements in "b"
  • _mm256_atan2_ps Compute the inverse tangent of packed single-precision floating-point elements in "a" divided by packed elements in "b"
  • _mm_atanh_pd Compute the inverse hyperbolic tangent of packed double-precision floating-point elements in "a" expressed in radians
  • _mm256_atanh_pd Compute the inverse hyperbolic tangent of packed double-precision floating-point elements in "a" expressed in radians
  • _mm_atanh_ps Compute the inverse hyperbolic tangent of packed single-precision floating-point elements in "a" expressed in radians
  • _mm256_atanh_ps Compute the inverse hyperbolic tangent of packed single-precision floating-point elements in "a" expressed in radians

C

  • _mm_cbrt_pd Compute the cube root of packed double-precision floating-point elements in "a"
  • _mm256_cbrt_pd Compute the cube root of packed double-precision floating-point elements in "a"
  • _mm_cbrt_ps Compute the cube root of packed single-precision floating-point elements in "a"
  • _mm256_cbrt_ps Compute the cube root of packed single-precision floating-point elements in "a"
  • _mm_cdfnorm_pd Compute the cumulative distribution function of packed double-precision floating-point elements in "a" using the normal distribution
  • _mm256_cdfnorm_pd Compute the cumulative distribution function of packed double-precision floating-point elements in "a" using the normal distribution
  • _mm_cdfnorm_ps Compute the cumulative distribution function of packed single-precision floating-point elements in "a" using the normal distribution
  • _mm256_cdfnorm_ps Compute the cumulative distribution function of packed single-precision floating-point elements in "a" using the normal distribution
  • _mm_cdfnorminv_pd Compute the inverse cumulative distribution function of packed double-precision floating-point elements in "a" using the normal distribution
  • _mm256_cdfnorminv_pd Compute the inverse cumulative distribution function of packed double-precision floating-point elements in "a" using the normal distribution
  • _mm_cdfnorminv_ps Compute the inverse cumulative distribution function of packed single-precision floating-point elements in "a" using the normal distribution
  • _mm256_cdfnorminv_ps Compute the inverse cumulative distribution function of packed single-precision floating-point elements in "a" using the normal distribution
  • _mm_cexp_ps Compute the exponential value of "e" raised to the power of packed complex single-precision floating-point elements in "a"
  • _mm256_cexp_ps Compute the exponential value of "e" raised to the power of packed complex single-precision floating-point elements in "a"
  • _mm_clog_ps Compute the natural logarithm of packed complex single-precision floating-point elements in "a"
  • _mm256_clog_ps Compute the natural logarithm of packed complex single-precision floating-point elements in "a"
  • _mm_cos_pd Compute the cosine of packed double-precision floating-point elements in "a" expressed in radians
  • _mm256_cos_pd Compute the cosine of packed double-precision floating-point elements in "a" expressed in radians
  • _mm_cos_ps Compute the cosine of packed single-precision floating-point elements in "a" expressed in radians
  • _mm256_cos_ps Compute the cosine of packed single-precision floating-point elements in "a" expressed in radians
  • _mm_cosd_pd Compute the cosine of packed double-precision floating-point elements in "a" expressed in degrees
  • _mm256_cosd_pd Compute the cosine of packed double-precision floating-point elements in "a" expressed in degrees
  • _mm_cosd_ps Compute the cosine of packed single-precision floating-point elements in "a" expressed in degrees
  • _mm256_cosd_ps Compute the cosine of packed single-precision floating-point elements in "a" expressed in degrees
  • _mm_cosh_pd Compute the hyperbolic cosine of packed double-precision floating-point elements in "a" expressed in radians
  • _mm256_cosh_pd Compute the hyperbolic cosine of packed double-precision floating-point elements in "a" expressed in radians
  • _mm_cosh_ps Compute the hyperbolic cosine of packed single-precision floating-point elements in "a" expressed in radians
  • _mm256_cosh_ps Compute the hyperbolic cosine of packed single-precision floating-point elements in "a" expressed in radians
  • _mm_csqrt_ps Compute the square root of packed complex single-precision floating-point elements in "a"
  • _mm256_csqrt_ps Compute the square root of packed complex single-precision floating-point elements in "a"

D

  • _mm_div_epi8 Divide packed 8-bit integers in "a" by packed elements in "b", and store the truncated results in "dst"
  • _mm256_div_epi8 Divide packed 8-bit integers in "a" by packed elements in "b", and store the truncated results in "dst"
  • _mm_div_epi16 Divide packed 16-bit integers in "a" by packed elements in "b", and store the truncated results in "dst"
  • _mm256_div_epi16 Divide packed 16-bit integers in "a" by packed elements in "b", and store the truncated results in "dst"
  • _mm_div_epi32 Divide packed 32-bit integers in "a" by packed elements in "b", and store the truncated results in "dst"
  • _mm256_div_epi32 Divide packed 32-bit integers in "a" by packed elements in "b", and store the truncated results in "dst"
  • _mm_div_epi64 Divide packed 64-bit integers in "a" by packed elements in "b", and store the truncated results in "dst"
  • _mm256_div_epi64 Divide packed 64-bit integers in "a" by packed elements in "b", and store the truncated results in "dst"
  • _mm_div_epu8 Divide packed unsigned 8-bit integers in "a" by packed elements in "b", and store the truncated results in "dst"
  • _mm256_div_epu8 Divide packed unsigned 8-bit integers in "a" by packed elements in "b", and store the truncated results in "dst"
  • _mm_div_epu16 Divide packed unsigned 16-bit integers in "a" by packed elements in "b", and store the truncated results in "dst"
  • _mm256_div_epu16 Divide packed unsigned 16-bit integers in "a" by packed elements in "b", and store the truncated results in "dst"
  • _mm_div_epu32 Divide packed unsigned 32-bit integers in "a" by packed elements in "b", and store the truncated results in "dst"
  • _mm256_div_epu32 Divide packed unsigned 32-bit integers in "a" by packed elements in "b", and store the truncated results in "dst"
  • _mm_div_epu64 Divide packed unsigned 64-bit integers in "a" by packed elements in "b", and store the truncated results in "dst"
  • _mm256_div_epu64 Divide packed unsigned 64-bit integers in "a" by packed elements in "b", and store the truncated results in "dst"

E

  • _mm_erf_pd Compute the error function of packed double-precision floating-point elements in "a"
  • _mm256_erf_pd Compute the error function of packed double-precision floating-point elements in "a"
  • _mm_erf_ps Compute the error function of packed single-precision floating-point elements in "a"
  • _mm256_erf_ps Compute the error function of packed single-precision floating-point elements in "a"
  • _mm_erfc_pd Compute the complementary error function of packed double-precision floating-point elements in "a"
  • _mm256_erfc_pd Compute the complementary error function of packed double-precision floating-point elements in "a"
  • _mm_erfc_ps Compute the complementary error function of packed single-precision floating-point elements in "a"
  • _mm256_erfc_ps Compute the complementary error function of packed single-precision floating-point elements in "a"
  • _mm_erfcinv_pd Compute the inverse complementary error function of packed double-precision floating-point elements in "a"
  • _mm256_erfcinv_pd Compute the inverse complementary error function of packed double-precision floating-point elements in "a"
  • _mm_erfcinv_ps Compute the inverse complementary error function of packed single-precision floating-point elements in "a"
  • _mm256_erfcinv_ps Compute the inverse complementary error function of packed single-precision floating-point elements in "a"
  • _mm_erfinv_pd Compute the inverse error function of packed double-precision floating-point elements in "a"
  • _mm256_erfinv_pd Compute the inverse error function of packed double-precision floating-point elements in "a"
  • _mm_erfinv_ps Compute the inverse error function of packed single-precision floating-point elements in "a"
  • _mm256_erfinv_ps Compute the inverse error function of packed single-precision floating-point elements in "a"
  • _mm_exp_pd Compute the exponential value of "e" raised to the power of packed double-precision floating-point elements in "a"
  • _mm256_exp_pd Compute the exponential value of "e" raised to the power of packed double-precision floating-point elements in "a"
  • _mm_exp_ps Compute the exponential value of "e" raised to the power of packed single-precision floating-point elements in "a"
  • _mm256_exp_ps Compute the exponential value of "e" raised to the power of packed single-precision floating-point elements in "a"
  • _mm_exp10_pd Compute the exponential value of 10 raised to the power of packed double-precision floating-point elements in "a"
  • _mm256_exp10_pd Compute the exponential value of 10 raised to the power of packed double-precision floating-point elements in "a"
  • _mm_exp10_ps Compute the exponential value of 10 raised to the power of packed single-precision floating-point elements in "a"
  • _mm256_exp10_ps Compute the exponential value of 10 raised to the power of packed single-precision floating-point elements in "a"
  • _mm_exp2_pd Compute the exponential value of 2 raised to the power of packed double-precision floating-point elements in "a"
  • _mm256_exp2_pd Compute the exponential value of 2 raised to the power of packed double-precision floating-point elements in "a"
  • _mm_exp2_ps Compute the exponential value of 2 raised to the power of packed single-precision floating-point elements in "a"
  • _mm256_exp2_ps Compute the exponential value of 2 raised to the power of packed single-precision floating-point elements in "a"
  • _mm_expm1_pd Compute the exponential value of "e" raised to the power of packed double-precision floating-point elements in "a", subtract one from each element
  • _mm256_expm1_pd Compute the exponential value of "e" raised to the power of packed double-precision floating-point elements in "a", subtract one from each element
  • _mm_expm1_ps Compute the exponential value of "e" raised to the power of packed single-precision floating-point elements in "a", subtract one from each element
  • _mm256_expm1_ps Compute the exponential value of "e" raised to the power of packed single-precision floating-point elements in "a", subtract one from each element

H

  • _mm_hypot_pd Compute the length of the hypotenous of a right triangle, with the lengths of the other two sides of the triangle stored as packed double-precision floating-point elements in "a" and "b"
  • _mm256_hypot_pd Compute the length of the hypotenous of a right triangle, with the lengths of the other two sides of the triangle stored as packed double-precision floating-point elements in "a" and "b"
  • _mm_hypot_ps Compute the length of the hypotenous of a right triangle, with the lengths of the other two sides of the triangle stored as packed single-precision floating-point elements in "a" and "b"
  • _mm256_hypot_ps Compute the length of the hypotenous of a right triangle, with the lengths of the other two sides of the triangle stored as packed single-precision floating-point elements in "a" and "b"

I

  • _mm_idiv_epi32 Divide packed 32-bit integers in "a" by packed elements in "b", and store the truncated results in "dst"
  • _mm256_idiv_epi32 Divide packed 32-bit integers in "a" by packed elements in "b", and store the truncated results in "dst"
  • _mm_idivrem_epi32 Divide packed 32-bit integers in "a" by packed elements in "b", store the truncated results in "dst", and store the remainders as packed 32-bit integers into memory at "mem_addr"
  • _mm256_idivrem_epi32 Divide packed 32-bit integers in "a" by packed elements in "b", store the truncated results in "dst", and store the remainders as packed 32-bit integers into memory at "mem_addr"
  • _mm_invcbrt_pd Compute the inverse cube root of packed double-precision floating-point elements in "a"
  • _mm256_invcbrt_pd Compute the inverse cube root of packed double-precision floating-point elements in "a"
  • _mm_invcbrt_ps Compute the inverse cube root of packed single-precision floating-point elements in "a"
  • _mm256_invcbrt_ps Compute the inverse cube root of packed single-precision floating-point elements in "a"
  • _mm_invsqrt_pd Compute the inverse square root of packed double-precision floating-point elements in "a"
  • _mm256_invsqrt_pd Compute the inverse square root of packed double-precision floating-point elements in "a"
  • _mm_invsqrt_ps Compute the inverse square root of packed single-precision floating-point elements in "a"
  • _mm256_invsqrt_ps Compute the inverse square root of packed single-precision floating-point elements in "a"
  • _mm_irem_epi32 Divide packed 32-bit integers in "a" by packed elements in "b", and store the remainders as packed 32-bit integers in "dst"
  • _mm256_irem_epi32 Divide packed 32-bit integers in "a" by packed elements in "b", and store the remainders as packed 32-bit integers in "dst"

L

  • _mm_log_pd Compute the natural logarithm of packed double-precision floating-point elements in "a"
  • _mm256_log_pd Compute the natural logarithm of packed double-precision floating-point elements in "a"
  • _mm_log_ps Compute the natural logarithm of packed single-precision floating-point elements in "a"
  • _mm256_log_ps Compute the natural logarithm of packed single-precision floating-point elements in "a"
  • _mm_log10_pd Compute the base-10 logarithm of packed double-precision floating-point elements in "a"
  • _mm256_log10_pd Compute the base-10 logarithm of packed double-precision floating-point elements in "a"
  • _mm_log10_ps Compute the base-10 logarithm of packed single-precision floating-point elements in "a"
  • _mm256_log10_ps Compute the base-10 logarithm of packed single-precision floating-point elements in "a"
  • _mm_log1p_pd Compute the natural logarithm of one plus packed double-precision floating-point elements in "a"
  • _mm256_log1p_pd Compute the natural logarithm of one plus packed double-precision floating-point elements in "a"
  • _mm_log1p_ps Compute the natural logarithm of one plus packed single-precision floating-point elements in "a"
  • _mm256_log1p_ps Compute the natural logarithm of one plus packed single-precision floating-point elements in "a"
  • _mm_log2_pd Compute the base-2 logarithm of packed double-precision floating-point elements in "a"
  • _mm256_log2_pd Compute the base-2 logarithm of packed double-precision floating-point elements in "a"
  • _mm_log2_ps Compute the base-2 logarithm of packed single-precision floating-point elements in "a"
  • _mm256_log2_ps Compute the base-2 logarithm of packed single-precision floating-point elements in "a"
  • _mm_logb_pd Convert the exponent of each packed double-precision floating-point element in "a" to a double-precision floating-point number representing the integer exponent
  • _mm256_logb_pd Convert the exponent of each packed double-precision floating-point element in "a" to a double-precision floating-point number representing the integer exponent
  • _mm_logb_ps Convert the exponent of each packed single-precision floating-point element in "a" to a single-precision floating-point number representing the integer exponent
  • _mm256_logb_ps Convert the exponent of each packed single-precision floating-point element in "a" to a single-precision floating-point number representing the integer exponent

P

  • _mm_pow_pd Compute the exponential value of packed double-precision floating-point elements in "a" raised by packed elements in "b"
  • _mm256_pow_pd Compute the exponential value of packed double-precision floating-point elements in "a" raised by packed elements in "b"
  • _mm_pow_ps Compute the exponential value of packed single-precision floating-point elements in "a" raised by packed elements in "b"
  • _mm256_pow_ps Compute the exponential value of packed single-precision floating-point elements in "a" raised by packed elements in "b"

R

  • _mm_rem_epi8 Divide packed 8-bit integers in "a" by packed elements in "b", and store the remainders as packed 32-bit integers in "dst"
  • _mm256_rem_epi8 Divide packed 8-bit integers in "a" by packed elements in "b", and store the remainders as packed 32-bit integers in "dst"
  • _mm_rem_epi16 Divide packed 16-bit integers in "a" by packed elements in "b", and store the remainders as packed 32-bit integers in "dst"
  • _mm256_rem_epi16 Divide packed 16-bit integers in "a" by packed elements in "b", and store the remainders as packed 32-bit integers in "dst"
  • _mm_rem_epi32 Divide packed 32-bit integers in "a" by packed elements in "b", and store the remainders as packed 32-bit integers in "dst"
  • _mm256_rem_epi32 Divide packed 32-bit integers in "a" by packed elements in "b", and store the remainders as packed 32-bit integers in "dst"
  • _mm_rem_epi64 Divide packed 64-bit integers in "a" by packed elements in "b", and store the remainders as packed 32-bit integers in "dst"
  • _mm256_rem_epi64 Divide packed 64-bit integers in "a" by packed elements in "b", and store the remainders as packed 32-bit integers in "dst"
  • _mm_rem_epu8 Divide packed unsigned 8-bit integers in "a" by packed elements in "b", and store the remainders as packed unsigned 32-bit integers in "dst"
  • _mm256_rem_epu8 Divide packed unsigned 8-bit integers in "a" by packed elements in "b", and store the remainders as packed unsigned 32-bit integers in "dst"
  • _mm_rem_epu16 Divide packed unsigned 16-bit integers in "a" by packed elements in "b", and store the remainders as packed unsigned 32-bit integers in "dst"
  • _mm256_rem_epu16 Divide packed unsigned 16-bit integers in "a" by packed elements in "b", and store the remainders as packed unsigned 32-bit integers in "dst"
  • _mm_rem_epu32 Divide packed unsigned 32-bit integers in "a" by packed elements in "b", and store the remainders as packed unsigned 32-bit integers in "dst"
  • _mm256_rem_epu32 Divide packed unsigned 32-bit integers in "a" by packed elements in "b", and store the remainders as packed unsigned 32-bit integers in "dst"
  • _mm_rem_epu64 Divide packed unsigned 64-bit integers in "a" by packed elements in "b", and store the remainders as packed unsigned 32-bit integers in "dst"
  • _mm256_rem_epu64 Divide packed unsigned 64-bit integers in "a" by packed elements in "b", and store the remainders as packed unsigned 32-bit integers in "dst"

S

  • _mm_sin_pd Compute the sine of packed double-precision floating-point elements in "a" expressed in radians
  • _mm256_sin_pd Compute the sine of packed double-precision floating-point elements in "a" expressed in radians
  • _mm_sin_ps Compute the sine of packed single-precision floating-point elements in "a" expressed in radians
  • _mm256_sin_ps Compute the sine of packed single-precision floating-point elements in "a" expressed in radians
  • _mm_sincos_pd Compute the sine and cosine of packed double-precision floating-point elements in "a" expressed in radians, store the sine in "dst", and store the cosine into memory at "mem_addr"
  • _mm256_sincos_pd Compute the sine and cosine of packed double-precision floating-point elements in "a" expressed in radians, store the sine in "dst", and store the cosine into memory at "mem_addr"
  • _mm_sincos_ps Compute the sine and cosine of packed single-precision floating-point elements in "a" expressed in radians, store the sine in "dst", and store the cosine into memory at "mem_addr"
  • _mm256_sincos_ps Compute the sine and cosine of packed single-precision floating-point elements in "a" expressed in radians, store the sine in "dst", and store the cosine into memory at "mem_addr"
  • _mm_sind_pd Compute the sine of packed double-precision floating-point elements in "a" expressed in degrees
  • _mm256_sind_pd Compute the sine of packed double-precision floating-point elements in "a" expressed in degrees
  • _mm_sind_ps Compute the sine of packed single-precision floating-point elements in "a" expressed in degrees
  • _mm256_sind_ps Compute the sine of packed single-precision floating-point elements in "a" expressed in degrees
  • _mm_sinh_pd Compute the hyperbolic sine of packed double-precision floating-point elements in "a" expressed in radians
  • _mm256_sinh_pd Compute the hyperbolic sine of packed double-precision floating-point elements in "a" expressed in radians
  • _mm_sinh_ps Compute the hyperbolic sine of packed single-precision floating-point elements in "a" expressed in radians
  • _mm256_sinh_ps Compute the hyperbolic sine of packed single-precision floating-point elements in "a" expressed in radians
  • _mm_svml_ceil_pd Round the packed double-precision floating-point elements in "a" up to an integer value
  • _mm256_svml_ceil_pd Round the packed double-precision floating-point elements in "a" up to an integer value
  • _mm_svml_ceil_ps Round the packed single-precision floating-point elements in "a" up to an integer value
  • _mm256_svml_ceil_ps Round the packed single-precision floating-point elements in "a" up to an integer value
  • _mm_svml_floor_pd Round the packed double-precision floating-point elements in "a" down to an integer value
  • _mm256_svml_floor_pd Round the packed double-precision floating-point elements in "a" down to an integer value
  • _mm_svml_floor_ps Round the packed single-precision floating-point elements in "a" down to an integer value
  • _mm256_svml_floor_ps Round the packed single-precision floating-point elements in "a" down to an integer value
  • _mm_svml_round_pd Round the packed double-precision floating-point elements in "a" to the nearest integer value
  • _mm256_svml_round_pd Round the packed double-precision floating-point elements in "a" to the nearest integer value
  • _mm_svml_round_ps Round the packed single-precision floating-point elements in "a" to the nearest integer value
  • _mm256_svml_round_ps Round the packed single-precision floating-point elements in "a" to the nearest integer value
  • _mm_svml_sqrt_pd Compute the square root of packed double-precision floating-point elements in "a"
  • _mm256_svml_sqrt_pd Compute the square root of packed double-precision floating-point elements in "a"
  • _mm_svml_sqrt_ps Compute the square root of packed single-precision floating-point elements in "a"
  • _mm256_svml_sqrt_ps Compute the square root of packed single-precision floating-point elements in "a"

T

  • _mm_tan_pd Compute the tangent of packed double-precision floating-point elements in "a" expressed in radians
  • _mm256_tan_pd Compute the tangent of packed double-precision floating-point elements in "a" expressed in radians
  • _mm_tan_ps Compute the tangent of packed single-precision floating-point elements in "a" expressed in radians
  • _mm256_tan_ps Compute the tangent of packed single-precision floating-point elements in "a" expressed in radians
  • _mm_tand_pd Compute the tangent of packed double-precision floating-point elements in "a" expressed in degrees
  • _mm256_tand_pd Compute the tangent of packed double-precision floating-point elements in "a" expressed in degrees
  • _mm_tand_ps Compute the tangent of packed single-precision floating-point elements in "a" expressed in degrees
  • _mm256_tand_ps Compute the tangent of packed single-precision floating-point elements in "a" expressed in degrees
  • _mm_tanh_pd Compute the hyperbolic tangent of packed double-precision floating-point elements in "a" expressed in radians
  • _mm256_tanh_pd Compute the hyperbolic tangent of packed double-precision floating-point elements in "a" expressed in radians
  • _mm_tanh_ps Compute the hyperbolic tangent of packed single-precision floating-point elements in "a" expressed in radians
  • _mm256_tanh_ps Compute the hyperbolic tangent of packed single-precision floating-point elements in "a" expressed in radians
  • _mm_trunc_pd Truncate the packed double-precision floating-point elements in "a"
  • _mm256_trunc_pd Truncate the packed double-precision floating-point elements in "a"
  • _mm_trunc_ps Truncate the packed single-precision floating-point elements in "a"
  • _mm256_trunc_ps Truncate the packed single-precision floating-point elements in "a"

U

  • _mm_udiv_epi32 Divide packed unsigned 32-bit integers in "a" by packed elements in "b", and store the truncated results in "dst"
  • _mm256_udiv_epi32 Divide packed unsigned 32-bit integers in "a" by packed elements in "b", and store the truncated results in "dst"
  • _mm_udivrem_epi32 Divide packed unsigned 32-bit integers in "a" by packed elements in "b", store the truncated results in "dst", and store the remainders as packed unsigned 32-bit integers into memory at "mem_addr"
  • _mm256_udivrem_epi32 Divide packed unsigned 32-bit integers in "a" by packed elements in "b", store the truncated results in "dst", and store the remainders as packed unsigned 32-bit integers into memory at "mem_addr"
  • _mm_urem_epi32 Divide packed unsigned 32-bit integers in "a" by packed elements in "b", and store the remainders as packed unsigned 32-bit integers in "dst"
  • _mm256_urem_epi32 Divide packed unsigned 32-bit integers in "a" by packed elements in "b", and store the remainders as packed unsigned 32-bit integers in "dst"


Other

A B C D E F G I L M P R S T U W X

A

  • _addcarry_u32 Add unsigned 32-bit integers "a" and "b" with unsigned 8-bit carry-in "c_in" (carry flag), and store the unsigned 32-bit result in "out", and the carry-out in "dst" (carry or overflow flag)
  • _addcarry_u64 Add unsigned 64-bit integers "a" and "b" with unsigned 8-bit carry-in "c_in" (carry flag), and store the unsigned 64-bit result in "out", and the carry-out in "dst" (carry or overflow flag)
  • _addcarryx_u32 Add unsigned 32-bit integers "a" and "b" with unsigned 8-bit carry-in "c_in" (carry or overflow flag), and store the unsigned 32-bit result in "out", and the carry-out in "dst" (carry or overflow flag)
  • _addcarryx_u64 Add unsigned 64-bit integers "a" and "b" with unsigned 8-bit carry-in "c_in" (carry or overflow flag), and store the unsigned 64-bit result in "out", and the carry-out in "dst" (carry or overflow flag)
  • _mm_aesdec_si128 Perform one round of an AES decryption flow on data (state) in "a" using the round key in "RoundKey"
  • _mm_aesdeclast_si128 Perform the last round of an AES decryption flow on data (state) in "a" using the round key in "RoundKey"
  • _mm_aesenc_si128 Perform one round of an AES encryption flow on data (state) in "a" using the round key in "RoundKey"
  • _mm_aesenclast_si128 Perform the last round of an AES encryption flow on data (state) in "a" using the round key in "RoundKey"
  • _mm_aesimc_si128 Perform the InvMixColumns transformation on "a" and store the result in "dst"
  • _mm_aeskeygenassist_si128 Assist in expanding the AES cipher key by computing steps towards generating a round key for encryption cipher using data from "a" and an 8-bit round constant specified in "imm8"
  • _allow_cpu_features Treat the processor-specific feature(s) specified in "a" as available
  • _andn_u32 Compute the bitwise NOT of 32-bit integer "a" and then AND with b
  • _andn_u64 Compute the bitwise NOT of 64-bit integer "a" and then AND with b

B

  • _bextr_u32 Extract contiguous bits from unsigned 32-bit integer "a", and store the result in "dst"
  • _bextr_u64 Extract contiguous bits from unsigned 64-bit integer "a", and store the result in "dst"
  • _bextr2_u32 Extract contiguous bits from unsigned 32-bit integer "a", and store the result in "dst"
  • _bextr2_u64 Extract contiguous bits from unsigned 64-bit integer "a", and store the result in "dst"
  • _bit_scan_forward Set "dst" to the index of the lowest set bit in 32-bit integer "a"
  • _bit_scan_reverse Set "dst" to the index of the highest set bit in 32-bit integer "a"
  • _BitScanForward Set "index" to the index of the lowest set bit in 32-bit integer "mask"
  • _BitScanForward64 Set "index" to the index of the lowest set bit in 64-bit integer "mask"
  • _BitScanReverse Set "index" to the index of the highest set bit in 32-bit integer "mask"
  • _BitScanReverse64 Set "index" to the index of the highest set bit in 64-bit integer "mask"
  • _bittest Return the bit at index "b" of 32-bit integer "a".
  • _bittest64 Return the bit at index "b" of 64-bit integer "a".
  • _bittestandcomplement Return the bit at index "b" of 32-bit integer "a", and set that bit to its complement
  • _bittestandcomplement64 Return the bit at index "b" of 64-bit integer "a", and set that bit to its complement
  • _bittestandreset Return the bit at index "b" of 32-bit integer "a", and set that bit to zero
  • _bittestandreset64 Return the bit at index "b" of 64-bit integer "a", and set that bit to zero
  • _bittestandset Return the bit at index "b" of 32-bit integer "a", and set that bit to one
  • _bittestandset64 Return the bit at index "b" of 64-bit integer "a", and set that bit to one
  • _blsi_u32 Extract the lowest set bit from unsigned 32-bit integer "a" and set the corresponding bit in "dst"
  • _blsi_u64 Extract the lowest set bit from unsigned 64-bit integer "a" and set the corresponding bit in "dst"
  • _blsmsk_u32 Set all the lower bits of "dst" up to and including the lowest set bit in unsigned 32-bit integer "a"
  • _blsmsk_u64 Set all the lower bits of "dst" up to and including the lowest set bit in unsigned 64-bit integer "a"
  • _blsr_u32 Copy all bits from unsigned 32-bit integer "a" to "dst", and reset (set to 0) the bit in "dst" that corresponds to the lowest set bit in "a"
  • _blsr_u64 Copy all bits from unsigned 64-bit integer "a" to "dst", and reset (set to 0) the bit in "dst" that corresponds to the lowest set bit in "a"
  • _bnd_chk_ptr_bounds Checks if ["q", "q" + "size" - 1] is within the lower and upper bounds of "q" and throws a #BR if not
  • _bnd_chk_ptr_lbounds Checks if "q" is within its lower bound, and throws a #BR if not.
  • _bnd_chk_ptr_ubounds Checks if "q" is within its upper bound, and throws a #BR if not.
  • _bnd_copy_ptr_bounds Make a pointer with the value of "q" and bounds set to the bounds of "r" (e
  • _bnd_get_ptr_lbound Return the lower bound of "q".
  • _bnd_get_ptr_ubound Return the upper bound of "q".
  • _bnd_init_ptr_bounds Make a pointer with the value of "q" and open bounds, which allow the pointer to access the entire virtual address space
  • _bnd_narrow_ptr_bounds Narrow the bounds for pointer "q" to the intersection of the bounds of "r" and the bounds ["q", "q" + "size" - 1]
  • _bnd_set_ptr_bounds Make a pointer with the value of "srcmem" and bounds set to ["srcmem", "srcmem" + "size" - 1]
  • _bnd_store_ptr_bounds Stores the bounds of "ptr_val" pointer in memory at address "ptr_addr"
  • _bswap Reverse the byte order of 32-bit integer "a", and store the result in "dst"
  • _bswap64 Reverse the byte order of 64-bit integer "a", and store the result in "dst"
  • _bzhi_u32 Copy all bits from unsigned 32-bit integer "a" to "dst", and reset (set to 0) the high bits in "dst" starting at "index"
  • _bzhi_u64 Copy all bits from unsigned 64-bit integer "a" to "dst", and reset (set to 0) the high bits in "dst" starting at "index"

C

  • _castf32_u32 Cast from type float to type unsigned __int32 without conversion. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.
  • _castf64_u64 Cast from type double to type unsigned __int64 without conversion
  • _castu32_f32 Cast from type unsigned __int32 to type float without conversion. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.
  • _castu64_f64 Cast from type unsigned __int64 to type double without conversion
  • _mm_cldemote Hint to hardware that the cache line that contains "p" should be demoted from the cache closest to the processor core to a level more distant from the processor core
  • _mm_clflushopt Invalidate and flush the cache line that contains "p" from all levels of the cache hierarchy
  • _mm_clmulepi64_si128 Perform a carry-less multiplication of two 64-bit integers, selected from "a" and "b" according to "imm8"
  • _clrssbsy Mark shadow stack pointed to by "p" as not busy.
  • _mm_clwb Write back to memory the cache line that contains "p" from any level of the cache hierarchy in the cache coherence domain
  • _mm_cvtph_ps Convert packed half-precision (16-bit) floating-point elements in "a" to packed single-precision floating-point elements
  • _mm256_cvtph_ps Convert packed half-precision (16-bit) floating-point elements in "a" to packed single-precision floating-point elements
  • _mm_cvtps_ph Convert packed single-precision floating-point elements in "a" to packed half-precision (16-bit) floating-point elements
  • _mm256_cvtps_ph Convert packed single-precision floating-point elements in "a" to packed half-precision (16-bit) floating-point elements
  • _cvtsh_ss Convert the half-precision (16-bit) floating-point value "a" to a single-precision floating-point value
  • _cvtss_sh Convert the single-precision floating-point value "a" to a half-precision (16-bit) floating-point value

D

  • _directstoreu_u32 Store 32-bit integer from "val" into memory using direct store.
  • _directstoreu_u64 Store 64-bit integer from "val" into memory using direct store.

E

  • _encls_u32 Invoke the Intel SGX enclave system (privileged) leaf function specified by "a"
  • _enclu_u32 Invoke the Intel SGX enclave user (non-privilege) leaf function specified by "a"
  • _enclv_u32 Invoke the Intel SGX enclave virtualized (VMM) leaf function specified by "a"

F

  • _fxrstor Reload the x87 FPU, MMX technology, XMM, and MXCSR registers from the 512-byte memory image at "mem_addr"
  • _fxrstor64 Reload the x87 FPU, MMX technology, XMM, and MXCSR registers from the 512-byte memory image at "mem_addr"
  • _fxsave Save the current state of the x87 FPU, MMX technology, XMM, and MXCSR registers to a 512-byte memory location at "mem_addr"
  • _fxsave64 Save the current state of the x87 FPU, MMX technology, XMM, and MXCSR registers to a 512-byte memory location at "mem_addr"

G

  • _get_ssp If CET is enabled, read the low 32-bits of the current shadow stack pointer

I

  • _inc_ssp Increment the shadow stack pointer by 4 times the value specified in bits [7:0] of "a"
  • _incsspd Increment the shadow stack pointer by 4 times the value specified in bits [7:0] of "a"
  • _incsspq Increment the shadow stack pointer by 8 times the value specified in bits [7:0] of "a"
  • _invpcid Invalidate mappings in the Translation Lookaside Buffers (TLBs) and paging-structure caches for the processor context identifier (PCID) specified by "descriptor" based on the invalidation type specified in "type"

L

  • _loadbe_i16 Load 16 bits from memory, perform a byte swap operation, and store the result in "dst"
  • _loadbe_i32 Load 32 bits from memory, perform a byte swap operation, and store the result in "dst"
  • _loadbe_i64 Load 64 bits from memory, perform a byte swap operation, and store the result in "dst"
  • _lrotl Shift the bits of unsigned long integer "a" left by the number of bits specified in "shift"
  • _lrotr Shift the bits of unsigned long integer "a" right by the number of bits specified in "shift"
  • _lzcnt_u32 Count the number of leading zero bits in unsigned 32-bit integer "a"
  • _lzcnt_u64 Count the number of leading zero bits in unsigned 64-bit integer "a"

M

  • _may_i_use_cpu_feature Dynamically query the processor to determine if the processor-specific feature(s) specified in "a" are available
  • _mm_monitor Arm address monitoring hardware using the address specified in "p"
  • _movdir64b Move 64-byte (512-bit) value using direct store from source memory address "src" to destination memory address "dst"
  • _mulx_u32 Multiply unsigned 32-bit integers "a" and "b", store the low 32-bits of the result in "dst", and store the high 32-bits in "hi"
  • _mulx_u64 Multiply unsigned 64-bit integers "a" and "b", store the low 64-bits of the result in "dst", and store the high 64-bits in "hi"
  • _mm_mwait Hint to the processor that it can enter an implementation-dependent-optimized state while waiting for an event or store operation to the address range specified by MONITOR

P

  • _pconfig_u32 Invoke the PCONFIG leaf function specified by "a". The "__data" array contains 3 32-bit elements that may act as input, output, or be unused, depending on the semantics of the specified leaf function
  • _pdep_u32 Deposit contiguous low bits from unsigned 32-bit integer "a" to "dst" at the corresponding bit locations specified by "mask"
  • _pdep_u64 Deposit contiguous low bits from unsigned 64-bit integer "a" to "dst" at the corresponding bit locations specified by "mask"
  • _pext_u32 Extract bits from unsigned 32-bit integer "a" at the corresponding bit locations specified by "mask" to contiguous low bits in "dst"
  • _pext_u64 Extract bits from unsigned 64-bit integer "a" at the corresponding bit locations specified by "mask" to contiguous low bits in "dst"
  • _mm_popcnt_u32 Count the number of bits set to 1 in unsigned 32-bit integer "a"
  • _mm_popcnt_u64 Count the number of bits set to 1 in unsigned 64-bit integer "a"
  • _popcnt32 Count the number of bits set to 1 in 32-bit integer "a", and return that count in "dst"
  • _popcnt64 Count the number of bits set to 1 in 64-bit integer "a", and return that count in "dst"
  • _mm_prefetch Other Fetch the line of data from memory that contains address "p" to a location in the cache heirarchy specified by the locality hint "i"
  • _ptwrite32 Insert the 32-bit data from "a" into a Processor Trace stream via a PTW packet
  • _ptwrite64 Insert the 64-bit data from "a" into a Processor Trace stream via a PTW packet

R

  • _rdpid_u32 Copy the IA32_TSC_AUX MSR (signature value) into "dst".
  • _rdpmc Read the Performance Monitor Counter (PMC) specified by "a", and store up to 64-bits in "dst"
  • _rdrand16_step Read a hardware generated 16-bit random value and store the result in "val"
  • _rdrand32_step Read a hardware generated 32-bit random value and store the result in "val"
  • _rdrand64_step Read a hardware generated 64-bit random value and store the result in "val"
  • _rdseed16_step Read a 16-bit NIST SP800-90B and SP800-90C compliant random value and store in "val"
  • _rdseed32_step Read a 32-bit NIST SP800-90B and SP800-90C compliant random value and store in "val"
  • _rdseed64_step Read a 64-bit NIST SP800-90B and SP800-90C compliant random value and store in "val"
  • _rdsspd_i32 Read the low 32-bits of the current shadow stack pointer, and store the result in "dst"
  • _rdsspq_i64 Read the current shadow stack pointer, and store the result in "dst"
  • _rdtsc Copy the current 64-bit value of the processor's time-stamp counter into "dst"
  • __rdtscp Copy the current 64-bit value of the processor's time-stamp counter into "dst", and store the IA32_TSC_AUX MSR (signature value) into memory at "mem_addr"
  • _readfsbase_u32 Read the FS segment base register and store the 32-bit result in "dst"
  • _readfsbase_u64 Read the FS segment base register and store the 64-bit result in "dst"
  • _readgsbase_u32 Read the GS segment base register and store the 32-bit result in "dst"
  • _readgsbase_u64 Read the GS segment base register and store the 64-bit result in "dst"
  • _rotl Shift the bits of unsigned 32-bit integer "a" left by the number of bits specified in "shift"
  • _rotl64 Shift the bits of unsigned 64-bit integer "a" left by the number of bits specified in "shift"
  • _rotr Shift the bits of unsigned 32-bit integer "a" right by the number of bits specified in "shift"
  • _rotr64 Shift the bits of unsigned 64-bit integer "a" right by the number of bits specified in "shift"
  • _rotwl Shift the bits of unsigned 16-bit integer "a" left by the number of bits specified in "shift"
  • _rotwr Shift the bits of unsigned 16-bit integer "a" right by the number of bits specified in "shift"
  • _rstorssp Restore the saved shadow stack pointer from the shadow stack restore token previously created on shadow stack by saveprevssp

S

  • _saveprevssp Save the previous shadow stack pointer context.
  • _setssbsy Mark shadow stack pointed to by IA32_PL0_SSP as busy.
  • _mm_sha1msg1_epu32 Perform an intermediate calculation for the next four SHA1 message values (unsigned 32-bit integers) using previous message values from "a" and "b"
  • _mm_sha1msg2_epu32 Perform the final calculation for the next four SHA1 message values (unsigned 32-bit integers) using the intermediate result in "a" and the previous message values in "b"
  • _mm_sha1nexte_epu32 Calculate SHA1 state variable E after four rounds of operation from the current SHA1 state variable "a", add that value to the scheduled values (unsigned 32-bit integers) in "b"
  • _mm_sha1rnds4_epu32 Perform four rounds of SHA1 operation using an initial SHA1 state (A,B,C,D) from "a" and some pre-computed sum of the next 4 round message values (unsigned 32-bit integers), and state variable E from "b", and store the updated SHA1 state (A,B,C,D) in "dst"
  • _mm_sha256msg1_epu32 Perform an intermediate calculation for the next four SHA256 message values (unsigned 32-bit integers) using previous message values from "a" and "b"
  • _mm_sha256msg2_epu32 Perform the final calculation for the next four SHA256 message values (unsigned 32-bit integers) using previous message values from "a" and "b"
  • _mm_sha256rnds2_epu32 Perform 2 rounds of SHA256 operation using an initial SHA256 state (C,D,G,H) from "a", an initial SHA256 state (A,B,E,F) from "b", and a pre-computed sum of the next 2 round message values (unsigned 32-bit integers) and the corresponding round constants from "k", and store the updated SHA256 state (A,B,E,F) in "dst"
  • _storebe_i16 Perform a bit swap operation of the 16 bits in "data", and store the results to memory
  • _storebe_i32 Perform a bit swap operation of the 32 bits in "data", and store the results to memory
  • _storebe_i64 Perform a bit swap operation of the 64 bits in "data", and store the results to memory
  • _subborrow_u32 Add unsigned 8-bit borrow "b_in" (carry flag) to unsigned 32-bit integer "b", and subtract the result from unsigned 32-bit integer "a"
  • _subborrow_u64 Add unsigned 8-bit borrow "b_in" (carry flag) to unsigned 64-bit integer "b", and subtract the result from unsigned 64-bit integer "a"

T

  • _tpause Directs the processor to enter an implementation-dependent optimized state until the TSC reaches or exceeds the value specified in "counter"
  • _mm_tzcnt_32 Count the number of trailing zero bits in unsigned 32-bit integer "a"
  • _mm_tzcnt_64 Count the number of trailing zero bits in unsigned 64-bit integer "a"
  • _tzcnt_u32 Count the number of trailing zero bits in unsigned 32-bit integer "a"
  • _tzcnt_u64 Count the number of trailing zero bits in unsigned 64-bit integer "a"

U

  • _umonitor Sets up a linear address range to be monitored by hardware and activates the monitor
  • _umwait Directs the processor to enter an implementation-dependent optimized state while monitoring a range of addresses

W

  • _wbinvd Write back and flush internal caches. Initiate writing-back and flushing of external caches.
  • _wbnoinvd Write back and do not flush internal caches. Initiate writing-back without flushing of external caches.
  • _writefsbase_u32 Write the unsigned 32-bit integer "a" to the FS segment base register
  • _writefsbase_u64 Write the unsigned 64-bit integer "a" to the FS segment base register
  • _writegsbase_u32 Write the unsigned 32-bit integer "a" to the GS segment base register
  • _writegsbase_u64 Write the unsigned 64-bit integer "a" to the GS segment base register
  • _wrssd Write 32-bit value in "val" to a shadow stack page in memory specified by "p"
  • _wrssq Write 64-bit value in "val" to a shadow stack page in memory specified by "p"
  • _wrussd Write 32-bit value in "val" to a user shadow stack page in memory specified by "p"
  • _wrussq Write 64-bit value in "val" to a user shadow stack page in memory specified by "p"

X

  • _xabort Force an RTM abort. The EAX register is updated to reflect an XABORT instruction caused the abort, and the "imm8" parameter will be provided in bits [31:24] of EAX. Following an RTM abort, the logical processor resumes execution at the fallback address computed through the outermost XBEGIN instruction.
  • _xbegin Specify the start of an RTM code region. If the logical processor was not already in transactional execution, then this call causes the logical processor to transition into transactional execution. On an RTM abort, the logical processor discards all architectural register and memory updates performed during the RTM execution, restores architectural state, and starts execution beginning at the fallback address computed from the outermost XBEGIN instruction. Return status of ~0 (0xFFFF) if continuing inside transaction
  • _xend Specify the end of an RTM code region. If this corresponds to the outermost scope, the logical processor will attempt to commit the logical processor state atomically. If the commit fails, the logical processor will perform an RTM abort.
  • _xgetbv Copy up to 64-bits from the value of the extended control register (XCR) specified by "a" into "dst"
  • _xrstor Perform a full or partial restore of the enabled processor states using the state information stored in memory at "mem_addr"
  • _xrstor64 Perform a full or partial restore of the enabled processor states using the state information stored in memory at "mem_addr"
  • _xrstors Perform a full or partial restore of the enabled processor states using the state information stored in memory at "mem_addr"
  • _xrstors64 Perform a full or partial restore of the enabled processor states using the state information stored in memory at "mem_addr"
  • _xsave Perform a full or partial save of the enabled processor states to memory at "mem_addr"
  • _xsave64 Perform a full or partial save of the enabled processor states to memory at "mem_addr"
  • _xsavec Perform a full or partial save of the enabled processor states to memory at "mem_addr"
  • _xsavec64 Perform a full or partial save of the enabled processor states to memory at "mem_addr"
  • _xsaveopt Perform a full or partial save of the enabled processor states to memory at "mem_addr"
  • _xsaveopt64 Perform a full or partial save of the enabled processor states to memory at "mem_addr"
  • _xsaves Perform a full or partial save of the enabled processor states to memory at "mem_addr"
  • _xsaves64 Perform a full or partial save of the enabled processor states to memory at "mem_addr"
  • _xsetbv Copy 64-bits from "val" to the extended control register (XCR) specified by "a"
  • _xtest Query the transactional execution status, return 1 if inside a transactionally executing RTM or HLE region


Categories

  • Application-Targeted
  • Arithmetic
  • Bit Manipulation
  • Cast
  • Compare
  • Convert
  • Cryptography
  • Elementary Math Functions
  • General Support
  • Load
  • Logical
  • Miscellaneous
  • Move
  • OS-Targeted
  • Probability/Statistics
  • Random
  • Set
  • Shift
  • Special Math Functions
  • Store
  • String Compare
  • Swizzle
  • Trigonometry


Application-Targeted

None

None

  • _mm_clmulepi64_si128 Perform a carry-less multiplication of two 64-bit integers, selected from "a" and "b" according to "imm8"


Arithmetic

A D E F H I M P R S U

A

  • _mm_add_epi8 Add packed 8-bit integers in "a" and "b", and store the results in "dst"
  • _mm256_add_epi8 Add packed 8-bit integers in "a" and "b", and store the results in "dst"
  • _mm_add_epi16 Add packed 16-bit integers in "a" and "b", and store the results in "dst"
  • _mm256_add_epi16 Add packed 16-bit integers in "a" and "b", and store the results in "dst"
  • _mm_add_epi32 Add packed 32-bit integers in "a" and "b", and store the results in "dst"
  • _mm256_add_epi32 Add packed 32-bit integers in "a" and "b", and store the results in "dst"
  • _mm_add_epi64 Add packed 64-bit integers in "a" and "b", and store the results in "dst"
  • _mm256_add_epi64 Add packed 64-bit integers in "a" and "b", and store the results in "dst"
  • _mm_add_pd Add packed double-precision floating-point elements in "a" and "b"
  • _mm256_add_pd Add packed double-precision floating-point elements in "a" and "b"
  • _mm_add_pi8 Add packed 8-bit integers in "a" and "b", and store the results in "dst"
  • _mm_add_pi16 Add packed 16-bit integers in "a" and "b", and store the results in "dst"
  • _mm_add_pi32 Add packed 32-bit integers in "a" and "b", and store the results in "dst"
  • _mm_add_ps Add packed single-precision floating-point elements in "a" and "b"
  • _mm256_add_ps Add packed single-precision floating-point elements in "a" and "b"
  • _mm_add_sd Add the lower double-precision floating-point element in "a" and "b"
  • _mm_add_si64 Add 64-bit integers "a" and "b", and store the result in "dst".
  • _mm_add_ss Add the lower single-precision floating-point element in "a" and "b"
  • _addcarry_u32 Add unsigned 32-bit integers "a" and "b" with unsigned 8-bit carry-in "c_in" (carry flag), and store the unsigned 32-bit result in "out", and the carry-out in "dst" (carry or overflow flag)
  • _addcarry_u64 Add unsigned 64-bit integers "a" and "b" with unsigned 8-bit carry-in "c_in" (carry flag), and store the unsigned 64-bit result in "out", and the carry-out in "dst" (carry or overflow flag)
  • _addcarryx_u32 Add unsigned 32-bit integers "a" and "b" with unsigned 8-bit carry-in "c_in" (carry or overflow flag), and store the unsigned 32-bit result in "out", and the carry-out in "dst" (carry or overflow flag)
  • _addcarryx_u64 Add unsigned 64-bit integers "a" and "b" with unsigned 8-bit carry-in "c_in" (carry or overflow flag), and store the unsigned 64-bit result in "out", and the carry-out in "dst" (carry or overflow flag)
  • _mm_adds_epi8 Add packed 8-bit integers in "a" and "b" using saturation, and store the results in "dst"
  • _mm256_adds_epi8 Add packed 8-bit integers in "a" and "b" using saturation, and store the results in "dst"
  • _mm_adds_epi16 Add packed 16-bit integers in "a" and "b" using saturation, and store the results in "dst"
  • _mm256_adds_epi16 Add packed 16-bit integers in "a" and "b" using saturation, and store the results in "dst"
  • _mm_adds_epu8 Add packed unsigned 8-bit integers in "a" and "b" using saturation
  • _mm256_adds_epu8 Add packed unsigned 8-bit integers in "a" and "b" using saturation
  • _mm_adds_epu16 Add packed unsigned 16-bit integers in "a" and "b" using saturation
  • _mm256_adds_epu16 Add packed unsigned 16-bit integers in "a" and "b" using saturation
  • _mm_adds_pi8 Add packed 8-bit integers in "a" and "b" using saturation, and store the results in "dst"
  • _mm_adds_pi16 Add packed 16-bit integers in "a" and "b" using saturation, and store the results in "dst"
  • _mm_adds_pu8 Add packed unsigned 8-bit integers in "a" and "b" using saturation
  • _mm_adds_pu16 Add packed unsigned 16-bit integers in "a" and "b" using saturation
  • _mm_addsub_pd Alternatively add and subtract packed double-precision floating-point elements in "a" to/from packed elements in "b"
  • _mm256_addsub_pd Alternatively add and subtract packed double-precision floating-point elements in "a" to/from packed elements in "b"
  • _mm_addsub_ps Alternatively add and subtract packed single-precision floating-point elements in "a" to/from packed elements in "b"
  • _mm256_addsub_ps Alternatively add and subtract packed single-precision floating-point elements in "a" to/from packed elements in "b"

D

  • _mm_div_epi8 Divide packed 8-bit integers in "a" by packed elements in "b", and store the truncated results in "dst"
  • _mm256_div_epi8 Divide packed 8-bit integers in "a" by packed elements in "b", and store the truncated results in "dst"
  • _mm_div_epi16 Divide packed 16-bit integers in "a" by packed elements in "b", and store the truncated results in "dst"
  • _mm256_div_epi16 Divide packed 16-bit integers in "a" by packed elements in "b", and store the truncated results in "dst"
  • _mm_div_epi32 Divide packed 32-bit integers in "a" by packed elements in "b", and store the truncated results in "dst"
  • _mm256_div_epi32 Divide packed 32-bit integers in "a" by packed elements in "b", and store the truncated results in "dst"
  • _mm_div_epi64 Divide packed 64-bit integers in "a" by packed elements in "b", and store the truncated results in "dst"
  • _mm256_div_epi64 Divide packed 64-bit integers in "a" by packed elements in "b", and store the truncated results in "dst"
  • _mm_div_epu8 Divide packed unsigned 8-bit integers in "a" by packed elements in "b", and store the truncated results in "dst"
  • _mm256_div_epu8 Divide packed unsigned 8-bit integers in "a" by packed elements in "b", and store the truncated results in "dst"
  • _mm_div_epu16 Divide packed unsigned 16-bit integers in "a" by packed elements in "b", and store the truncated results in "dst"
  • _mm256_div_epu16 Divide packed unsigned 16-bit integers in "a" by packed elements in "b", and store the truncated results in "dst"
  • _mm_div_epu32 Divide packed unsigned 32-bit integers in "a" by packed elements in "b", and store the truncated results in "dst"
  • _mm256_div_epu32 Divide packed unsigned 32-bit integers in "a" by packed elements in "b", and store the truncated results in "dst"
  • _mm_div_epu64 Divide packed unsigned 64-bit integers in "a" by packed elements in "b", and store the truncated results in "dst"
  • _mm256_div_epu64 Divide packed unsigned 64-bit integers in "a" by packed elements in "b", and store the truncated results in "dst"
  • _mm_div_pd Divide packed double-precision floating-point elements in "a" by packed elements in "b"
  • _mm256_div_pd Divide packed double-precision floating-point elements in "a" by packed elements in "b"
  • _mm_div_ps Divide packed single-precision floating-point elements in "a" by packed elements in "b"
  • _mm256_div_ps Divide packed single-precision floating-point elements in "a" by packed elements in "b"
  • _mm_div_sd Divide the lower double-precision floating-point element in "a" by the lower double-precision floating-point element in "b"
  • _mm_div_ss Divide the lower single-precision floating-point element in "a" by the lower single-precision floating-point element in "b"
  • _mm_dp_pd Conditionally multiply the packed double-precision floating-point elements in "a" and "b" using the high 4 bits in "imm8", sum the four products, and conditionally store the sum in "dst" using the low 4 bits of "imm8"
  • _mm_dp_ps Conditionally multiply the packed single-precision floating-point elements in "a" and "b" using the high 4 bits in "imm8", sum the four products, and conditionally store the sum in "dst" using the low 4 bits of "imm8"
  • _mm256_dp_ps Conditionally multiply the packed single-precision floating-point elements in "a" and "b" using the high 4 bits in "imm8", sum the four products, and conditionally store the sum in "dst" using the low 4 bits of "imm8"

E

  • _mm_erf_pd Compute the error function of packed double-precision floating-point elements in "a"

F

  • _mm_fmadd_pd Multiply packed double-precision floating-point elements in "a" and "b", add the intermediate result to packed elements in "c"
  • _mm256_fmadd_pd Multiply packed double-precision floating-point elements in "a" and "b", add the intermediate result to packed elements in "c"
  • _mm_fmadd_ps Multiply packed single-precision floating-point elements in "a" and "b", add the intermediate result to packed elements in "c"
  • _mm256_fmadd_ps Multiply packed single-precision floating-point elements in "a" and "b", add the intermediate result to packed elements in "c"
  • _mm_fmadd_sd Multiply the lower double-precision floating-point elements in "a" and "b", and add the intermediate result to the lower element in "c"
  • _mm_fmadd_ss Multiply the lower single-precision floating-point elements in "a" and "b", and add the intermediate result to the lower element in "c"
  • _mm_fmaddsub_pd Multiply packed double-precision floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result
  • _mm256_fmaddsub_pd Multiply packed double-precision floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result
  • _mm_fmaddsub_ps Multiply packed single-precision floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result
  • _mm256_fmaddsub_ps Multiply packed single-precision floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result
  • _mm_fmsub_pd Multiply packed double-precision floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result
  • _mm256_fmsub_pd Multiply packed double-precision floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result
  • _mm_fmsub_ps Multiply packed single-precision floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result
  • _mm256_fmsub_ps Multiply packed single-precision floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result
  • _mm_fmsub_sd Multiply the lower double-precision floating-point elements in "a" and "b", and subtract the lower element in "c" from the intermediate result
  • _mm_fmsub_ss Multiply the lower single-precision floating-point elements in "a" and "b", and subtract the lower element in "c" from the intermediate result
  • _mm_fmsubadd_pd Multiply packed double-precision floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result
  • _mm256_fmsubadd_pd Multiply packed double-precision floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result
  • _mm_fmsubadd_ps Multiply packed single-precision floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result
  • _mm256_fmsubadd_ps Multiply packed single-precision floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result
  • _mm_fnmadd_pd Multiply packed double-precision floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c"
  • _mm256_fnmadd_pd Multiply packed double-precision floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c"
  • _mm_fnmadd_ps Multiply packed single-precision floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c"
  • _mm256_fnmadd_ps Multiply packed single-precision floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c"
  • _mm_fnmadd_sd Multiply the lower double-precision floating-point elements in "a" and "b", and add the negated intermediate result to the lower element in "c"
  • _mm_fnmadd_ss Multiply the lower single-precision floating-point elements in "a" and "b", and add the negated intermediate result to the lower element in "c"
  • _mm_fnmsub_pd Multiply packed double-precision floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result
  • _mm256_fnmsub_pd Multiply packed double-precision floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result
  • _mm_fnmsub_ps Multiply packed single-precision floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result
  • _mm256_fnmsub_ps Multiply packed single-precision floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result
  • _mm_fnmsub_sd Multiply the lower double-precision floating-point elements in "a" and "b", and subtract the lower element in "c" from the negated intermediate result
  • _mm_fnmsub_ss Multiply the lower single-precision floating-point elements in "a" and "b", and subtract the lower element in "c" from the negated intermediate result

H

  • _mm_hadd_epi16 Horizontally add adjacent pairs of 16-bit integers in "a" and "b", and pack the signed 16-bit results in "dst"
  • _mm256_hadd_epi16 Horizontally add adjacent pairs of 16-bit integers in "a" and "b", and pack the signed 16-bit results in "dst"
  • _mm_hadd_epi32 Horizontally add adjacent pairs of 32-bit integers in "a" and "b", and pack the signed 32-bit results in "dst"
  • _mm256_hadd_epi32 Horizontally add adjacent pairs of 32-bit integers in "a" and "b", and pack the signed 32-bit results in "dst"
  • _mm_hadd_pd Horizontally add adjacent pairs of double-precision floating-point elements in "a" and "b", and pack the results in "dst"
  • _mm256_hadd_pd Horizontally add adjacent pairs of double-precision floating-point elements in "a" and "b", and pack the results in "dst"
  • _mm_hadd_pi16 Horizontally add adjacent pairs of 16-bit integers in "a" and "b", and pack the signed 16-bit results in "dst"
  • _mm_hadd_pi32 Horizontally add adjacent pairs of 32-bit integers in "a" and "b", and pack the signed 32-bit results in "dst"
  • _mm_hadd_ps Horizontally add adjacent pairs of single-precision floating-point elements in "a" and "b", and pack the results in "dst"
  • _mm256_hadd_ps Horizontally add adjacent pairs of single-precision floating-point elements in "a" and "b", and pack the results in "dst"
  • _mm_hadds_epi16 Horizontally add adjacent pairs of 16-bit integers in "a" and "b" using saturation, and pack the signed 16-bit results in "dst"
  • _mm256_hadds_epi16 Horizontally add adjacent pairs of 16-bit integers in "a" and "b" using saturation, and pack the signed 16-bit results in "dst"
  • _mm_hadds_pi16 Horizontally add adjacent pairs of 16-bit integers in "a" and "b" using saturation, and pack the signed 16-bit results in "dst"
  • _mm_hsub_epi16 Horizontally subtract adjacent pairs of 16-bit integers in "a" and "b", and pack the signed 16-bit results in "dst"
  • _mm256_hsub_epi16 Horizontally subtract adjacent pairs of 16-bit integers in "a" and "b", and pack the signed 16-bit results in "dst"
  • _mm_hsub_epi32 Horizontally subtract adjacent pairs of 32-bit integers in "a" and "b", and pack the signed 32-bit results in "dst"
  • _mm256_hsub_epi32 Horizontally subtract adjacent pairs of 32-bit integers in "a" and "b", and pack the signed 32-bit results in "dst"
  • _mm_hsub_pd Horizontally subtract adjacent pairs of double-precision floating-point elements in "a" and "b", and pack the results in "dst"
  • _mm256_hsub_pd Horizontally subtract adjacent pairs of double-precision floating-point elements in "a" and "b", and pack the results in "dst"
  • _mm_hsub_pi16 Horizontally subtract adjacent pairs of 16-bit integers in "a" and "b", and pack the signed 16-bit results in "dst"
  • _mm_hsub_pi32 Horizontally subtract adjacent pairs of 32-bit integers in "a" and "b", and pack the signed 32-bit results in "dst"
  • _mm_hsub_ps Horizontally add adjacent pairs of single-precision floating-point elements in "a" and "b", and pack the results in "dst"
  • _mm256_hsub_ps Horizontally add adjacent pairs of single-precision floating-point elements in "a" and "b", and pack the results in "dst"
  • _mm_hsubs_epi16 Horizontally subtract adjacent pairs of 16-bit integers in "a" and "b" using saturation, and pack the signed 16-bit results in "dst"
  • _mm256_hsubs_epi16 Horizontally subtract adjacent pairs of 16-bit integers in "a" and "b" using saturation, and pack the signed 16-bit results in "dst"
  • _mm_hsubs_pi16 Horizontally subtract adjacent pairs of 16-bit integers in "a" and "b" using saturation, and pack the signed 16-bit results in "dst"

I

  • _mm_idiv_epi32 Divide packed 32-bit integers in "a" by packed elements in "b", and store the truncated results in "dst"
  • _mm256_idiv_epi32 Divide packed 32-bit integers in "a" by packed elements in "b", and store the truncated results in "dst"
  • _mm_idivrem_epi32 Divide packed 32-bit integers in "a" by packed elements in "b", store the truncated results in "dst", and store the remainders as packed 32-bit integers into memory at "mem_addr"
  • _mm256_idivrem_epi32 Divide packed 32-bit integers in "a" by packed elements in "b", store the truncated results in "dst", and store the remainders as packed 32-bit integers into memory at "mem_addr"
  • _mm_irem_epi32 Divide packed 32-bit integers in "a" by packed elements in "b", and store the remainders as packed 32-bit integers in "dst"
  • _mm256_irem_epi32 Divide packed 32-bit integers in "a" by packed elements in "b", and store the remainders as packed 32-bit integers in "dst"

M

  • _mm_madd_epi16 Multiply packed signed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers
  • _mm256_madd_epi16 Multiply packed signed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers
  • _mm_madd_pi16 Multiply packed 16-bit integers in "a" and "b", producing intermediate 32-bit integers
  • _mm_maddubs_epi16 Vertically multiply each unsigned 8-bit integer from "a" with the corresponding signed 8-bit integer from "b", producing intermediate signed 16-bit integers
  • _mm256_maddubs_epi16 Vertically multiply each unsigned 8-bit integer from "a" with the corresponding signed 8-bit integer from "b", producing intermediate signed 16-bit integers
  • _mm_maddubs_pi16 Vertically multiply each unsigned 8-bit integer from "a" with the corresponding signed 8-bit integer from "b", producing intermediate signed 16-bit integers
  • _mm_mpsadbw_epu8 Compute the sum of absolute differences (SADs) of quadruplets of unsigned 8-bit integers in "a" compared to those in "b", and store the 16-bit results in "dst"
  • _mm_mul_epi32 Multiply the low 32-bit integers from each packed 64-bit element in "a" and "b", and store the signed 64-bit results in "dst"
  • _mm256_mul_epi32 Multiply the low 32-bit integers from each packed 64-bit element in "a" and "b", and store the signed 64-bit results in "dst"
  • _mm_mul_epu32 Multiply the low unsigned 32-bit integers from each packed 64-bit element in "a" and "b", and store the unsigned 64-bit results in "dst"
  • _mm256_mul_epu32 Multiply the low unsigned 32-bit integers from each packed 64-bit element in "a" and "b", and store the unsigned 64-bit results in "dst"
  • _mm_mul_pd Multiply packed double-precision floating-point elements in "a" and "b"
  • _mm256_mul_pd Multiply packed double-precision floating-point elements in "a" and "b"
  • _mm_mul_ps Multiply packed single-precision floating-point elements in "a" and "b"
  • _mm256_mul_ps Multiply packed single-precision floating-point elements in "a" and "b"
  • _mm_mul_sd Multiply the lower double-precision floating-point element in "a" and "b"
  • _mm_mul_ss Multiply the lower single-precision floating-point element in "a" and "b"
  • _mm_mul_su32 Multiply the low unsigned 32-bit integers from "a" and "b", and store the unsigned 64-bit result in "dst"
  • _mm_mulhi_epi16 Multiply the packed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst"
  • _mm256_mulhi_epi16 Multiply the packed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst"
  • _mm_mulhi_epu16 Multiply the packed unsigned 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst"
  • _mm256_mulhi_epu16 Multiply the packed unsigned 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst"
  • _mm_mulhi_pi16 Multiply the packed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst"
  • _mm_mulhi_pu16 Multiply the packed unsigned 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst"
  • _mm_mulhrs_epi16 Multiply packed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers
  • _mm256_mulhrs_epi16 Multiply packed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers
  • _mm_mulhrs_pi16 Multiply packed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers
  • _mm_mullo_epi16 Multiply the packed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the low 16 bits of the intermediate integers in "dst"
  • _mm256_mullo_epi16 Multiply the packed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the low 16 bits of the intermediate integers in "dst"
  • _mm_mullo_epi32 Multiply the packed 32-bit integers in "a" and "b", producing intermediate 64-bit integers, and store the low 32 bits of the intermediate integers in "dst"
  • _mm256_mullo_epi32 Multiply the packed 32-bit integers in "a" and "b", producing intermediate 64-bit integers, and store the low 32 bits of the intermediate integers in "dst"
  • _mm_mullo_pi16 Multiply the packed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the low 16 bits of the intermediate integers in "dst"
  • _mulx_u32 Multiply unsigned 32-bit integers "a" and "b", store the low 32-bits of the result in "dst", and store the high 32-bits in "hi"
  • _mulx_u64 Multiply unsigned 64-bit integers "a" and "b", store the low 64-bits of the result in "dst", and store the high 64-bits in "hi"

P

  • _m_paddb Add packed 8-bit integers in "a" and "b", and store the results in "dst"
  • _m_paddd Add packed 32-bit integers in "a" and "b", and store the results in "dst"
  • _m_paddsb Add packed 8-bit integers in "a" and "b" using saturation, and store the results in "dst"
  • _m_paddsw Add packed 16-bit integers in "a" and "b" using saturation, and store the results in "dst"
  • _m_paddusb Add packed unsigned 8-bit integers in "a" and "b" using saturation
  • _m_paddusw Add packed unsigned 16-bit integers in "a" and "b" using saturation
  • _m_paddw Add packed 16-bit integers in "a" and "b", and store the results in "dst"
  • _m_pmaddwd Multiply packed 16-bit integers in "a" and "b", producing intermediate 32-bit integers
  • _m_pmulhuw Multiply the packed unsigned 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst"
  • _m_pmulhw Multiply the packed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst"
  • _m_pmullw Multiply the packed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the low 16 bits of the intermediate integers in "dst"
  • _m_psadbw Compute the absolute differences of packed unsigned 8-bit integers in "a" and "b", then horizontally sum each consecutive 8 differences to produce four unsigned 16-bit integers, and pack these unsigned 16-bit integers in the low 16 bits of "dst"
  • _m_psubb Subtract packed 8-bit integers in "b" from packed 8-bit integers in "a"
  • _m_psubd Subtract packed 32-bit integers in "b" from packed 32-bit integers in "a"
  • _m_psubsb Subtract packed 8-bit integers in "b" from packed 8-bit integers in "a" using saturation
  • _m_psubsw Subtract packed 16-bit integers in "b" from packed 16-bit integers in "a" using saturation
  • _m_psubusb Subtract packed unsigned 8-bit integers in "b" from packed unsigned 8-bit integers in "a" using saturation
  • _m_psubusw Subtract packed unsigned 16-bit integers in "b" from packed unsigned 16-bit integers in "a" using saturation
  • _m_psubw Subtract packed 16-bit integers in "b" from packed 16-bit integers in "a"

R

  • _mm_rem_epi8 Divide packed 8-bit integers in "a" by packed elements in "b", and store the remainders as packed 32-bit integers in "dst"
  • _mm256_rem_epi8 Divide packed 8-bit integers in "a" by packed elements in "b", and store the remainders as packed 32-bit integers in "dst"
  • _mm_rem_epi16 Divide packed 16-bit integers in "a" by packed elements in "b", and store the remainders as packed 32-bit integers in "dst"
  • _mm256_rem_epi16 Divide packed 16-bit integers in "a" by packed elements in "b", and store the remainders as packed 32-bit integers in "dst"
  • _mm_rem_epi32 Divide packed 32-bit integers in "a" by packed elements in "b", and store the remainders as packed 32-bit integers in "dst"
  • _mm256_rem_epi32 Divide packed 32-bit integers in "a" by packed elements in "b", and store the remainders as packed 32-bit integers in "dst"
  • _mm_rem_epi64 Divide packed 64-bit integers in "a" by packed elements in "b", and store the remainders as packed 32-bit integers in "dst"
  • _mm256_rem_epi64 Divide packed 64-bit integers in "a" by packed elements in "b", and store the remainders as packed 32-bit integers in "dst"
  • _mm_rem_epu8 Divide packed unsigned 8-bit integers in "a" by packed elements in "b", and store the remainders as packed unsigned 32-bit integers in "dst"
  • _mm256_rem_epu8 Divide packed unsigned 8-bit integers in "a" by packed elements in "b", and store the remainders as packed unsigned 32-bit integers in "dst"
  • _mm_rem_epu16 Divide packed unsigned 16-bit integers in "a" by packed elements in "b", and store the remainders as packed unsigned 32-bit integers in "dst"
  • _mm256_rem_epu16 Divide packed unsigned 16-bit integers in "a" by packed elements in "b", and store the remainders as packed unsigned 32-bit integers in "dst"
  • _mm_rem_epu32 Divide packed unsigned 32-bit integers in "a" by packed elements in "b", and store the remainders as packed unsigned 32-bit integers in "dst"
  • _mm256_rem_epu32 Divide packed unsigned 32-bit integers in "a" by packed elements in "b", and store the remainders as packed unsigned 32-bit integers in "dst"
  • _mm_rem_epu64 Divide packed unsigned 64-bit integers in "a" by packed elements in "b", and store the remainders as packed unsigned 32-bit integers in "dst"
  • _mm256_rem_epu64 Divide packed unsigned 64-bit integers in "a" by packed elements in "b", and store the remainders as packed unsigned 32-bit integers in "dst"

S

  • _mm_sad_epu8 Compute the absolute differences of packed unsigned 8-bit integers in "a" and "b", then horizontally sum each consecutive 8 differences to produce two unsigned 16-bit integers, and pack these unsigned 16-bit integers in the low 16 bits of 64-bit elements in "dst"
  • _mm256_sad_epu8 Compute the absolute differences of packed unsigned 8-bit integers in "a" and "b", then horizontally sum each consecutive 8 differences to produce four unsigned 16-bit integers, and pack these unsigned 16-bit integers in the low 16 bits of 64-bit elements in "dst"
  • _mm_sad_pu8 Compute the absolute differences of packed unsigned 8-bit integers in "a" and "b", then horizontally sum each consecutive 8 differences to produce four unsigned 16-bit integers, and pack these unsigned 16-bit integers in the low 16 bits of "dst"
  • _mm_sign_epi8 Negate packed 8-bit integers in "a" when the corresponding signed 8-bit integer in "b" is negative
  • _mm256_sign_epi8 Negate packed 8-bit integers in "a" when the corresponding signed 8-bit integer in "b" is negative
  • _mm_sign_epi16 Negate packed 16-bit integers in "a" when the corresponding signed 16-bit integer in "b" is negative
  • _mm256_sign_epi16 Negate packed 16-bit integers in "a" when the corresponding signed 16-bit integer in "b" is negative
  • _mm_sign_epi32 Negate packed 32-bit integers in "a" when the corresponding signed 32-bit integer in "b" is negative
  • _mm256_sign_epi32 Negate packed 32-bit integers in "a" when the corresponding signed 32-bit integer in "b" is negative
  • _mm_sign_pi8 Negate packed 8-bit integers in "a" when the corresponding signed 8-bit integer in "b" is negative
  • _mm_sign_pi16 Negate packed 16-bit integers in "a" when the corresponding signed 16-bit integer in "b" is negative
  • _mm_sign_pi32 Negate packed 32-bit integers in "a" when the corresponding signed 32-bit integer in "b" is negative
  • _mm_sub_epi8 Subtract packed 8-bit integers in "b" from packed 8-bit integers in "a"
  • _mm256_sub_epi8 Subtract packed 8-bit integers in "b" from packed 8-bit integers in "a"
  • _mm_sub_epi16 Subtract packed 16-bit integers in "b" from packed 16-bit integers in "a"
  • _mm256_sub_epi16 Subtract packed 16-bit integers in "b" from packed 16-bit integers in "a"
  • _mm_sub_epi32 Subtract packed 32-bit integers in "b" from packed 32-bit integers in "a"
  • _mm256_sub_epi32 Subtract packed 32-bit integers in "b" from packed 32-bit integers in "a"
  • _mm_sub_epi64 Subtract packed 64-bit integers in "b" from packed 64-bit integers in "a"
  • _mm256_sub_epi64 Subtract packed 64-bit integers in "b" from packed 64-bit integers in "a"
  • _mm_sub_pd Subtract packed double-precision floating-point elements in "b" from packed double-precision floating-point elements in "a"
  • _mm256_sub_pd Subtract packed double-precision floating-point elements in "b" from packed double-precision floating-point elements in "a"
  • _mm_sub_pi8 Subtract packed 8-bit integers in "b" from packed 8-bit integers in "a"
  • _mm_sub_pi16 Subtract packed 16-bit integers in "b" from packed 16-bit integers in "a"
  • _mm_sub_pi32 Subtract packed 32-bit integers in "b" from packed 32-bit integers in "a"
  • _mm_sub_ps Subtract packed single-precision floating-point elements in "b" from packed single-precision floating-point elements in "a"
  • _mm256_sub_ps Subtract packed single-precision floating-point elements in "b" from packed single-precision floating-point elements in "a"
  • _mm_sub_sd Subtract the lower double-precision floating-point element in "b" from the lower double-precision floating-point element in "a"
  • _mm_sub_si64 Subtract 64-bit integer "b" from 64-bit integer "a", and store the result in "dst"
  • _mm_sub_ss Subtract the lower single-precision floating-point element in "b" from the lower single-precision floating-point element in "a"
  • _subborrow_u32 Add unsigned 8-bit borrow "b_in" (carry flag) to unsigned 32-bit integer "b", and subtract the result from unsigned 32-bit integer "a"
  • _subborrow_u64 Add unsigned 8-bit borrow "b_in" (carry flag) to unsigned 64-bit integer "b", and subtract the result from unsigned 64-bit integer "a"
  • _mm_subs_epi8 Subtract packed 8-bit integers in "b" from packed 8-bit integers in "a" using saturation
  • _mm256_subs_epi8 Subtract packed 8-bit integers in "b" from packed 8-bit integers in "a" using saturation
  • _mm_subs_epi16 Subtract packed 16-bit integers in "b" from packed 16-bit integers in "a" using saturation
  • _mm256_subs_epi16 Subtract packed 16-bit integers in "b" from packed 16-bit integers in "a" using saturation
  • _mm_subs_epu8 Subtract packed unsigned 8-bit integers in "b" from packed unsigned 8-bit integers in "a" using saturation
  • _mm256_subs_epu8 Subtract packed unsigned 8-bit integers in "b" from packed unsigned 8-bit integers in "a" using saturation
  • _mm_subs_epu16 Subtract packed unsigned 16-bit integers in "b" from packed unsigned 16-bit integers in "a" using saturation
  • _mm256_subs_epu16 Subtract packed unsigned 16-bit integers in "b" from packed unsigned 16-bit integers in "a" using saturation
  • _mm_subs_pi8 Subtract packed 8-bit integers in "b" from packed 8-bit integers in "a" using saturation
  • _mm_subs_pi16 Subtract packed 16-bit integers in "b" from packed 16-bit integers in "a" using saturation
  • _mm_subs_pu8 Subtract packed unsigned 8-bit integers in "b" from packed unsigned 8-bit integers in "a" using saturation
  • _mm_subs_pu16 Subtract packed unsigned 16-bit integers in "b" from packed unsigned 16-bit integers in "a" using saturation

U

  • _mm_udiv_epi32 Divide packed unsigned 32-bit integers in "a" by packed elements in "b", and store the truncated results in "dst"
  • _mm256_udiv_epi32 Divide packed unsigned 32-bit integers in "a" by packed elements in "b", and store the truncated results in "dst"
  • _mm_udivrem_epi32 Divide packed unsigned 32-bit integers in "a" by packed elements in "b", store the truncated results in "dst", and store the remainders as packed unsigned 32-bit integers into memory at "mem_addr"
  • _mm256_udivrem_epi32 Divide packed unsigned 32-bit integers in "a" by packed elements in "b", store the truncated results in "dst", and store the remainders as packed unsigned 32-bit integers into memory at "mem_addr"
  • _mm_urem_epi32 Divide packed unsigned 32-bit integers in "a" by packed elements in "b", and store the remainders as packed unsigned 32-bit integers in "dst"
  • _mm256_urem_epi32 Divide packed unsigned 32-bit integers in "a" by packed elements in "b", and store the remainders as packed unsigned 32-bit integers in "dst"


Bit Manipulation

A B L P T

A

  • _andn_u32 Compute the bitwise NOT of 32-bit integer "a" and then AND with b
  • _andn_u64 Compute the bitwise NOT of 64-bit integer "a" and then AND with b

B

  • _bextr_u32 Extract contiguous bits from unsigned 32-bit integer "a", and store the result in "dst"
  • _bextr_u64 Extract contiguous bits from unsigned 64-bit integer "a", and store the result in "dst"
  • _bextr2_u32 Extract contiguous bits from unsigned 32-bit integer "a", and store the result in "dst"
  • _bextr2_u64 Extract contiguous bits from unsigned 64-bit integer "a", and store the result in "dst"
  • _bit_scan_forward Set "dst" to the index of the lowest set bit in 32-bit integer "a"
  • _bit_scan_reverse Set "dst" to the index of the highest set bit in 32-bit integer "a"
  • _BitScanForward Set "index" to the index of the lowest set bit in 32-bit integer "mask"
  • _BitScanForward64 Set "index" to the index of the lowest set bit in 64-bit integer "mask"
  • _BitScanReverse Set "index" to the index of the highest set bit in 32-bit integer "mask"
  • _BitScanReverse64 Set "index" to the index of the highest set bit in 64-bit integer "mask"
  • _bittest Return the bit at index "b" of 32-bit integer "a".
  • _bittest64 Return the bit at index "b" of 64-bit integer "a".
  • _bittestandcomplement Return the bit at index "b" of 32-bit integer "a", and set that bit to its complement
  • _bittestandcomplement64 Return the bit at index "b" of 64-bit integer "a", and set that bit to its complement
  • _bittestandreset Return the bit at index "b" of 32-bit integer "a", and set that bit to zero
  • _bittestandreset64 Return the bit at index "b" of 64-bit integer "a", and set that bit to zero
  • _bittestandset Return the bit at index "b" of 32-bit integer "a", and set that bit to one
  • _bittestandset64 Return the bit at index "b" of 64-bit integer "a", and set that bit to one
  • _blsi_u32 Extract the lowest set bit from unsigned 32-bit integer "a" and set the corresponding bit in "dst"
  • _blsi_u64 Extract the lowest set bit from unsigned 64-bit integer "a" and set the corresponding bit in "dst"
  • _blsmsk_u32 Set all the lower bits of "dst" up to and including the lowest set bit in unsigned 32-bit integer "a"
  • _blsmsk_u64 Set all the lower bits of "dst" up to and including the lowest set bit in unsigned 64-bit integer "a"
  • _blsr_u32 Copy all bits from unsigned 32-bit integer "a" to "dst", and reset (set to 0) the bit in "dst" that corresponds to the lowest set bit in "a"
  • _blsr_u64 Copy all bits from unsigned 64-bit integer "a" to "dst", and reset (set to 0) the bit in "dst" that corresponds to the lowest set bit in "a"
  • _bswap Reverse the byte order of 32-bit integer "a", and store the result in "dst"
  • _bswap64 Reverse the byte order of 64-bit integer "a", and store the result in "dst"
  • _bzhi_u32 Copy all bits from unsigned 32-bit integer "a" to "dst", and reset (set to 0) the high bits in "dst" starting at "index"
  • _bzhi_u64 Copy all bits from unsigned 64-bit integer "a" to "dst", and reset (set to 0) the high bits in "dst" starting at "index"

L

  • _lzcnt_u32 Count the number of leading zero bits in unsigned 32-bit integer "a"
  • _lzcnt_u64 Count the number of leading zero bits in unsigned 64-bit integer "a"

P

  • _pdep_u32 Deposit contiguous low bits from unsigned 32-bit integer "a" to "dst" at the corresponding bit locations specified by "mask"
  • _pdep_u64 Deposit contiguous low bits from unsigned 64-bit integer "a" to "dst" at the corresponding bit locations specified by "mask"
  • _pext_u32 Extract bits from unsigned 32-bit integer "a" at the corresponding bit locations specified by "mask" to contiguous low bits in "dst"
  • _pext_u64 Extract bits from unsigned 64-bit integer "a" at the corresponding bit locations specified by "mask" to contiguous low bits in "dst"
  • _mm_popcnt_u32 Count the number of bits set to 1 in unsigned 32-bit integer "a"
  • _mm_popcnt_u64 Count the number of bits set to 1 in unsigned 64-bit integer "a"
  • _popcnt32 Count the number of bits set to 1 in 32-bit integer "a", and return that count in "dst"
  • _popcnt64 Count the number of bits set to 1 in 64-bit integer "a", and return that count in "dst"

T

  • _mm_tzcnt_32 Count the number of trailing zero bits in unsigned 32-bit integer "a"
  • _mm_tzcnt_64 Count the number of trailing zero bits in unsigned 64-bit integer "a"
  • _tzcnt_u32 Count the number of trailing zero bits in unsigned 32-bit integer "a"
  • _tzcnt_u64 Count the number of trailing zero bits in unsigned 64-bit integer "a"


Cast

C Z

C

  • _castf32_u32 Cast from type float to type unsigned __int32 without conversion. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.
  • _castf64_u64 Cast from type double to type unsigned __int64 without conversion
  • _mm_castpd_ps Cast vector of type __m128d to type __m128. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.
  • _mm256_castpd_ps Cast vector of type __m256d to type __m256. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.
  • _mm_castpd_si128 Cast vector of type __m128d to type __m128i. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.
  • _mm256_castpd_si256 Casts vector of type __m256d to type __m256i. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.
  • _mm256_castpd128_pd256 Casts vector of type __m128d to type __m256d; the upper 128 bits of the result are undefined
  • _mm256_castpd256_pd128 Casts vector of type __m256d to type __m128d. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.
  • _mm_castps_pd Cast vector of type __m128 to type __m128d. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.
  • _mm256_castps_pd Cast vector of type __m256 to type __m256d. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.
  • _mm_castps_si128 Cast vector of type __m128 to type __m128i. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.
  • _mm256_castps_si256 Casts vector of type __m256 to type __m256i. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.
  • _mm256_castps128_ps256 Casts vector of type __m128 to type __m256; the upper 128 bits of the result are undefined
  • _mm256_castps256_ps128 Casts vector of type __m256 to type __m128. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.
  • _mm_castsi128_pd Cast vector of type __m128i to type __m128d. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.
  • _mm_castsi128_ps Cast vector of type __m128i to type __m128. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.
  • _mm256_castsi128_si256 Casts vector of type __m128i to type __m256i; the upper 128 bits of the result are undefined
  • _mm256_castsi256_pd Casts vector of type __m256i to type __m256d. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.
  • _mm256_castsi256_ps Casts vector of type __m256i to type __m256. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.
  • _mm256_castsi256_si128 Casts vector of type __m256i to type __m128i. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.
  • _castu32_f32 Cast from type unsigned __int32 to type float without conversion. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.
  • _castu64_f64 Cast from type unsigned __int64 to type double without conversion

Z

  • _mm256_zextpd128_pd256 Casts vector of type __m128d to type __m256d; the upper 128 bits of the result are zeroed
  • _mm256_zextps128_ps256 Casts vector of type __m128 to type __m256; the upper 128 bits of the result are zeroed
  • _mm256_zextsi128_si256 Casts vector of type __m128i to type __m256i; the upper 128 bits of the result are zeroed


Compare

C P U

C

  • _mm_cmp_pd Compare packed double-precision floating-point elements in "a" and "b"
  • _mm256_cmp_pd Compare packed double-precision floating-point elements in "a" and "b"
  • _mm_cmp_ps Compare packed single-precision floating-point elements in "a" and "b"
  • _mm256_cmp_ps Compare packed single-precision floating-point elements in "a" and "b"
  • _mm_cmp_sd Compare the lower double-precision floating-point element in "a" and "b"
  • _mm_cmp_ss Compare the lower single-precision floating-point element in "a" and "b"
  • _mm_cmpeq_epi8 Compare packed 8-bit integers in "a" and "b" for equality, and store the results in "dst"
  • _mm256_cmpeq_epi8 Compare packed 8-bit integers in "a" and "b" for equality, and store the results in "dst"
  • _mm_cmpeq_epi16 Compare packed 16-bit integers in "a" and "b" for equality, and store the results in "dst"
  • _mm256_cmpeq_epi16 Compare packed 16-bit integers in "a" and "b" for equality, and store the results in "dst"
  • _mm_cmpeq_epi32 Compare packed 32-bit integers in "a" and "b" for equality, and store the results in "dst"
  • _mm256_cmpeq_epi32 Compare packed 32-bit integers in "a" and "b" for equality, and store the results in "dst"
  • _mm_cmpeq_epi64 Compare packed 64-bit integers in "a" and "b" for equality, and store the results in "dst"
  • _mm256_cmpeq_epi64 Compare packed 64-bit integers in "a" and "b" for equality, and store the results in "dst"
  • _mm_cmpeq_pd Compare packed double-precision floating-point elements in "a" and "b" for equality
  • _mm_cmpeq_pi8 Compare packed 8-bit integers in "a" and "b" for equality, and store the results in "dst"
  • _mm_cmpeq_pi16 Compare packed 16-bit integers in "a" and "b" for equality, and store the results in "dst"
  • _mm_cmpeq_pi32 Compare packed 32-bit integers in "a" and "b" for equality, and store the results in "dst"
  • _mm_cmpeq_ps Compare packed single-precision floating-point elements in "a" and "b" for equality
  • _mm_cmpeq_sd Compare the lower double-precision floating-point elements in "a" and "b" for equality
  • _mm_cmpeq_ss Compare the lower single-precision floating-point elements in "a" and "b" for equality
  • _mm_cmpge_pd Compare packed double-precision floating-point elements in "a" and "b" for greater-than-or-equal
  • _mm_cmpge_ps Compare packed single-precision floating-point elements in "a" and "b" for greater-than-or-equal
  • _mm_cmpge_sd Compare the lower double-precision floating-point elements in "a" and "b" for greater-than-or-equal
  • _mm_cmpge_ss Compare the lower single-precision floating-point elements in "a" and "b" for greater-than-or-equal
  • _mm_cmpgt_epi8 Compare packed 8-bit integers in "a" and "b" for greater-than, and store the results in "dst"
  • _mm256_cmpgt_epi8 Compare packed 8-bit integers in "a" and "b" for greater-than, and store the results in "dst"
  • _mm_cmpgt_epi16 Compare packed 16-bit integers in "a" and "b" for greater-than, and store the results in "dst"
  • _mm256_cmpgt_epi16 Compare packed 16-bit integers in "a" and "b" for greater-than, and store the results in "dst"
  • _mm_cmpgt_epi32 Compare packed 32-bit integers in "a" and "b" for greater-than, and store the results in "dst"
  • _mm256_cmpgt_epi32 Compare packed 32-bit integers in "a" and "b" for greater-than, and store the results in "dst"
  • _mm_cmpgt_epi64 Compare packed 64-bit integers in "a" and "b" for greater-than, and store the results in "dst"
  • _mm256_cmpgt_epi64 Compare packed 64-bit integers in "a" and "b" for greater-than, and store the results in "dst"
  • _mm_cmpgt_pd Compare packed double-precision floating-point elements in "a" and "b" for greater-than
  • _mm_cmpgt_pi8 Compare packed 8-bit integers in "a" and "b" for greater-than, and store the results in "dst"
  • _mm_cmpgt_pi16 Compare packed 16-bit integers in "a" and "b" for greater-than, and store the results in "dst"
  • _mm_cmpgt_pi32 Compare packed 32-bit integers in "a" and "b" for greater-than, and store the results in "dst"
  • _mm_cmpgt_ps Compare packed single-precision floating-point elements in "a" and "b" for greater-than
  • _mm_cmpgt_sd Compare the lower double-precision floating-point elements in "a" and "b" for greater-than
  • _mm_cmpgt_ss Compare the lower single-precision floating-point elements in "a" and "b" for greater-than
  • _mm_cmple_pd Compare packed double-precision floating-point elements in "a" and "b" for less-than-or-equal
  • _mm_cmple_ps Compare packed single-precision floating-point elements in "a" and "b" for less-than-or-equal
  • _mm_cmple_sd Compare the lower double-precision floating-point elements in "a" and "b" for less-than-or-equal
  • _mm_cmple_ss Compare the lower single-precision floating-point elements in "a" and "b" for less-than-or-equal
  • _mm_cmplt_epi8 Compare packed 8-bit integers in "a" and "b" for less-than, and store the results in "dst"
  • _mm_cmplt_epi16 Compare packed 16-bit integers in "a" and "b" for less-than, and store the results in "dst"
  • _mm_cmplt_epi32 Compare packed 32-bit integers in "a" and "b" for less-than, and store the results in "dst"
  • _mm_cmplt_pd Compare packed double-precision floating-point elements in "a" and "b" for less-than
  • _mm_cmplt_ps Compare packed single-precision floating-point elements in "a" and "b" for less-than
  • _mm_cmplt_sd Compare the lower double-precision floating-point elements in "a" and "b" for less-than
  • _mm_cmplt_ss Compare the lower single-precision floating-point elements in "a" and "b" for less-than
  • _mm_cmpneq_pd Compare packed double-precision floating-point elements in "a" and "b" for not-equal
  • _mm_cmpneq_ps Compare packed single-precision floating-point elements in "a" and "b" for not-equal
  • _mm_cmpneq_sd Compare the lower double-precision floating-point elements in "a" and "b" for not-equal
  • _mm_cmpneq_ss Compare the lower single-precision floating-point elements in "a" and "b" for not-equal
  • _mm_cmpnge_pd Compare packed double-precision floating-point elements in "a" and "b" for not-greater-than-or-equal
  • _mm_cmpnge_ps Compare packed single-precision floating-point elements in "a" and "b" for not-greater-than-or-equal
  • _mm_cmpnge_sd Compare the lower double-precision floating-point elements in "a" and "b" for not-greater-than-or-equal
  • _mm_cmpnge_ss Compare the lower single-precision floating-point elements in "a" and "b" for not-greater-than-or-equal
  • _mm_cmpngt_pd Compare packed double-precision floating-point elements in "a" and "b" for not-greater-than
  • _mm_cmpngt_ps Compare packed single-precision floating-point elements in "a" and "b" for not-greater-than
  • _mm_cmpngt_sd Compare the lower double-precision floating-point elements in "a" and "b" for not-greater-than
  • _mm_cmpngt_ss Compare the lower single-precision floating-point elements in "a" and "b" for not-greater-than
  • _mm_cmpnle_pd Compare packed double-precision floating-point elements in "a" and "b" for not-less-than-or-equal
  • _mm_cmpnle_ps Compare packed single-precision floating-point elements in "a" and "b" for not-less-than-or-equal
  • _mm_cmpnle_sd Compare the lower double-precision floating-point elements in "a" and "b" for not-less-than-or-equal
  • _mm_cmpnle_ss Compare the lower single-precision floating-point elements in "a" and "b" for not-less-than-or-equal
  • _mm_cmpnlt_pd Compare packed double-precision floating-point elements in "a" and "b" for not-less-than
  • _mm_cmpnlt_ps Compare packed single-precision floating-point elements in "a" and "b" for not-less-than
  • _mm_cmpnlt_sd Compare the lower double-precision floating-point elements in "a" and "b" for not-less-than
  • _mm_cmpnlt_ss Compare the lower single-precision floating-point elements in "a" and "b" for not-less-than
  • _mm_cmpord_pd Compare packed double-precision floating-point elements in "a" and "b" to see if neither is NaN
  • _mm_cmpord_ps Compare packed single-precision floating-point elements in "a" and "b" to see if neither is NaN
  • _mm_cmpord_sd Compare the lower double-precision floating-point elements in "a" and "b" to see if neither is NaN
  • _mm_cmpord_ss Compare the lower single-precision floating-point elements in "a" and "b" to see if neither is NaN
  • _mm_cmpunord_pd Compare packed double-precision floating-point elements in "a" and "b" to see if either is NaN
  • _mm_cmpunord_ps Compare packed single-precision floating-point elements in "a" and "b" to see if either is NaN
  • _mm_cmpunord_sd Compare the lower double-precision floating-point elements in "a" and "b" to see if either is NaN
  • _mm_cmpunord_ss Compare the lower single-precision floating-point elements in "a" and "b" to see if either is NaN
  • _mm_comieq_sd Compare the lower double-precision floating-point element in "a" and "b" for equality
  • _mm_comieq_ss Compare the lower single-precision floating-point element in "a" and "b" for equality
  • _mm_comige_sd Compare the lower double-precision floating-point element in "a" and "b" for greater-than-or-equal
  • _mm_comige_ss Compare the lower single-precision floating-point element in "a" and "b" for greater-than-or-equal
  • _mm_comigt_sd Compare the lower double-precision floating-point element in "a" and "b" for greater-than
  • _mm_comigt_ss Compare the lower single-precision floating-point element in "a" and "b" for greater-than
  • _mm_comile_sd Compare the lower double-precision floating-point element in "a" and "b" for less-than-or-equal
  • _mm_comile_ss Compare the lower single-precision floating-point element in "a" and "b" for less-than-or-equal
  • _mm_comilt_sd Compare the lower double-precision floating-point element in "a" and "b" for less-than
  • _mm_comilt_ss Compare the lower single-precision floating-point element in "a" and "b" for less-than
  • _mm_comineq_sd Compare the lower double-precision floating-point element in "a" and "b" for not-equal
  • _mm_comineq_ss Compare the lower single-precision floating-point element in "a" and "b" for not-equal

P

  • _m_pcmpeqb Compare packed 8-bit integers in "a" and "b" for equality, and store the results in "dst"
  • _m_pcmpeqd Compare packed 32-bit integers in "a" and "b" for equality, and store the results in "dst"
  • _m_pcmpeqw Compare packed 16-bit integers in "a" and "b" for equality, and store the results in "dst"
  • _m_pcmpgtb Compare packed 8-bit integers in "a" and "b" for greater-than, and store the results in "dst"
  • _m_pcmpgtd Compare packed 32-bit integers in "a" and "b" for greater-than, and store the results in "dst"
  • _m_pcmpgtw Compare packed 16-bit integers in "a" and "b" for greater-than, and store the results in "dst"

U

  • _mm_ucomieq_sd Compare the lower double-precision floating-point element in "a" and "b" for equality
  • _mm_ucomieq_ss Compare the lower single-precision floating-point element in "a" and "b" for equality
  • _mm_ucomige_sd Compare the lower double-precision floating-point element in "a" and "b" for greater-than-or-equal
  • _mm_ucomige_ss Compare the lower single-precision floating-point element in "a" and "b" for greater-than-or-equal
  • _mm_ucomigt_sd Compare the lower double-precision floating-point element in "a" and "b" for greater-than
  • _mm_ucomigt_ss Compare the lower single-precision floating-point element in "a" and "b" for greater-than
  • _mm_ucomile_sd Compare the lower double-precision floating-point element in "a" and "b" for less-than-or-equal
  • _mm_ucomile_ss Compare the lower single-precision floating-point element in "a" and "b" for less-than-or-equal
  • _mm_ucomilt_sd Compare the lower double-precision floating-point element in "a" and "b" for less-than
  • _mm_ucomilt_ss Compare the lower single-precision floating-point element in "a" and "b" for less-than
  • _mm_ucomineq_sd Compare the lower double-precision floating-point element in "a" and "b" for not-equal
  • _mm_ucomineq_ss Compare the lower single-precision floating-point element in "a" and "b" for not-equal


Convert

C F P T

C

  • _mm_cvt_pi2ps Convert packed 32-bit integers in "b" to packed single-precision floating-point elements
  • _mm_cvt_ps2pi Convert packed single-precision floating-point elements in "a" to packed 32-bit integers
  • _mm_cvt_si2ss Convert the 32-bit integer "b" to a single-precision floating-point element
  • _mm_cvt_ss2si Convert the lower single-precision floating-point element in "a" to a 32-bit integer
  • _mm_cvtepi16_epi32 Sign extend packed 16-bit integers in "a" to packed 32-bit integers
  • _mm256_cvtepi16_epi32 Sign extend packed 16-bit integers in "a" to packed 32-bit integers
  • _mm_cvtepi16_epi64 Sign extend packed 16-bit integers in "a" to packed 64-bit integers
  • _mm256_cvtepi16_epi64 Sign extend packed 16-bit integers in "a" to packed 64-bit integers
  • _mm_cvtepi32_epi64 Sign extend packed 32-bit integers in "a" to packed 64-bit integers
  • _mm256_cvtepi32_epi64 Sign extend packed 32-bit integers in "a" to packed 64-bit integers
  • _mm_cvtepi32_pd Convert packed 32-bit integers in "a" to packed double-precision floating-point elements
  • _mm256_cvtepi32_pd Convert packed 32-bit integers in "a" to packed double-precision floating-point elements
  • _mm_cvtepi32_ps Convert packed 32-bit integers in "a" to packed single-precision floating-point elements
  • _mm256_cvtepi32_ps Convert packed 32-bit integers in "a" to packed single-precision floating-point elements
  • _mm_cvtepi8_epi16 Sign extend packed 8-bit integers in "a" to packed 16-bit integers
  • _mm256_cvtepi8_epi16 Sign extend packed 8-bit integers in "a" to packed 16-bit integers
  • _mm_cvtepi8_epi32 Sign extend packed 8-bit integers in "a" to packed 32-bit integers
  • _mm256_cvtepi8_epi32 Sign extend packed 8-bit integers in "a" to packed 32-bit integers
  • _mm_cvtepi8_epi64 Sign extend packed 8-bit integers in the low 8 bytes of "a" to packed 64-bit integers
  • _mm256_cvtepi8_epi64 Sign extend packed 8-bit integers in the low 8 bytes of "a" to packed 64-bit integers
  • _mm_cvtepu16_epi32 Zero extend packed unsigned 16-bit integers in "a" to packed 32-bit integers
  • _mm256_cvtepu16_epi32 Zero extend packed unsigned 16-bit integers in "a" to packed 32-bit integers
  • _mm_cvtepu16_epi64 Zero extend packed unsigned 16-bit integers in "a" to packed 64-bit integers
  • _mm256_cvtepu16_epi64 Zero extend packed unsigned 16-bit integers in "a" to packed 64-bit integers
  • _mm_cvtepu32_epi64 Zero extend packed unsigned 32-bit integers in "a" to packed 64-bit integers
  • _mm256_cvtepu32_epi64 Zero extend packed unsigned 32-bit integers in "a" to packed 64-bit integers
  • _mm_cvtepu8_epi16 Zero extend packed unsigned 8-bit integers in "a" to packed 16-bit integers
  • _mm256_cvtepu8_epi16 Zero extend packed unsigned 8-bit integers in "a" to packed 16-bit integers
  • _mm_cvtepu8_epi32 Zero extend packed unsigned 8-bit integers in "a" to packed 32-bit integers
  • _mm256_cvtepu8_epi32 Zero extend packed unsigned 8-bit integers in "a" to packed 32-bit integers
  • _mm_cvtepu8_epi64 Zero extend packed unsigned 8-bit integers in the low 8 byte sof "a" to packed 64-bit integers
  • _mm256_cvtepu8_epi64 Zero extend packed unsigned 8-bit integers in the low 8 byte sof "a" to packed 64-bit integers
  • _mm_cvtm64_si64 Copy 64-bit integer "a" to "dst".
  • _mm_cvtpd_epi32 Convert packed double-precision floating-point elements in "a" to packed 32-bit integers
  • _mm256_cvtpd_epi32 Convert packed double-precision floating-point elements in "a" to packed 32-bit integers
  • _mm_cvtpd_pi32 Convert packed double-precision floating-point elements in "a" to packed 32-bit integers
  • _mm_cvtpd_ps Convert packed double-precision floating-point elements in "a" to packed single-precision floating-point elements
  • _mm256_cvtpd_ps Convert packed double-precision floating-point elements in "a" to packed single-precision floating-point elements
  • _mm_cvtph_ps Convert packed half-precision (16-bit) floating-point elements in "a" to packed single-precision floating-point elements
  • _mm256_cvtph_ps Convert packed half-precision (16-bit) floating-point elements in "a" to packed single-precision floating-point elements
  • _mm_cvtpi16_ps Convert packed 16-bit integers in "a" to packed single-precision floating-point elements
  • _mm_cvtpi32_pd Convert packed 32-bit integers in "a" to packed double-precision floating-point elements
  • _mm_cvtpi32_ps Convert packed 32-bit integers in "b" to packed single-precision floating-point elements
  • _mm_cvtpi32x2_ps Convert packed 32-bit integers in "a" to packed single-precision floating-point elements
  • _mm_cvtpi8_ps Convert the lower packed 8-bit integers in "a" to packed single-precision floating-point elements
  • _mm_cvtps_epi32 Convert packed single-precision floating-point elements in "a" to packed 32-bit integers
  • _mm256_cvtps_epi32 Convert packed single-precision floating-point elements in "a" to packed 32-bit integers
  • _mm_cvtps_pd Convert packed single-precision floating-point elements in "a" to packed double-precision floating-point elements
  • _mm256_cvtps_pd Convert packed single-precision floating-point elements in "a" to packed double-precision floating-point elements
  • _mm_cvtps_ph Convert packed single-precision floating-point elements in "a" to packed half-precision (16-bit) floating-point elements
  • _mm256_cvtps_ph Convert packed single-precision floating-point elements in "a" to packed half-precision (16-bit) floating-point elements
  • _mm_cvtps_pi8 Convert packed single-precision floating-point elements in "a" to packed 8-bit integers
  • _mm_cvtps_pi16 Convert packed single-precision floating-point elements in "a" to packed 16-bit integers
  • _mm_cvtps_pi32 Convert packed single-precision floating-point elements in "a" to packed 32-bit integers
  • _mm_cvtpu16_ps Convert packed unsigned 16-bit integers in "a" to packed single-precision floating-point elements
  • _mm_cvtpu8_ps Convert the lower packed unsigned 8-bit integers in "a" to packed single-precision floating-point elements
  • _mm_cvtsd_f64 Copy the lower double-precision floating-point element of "a" to "dst"
  • _mm256_cvtsd_f64 Copy the lower double-precision floating-point element of "a" to "dst"
  • _mm_cvtsd_si32 Convert the lower double-precision floating-point element in "a" to a 32-bit integer
  • _mm_cvtsd_si64 Convert the lower double-precision floating-point element in "a" to a 64-bit integer
  • _mm_cvtsd_si64x Convert the lower double-precision floating-point element in "a" to a 64-bit integer
  • _mm_cvtsd_ss Convert the lower double-precision floating-point element in "b" to a single-precision floating-point element
  • _cvtsh_ss Convert the half-precision (16-bit) floating-point value "a" to a single-precision floating-point value
  • _mm_cvtsi128_si32 Copy the lower 32-bit integer in "a" to "dst".
  • _mm_cvtsi128_si64 Copy the lower 64-bit integer in "a" to "dst".
  • _mm_cvtsi128_si64x Copy the lower 64-bit integer in "a" to "dst".
  • _mm256_cvtsi256_si32 Copy the lower 32-bit integer in "a" to "dst".
  • _mm_cvtsi32_sd Convert the 32-bit integer "b" to a double-precision floating-point element
  • _mm_cvtsi32_si64 Copy 32-bit integer "a" to the lower elements of "dst", and zero the upper element of "dst"
  • _mm_cvtsi32_si128 Copy 32-bit integer "a" to the lower elements of "dst", and zero the upper elements of "dst"
  • _mm_cvtsi32_ss Convert the 32-bit integer "b" to a single-precision floating-point element
  • _mm_cvtsi64_m64 Copy 64-bit integer "a" to "dst".
  • _mm_cvtsi64_sd Convert the 64-bit integer "b" to a double-precision floating-point element
  • _mm_cvtsi64_si32 Copy the lower 32-bit integer in "a" to "dst".
  • _mm_cvtsi64_si128 Copy 64-bit integer "a" to the lower element of "dst", and zero the upper element
  • _mm_cvtsi64_ss Convert the 64-bit integer "b" to a single-precision floating-point element
  • _mm_cvtsi64x_sd Convert the 64-bit integer "b" to a double-precision floating-point element
  • _mm_cvtsi64x_si128 Copy 64-bit integer "a" to the lower element of "dst", and zero the upper element
  • _mm_cvtss_f32 Copy the lower single-precision floating-point element of "a" to "dst"
  • _mm256_cvtss_f32 Copy the lower single-precision floating-point element of "a" to "dst"
  • _mm_cvtss_sd Convert the lower single-precision floating-point element in "b" to a double-precision floating-point element
  • _cvtss_sh Convert the single-precision floating-point value "a" to a half-precision (16-bit) floating-point value
  • _mm_cvtss_si32 Convert the lower single-precision floating-point element in "a" to a 32-bit integer
  • _mm_cvtss_si64 Convert the lower single-precision floating-point element in "a" to a 64-bit integer
  • _mm_cvtt_ps2pi Convert packed single-precision floating-point elements in "a" to packed 32-bit integers with truncation
  • _mm_cvtt_ss2si Convert the lower single-precision floating-point element in "a" to a 32-bit integer with truncation
  • _mm_cvttpd_epi32 Convert packed double-precision floating-point elements in "a" to packed 32-bit integers with truncation
  • _mm256_cvttpd_epi32 Convert packed double-precision floating-point elements in "a" to packed 32-bit integers with truncation
  • _mm_cvttpd_pi32 Convert packed double-precision floating-point elements in "a" to packed 32-bit integers with truncation
  • _mm_cvttps_epi32 Convert packed single-precision floating-point elements in "a" to packed 32-bit integers with truncation
  • _mm256_cvttps_epi32 Convert packed single-precision floating-point elements in "a" to packed 32-bit integers with truncation
  • _mm_cvttps_pi32 Convert packed single-precision floating-point elements in "a" to packed 32-bit integers with truncation
  • _mm_cvttsd_si32 Convert the lower double-precision floating-point element in "a" to a 32-bit integer with truncation
  • _mm_cvttsd_si64 Convert the lower double-precision floating-point element in "a" to a 64-bit integer with truncation
  • _mm_cvttsd_si64x Convert the lower double-precision floating-point element in "a" to a 64-bit integer with truncation
  • _mm_cvttss_si32 Convert the lower single-precision floating-point element in "a" to a 32-bit integer with truncation
  • _mm_cvttss_si64 Convert the lower single-precision floating-point element in "a" to a 64-bit integer with truncation

F

  • _m_from_int Copy 32-bit integer "a" to the lower elements of "dst", and zero the upper element of "dst"
  • _m_from_int64 Copy 64-bit integer "a" to "dst".

P

  • _mm_packus_epi32 Convert packed 32-bit integers from "a" and "b" to packed 16-bit integers using unsigned saturation

T

  • _m_to_int Copy the lower 32-bit integer in "a" to "dst".
  • _m_to_int64 Copy 64-bit integer "a" to "dst".


Cryptography

A C S

A

  • _mm_aesdec_si128 Perform one round of an AES decryption flow on data (state) in "a" using the round key in "RoundKey"
  • _mm_aesdeclast_si128 Perform the last round of an AES decryption flow on data (state) in "a" using the round key in "RoundKey"
  • _mm_aesenc_si128 Perform one round of an AES encryption flow on data (state) in "a" using the round key in "RoundKey"
  • _mm_aesenclast_si128 Perform the last round of an AES encryption flow on data (state) in "a" using the round key in "RoundKey"
  • _mm_aesimc_si128 Perform the InvMixColumns transformation on "a" and store the result in "dst"
  • _mm_aeskeygenassist_si128 Assist in expanding the AES cipher key by computing steps towards generating a round key for encryption cipher using data from "a" and an 8-bit round constant specified in "imm8"

C

  • _mm_crc32_u8 Starting with the initial value in "crc", accumulates a CRC32 value for unsigned 8-bit integer "v", and stores the result in "dst"
  • _mm_crc32_u16 Starting with the initial value in "crc", accumulates a CRC32 value for unsigned 16-bit integer "v", and stores the result in "dst"
  • _mm_crc32_u32 Starting with the initial value in "crc", accumulates a CRC32 value for unsigned 32-bit integer "v", and stores the result in "dst"
  • _mm_crc32_u64 Starting with the initial value in "crc", accumulates a CRC32 value for unsigned 64-bit integer "v", and stores the result in "dst"

S

  • _mm_sha1msg1_epu32 Perform an intermediate calculation for the next four SHA1 message values (unsigned 32-bit integers) using previous message values from "a" and "b"
  • _mm_sha1msg2_epu32 Perform the final calculation for the next four SHA1 message values (unsigned 32-bit integers) using the intermediate result in "a" and the previous message values in "b"
  • _mm_sha1nexte_epu32 Calculate SHA1 state variable E after four rounds of operation from the current SHA1 state variable "a", add that value to the scheduled values (unsigned 32-bit integers) in "b"
  • _mm_sha1rnds4_epu32 Perform four rounds of SHA1 operation using an initial SHA1 state (A,B,C,D) from "a" and some pre-computed sum of the next 4 round message values (unsigned 32-bit integers), and state variable E from "b", and store the updated SHA1 state (A,B,C,D) in "dst"
  • _mm_sha256msg1_epu32 Perform an intermediate calculation for the next four SHA256 message values (unsigned 32-bit integers) using previous message values from "a" and "b"
  • _mm_sha256msg2_epu32 Perform the final calculation for the next four SHA256 message values (unsigned 32-bit integers) using previous message values from "a" and "b"
  • _mm_sha256rnds2_epu32 Perform 2 rounds of SHA256 operation using an initial SHA256 state (C,D,G,H) from "a", an initial SHA256 state (A,B,E,F) from "b", and a pre-computed sum of the next 2 round message values (unsigned 32-bit integers) and the corresponding round constants from "k", and store the updated SHA256 state (A,B,E,F) in "dst"


Elementary Math Functions

C E I L P R S

C

  • _mm_cbrt_pd Compute the cube root of packed double-precision floating-point elements in "a"
  • _mm256_cbrt_pd Compute the cube root of packed double-precision floating-point elements in "a"
  • _mm_cbrt_ps Compute the cube root of packed single-precision floating-point elements in "a"
  • _mm256_cbrt_ps Compute the cube root of packed single-precision floating-point elements in "a"
  • _mm_cexp_ps Compute the exponential value of "e" raised to the power of packed complex single-precision floating-point elements in "a"
  • _mm256_cexp_ps Compute the exponential value of "e" raised to the power of packed complex single-precision floating-point elements in "a"
  • _mm_clog_ps Compute the natural logarithm of packed complex single-precision floating-point elements in "a"
  • _mm256_clog_ps Compute the natural logarithm of packed complex single-precision floating-point elements in "a"
  • _mm_csqrt_ps Compute the square root of packed complex single-precision floating-point elements in "a"
  • _mm256_csqrt_ps Compute the square root of packed complex single-precision floating-point elements in "a"

E

  • _mm_exp_pd Compute the exponential value of "e" raised to the power of packed double-precision floating-point elements in "a"
  • _mm256_exp_pd Compute the exponential value of "e" raised to the power of packed double-precision floating-point elements in "a"
  • _mm_exp_ps Compute the exponential value of "e" raised to the power of packed single-precision floating-point elements in "a"
  • _mm256_exp_ps Compute the exponential value of "e" raised to the power of packed single-precision floating-point elements in "a"
  • _mm_exp10_pd Compute the exponential value of 10 raised to the power of packed double-precision floating-point elements in "a"
  • _mm256_exp10_pd Compute the exponential value of 10 raised to the power of packed double-precision floating-point elements in "a"
  • _mm_exp10_ps Compute the exponential value of 10 raised to the power of packed single-precision floating-point elements in "a"
  • _mm256_exp10_ps Compute the exponential value of 10 raised to the power of packed single-precision floating-point elements in "a"
  • _mm_exp2_pd Compute the exponential value of 2 raised to the power of packed double-precision floating-point elements in "a"
  • _mm256_exp2_pd Compute the exponential value of 2 raised to the power of packed double-precision floating-point elements in "a"
  • _mm_exp2_ps Compute the exponential value of 2 raised to the power of packed single-precision floating-point elements in "a"
  • _mm256_exp2_ps Compute the exponential value of 2 raised to the power of packed single-precision floating-point elements in "a"
  • _mm_expm1_pd Compute the exponential value of "e" raised to the power of packed double-precision floating-point elements in "a", subtract one from each element
  • _mm256_expm1_pd Compute the exponential value of "e" raised to the power of packed double-precision floating-point elements in "a", subtract one from each element
  • _mm_expm1_ps Compute the exponential value of "e" raised to the power of packed single-precision floating-point elements in "a", subtract one from each element
  • _mm256_expm1_ps Compute the exponential value of "e" raised to the power of packed single-precision floating-point elements in "a", subtract one from each element

I

  • _mm_invcbrt_pd Compute the inverse cube root of packed double-precision floating-point elements in "a"
  • _mm256_invcbrt_pd Compute the inverse cube root of packed double-precision floating-point elements in "a"
  • _mm_invcbrt_ps Compute the inverse cube root of packed single-precision floating-point elements in "a"
  • _mm256_invcbrt_ps Compute the inverse cube root of packed single-precision floating-point elements in "a"
  • _mm_invsqrt_pd Compute the inverse square root of packed double-precision floating-point elements in "a"
  • _mm256_invsqrt_pd Compute the inverse square root of packed double-precision floating-point elements in "a"
  • _mm_invsqrt_ps Compute the inverse square root of packed single-precision floating-point elements in "a"
  • _mm256_invsqrt_ps Compute the inverse square root of packed single-precision floating-point elements in "a"

L

  • _mm_log_pd Compute the natural logarithm of packed double-precision floating-point elements in "a"
  • _mm256_log_pd Compute the natural logarithm of packed double-precision floating-point elements in "a"
  • _mm_log_ps Compute the natural logarithm of packed single-precision floating-point elements in "a"
  • _mm256_log_ps Compute the natural logarithm of packed single-precision floating-point elements in "a"
  • _mm_log10_pd Compute the base-10 logarithm of packed double-precision floating-point elements in "a"
  • _mm256_log10_pd Compute the base-10 logarithm of packed double-precision floating-point elements in "a"
  • _mm_log10_ps Compute the base-10 logarithm of packed single-precision floating-point elements in "a"
  • _mm256_log10_ps Compute the base-10 logarithm of packed single-precision floating-point elements in "a"
  • _mm_log1p_pd Compute the natural logarithm of one plus packed double-precision floating-point elements in "a"
  • _mm256_log1p_pd Compute the natural logarithm of one plus packed double-precision floating-point elements in "a"
  • _mm_log1p_ps Compute the natural logarithm of one plus packed single-precision floating-point elements in "a"
  • _mm256_log1p_ps Compute the natural logarithm of one plus packed single-precision floating-point elements in "a"
  • _mm_log2_pd Compute the base-2 logarithm of packed double-precision floating-point elements in "a"
  • _mm256_log2_pd Compute the base-2 logarithm of packed double-precision floating-point elements in "a"
  • _mm_log2_ps Compute the base-2 logarithm of packed single-precision floating-point elements in "a"
  • _mm256_log2_ps Compute the base-2 logarithm of packed single-precision floating-point elements in "a"
  • _mm_logb_pd Convert the exponent of each packed double-precision floating-point element in "a" to a double-precision floating-point number representing the integer exponent
  • _mm256_logb_pd Convert the exponent of each packed double-precision floating-point element in "a" to a double-precision floating-point number representing the integer exponent
  • _mm_logb_ps Convert the exponent of each packed single-precision floating-point element in "a" to a single-precision floating-point number representing the integer exponent
  • _mm256_logb_ps Convert the exponent of each packed single-precision floating-point element in "a" to a single-precision floating-point number representing the integer exponent

P

  • _mm_pow_pd Compute the exponential value of packed double-precision floating-point elements in "a" raised by packed elements in "b"
  • _mm256_pow_pd Compute the exponential value of packed double-precision floating-point elements in "a" raised by packed elements in "b"
  • _mm_pow_ps Compute the exponential value of packed single-precision floating-point elements in "a" raised by packed elements in "b"
  • _mm256_pow_ps Compute the exponential value of packed single-precision floating-point elements in "a" raised by packed elements in "b"

R

  • _mm_rcp_ps Compute the approximate reciprocal of packed single-precision floating-point elements in "a"
  • _mm256_rcp_ps Compute the approximate reciprocal of packed single-precision floating-point elements in "a"
  • _mm_rcp_ss Compute the approximate reciprocal of the lower single-precision floating-point element in "a"
  • _mm_rsqrt_ps Compute the approximate reciprocal square root of packed single-precision floating-point elements in "a"
  • _mm256_rsqrt_ps Compute the approximate reciprocal square root of packed single-precision floating-point elements in "a"
  • _mm_rsqrt_ss Compute the approximate reciprocal square root of the lower single-precision floating-point element in "a"

S

  • _mm_sqrt_pd Compute the square root of packed double-precision floating-point elements in "a"
  • _mm256_sqrt_pd Compute the square root of packed double-precision floating-point elements in "a"
  • _mm_sqrt_ps Compute the square root of packed single-precision floating-point elements in "a"
  • _mm256_sqrt_ps Compute the square root of packed single-precision floating-point elements in "a"
  • _mm_sqrt_sd Compute the square root of the lower double-precision floating-point element in "b"
  • _mm_sqrt_ss Compute the square root of the lower single-precision floating-point element in "a"
  • _mm_svml_sqrt_pd Compute the square root of packed double-precision floating-point elements in "a"
  • _mm256_svml_sqrt_pd Compute the square root of packed double-precision floating-point elements in "a"
  • _mm_svml_sqrt_ps Compute the square root of packed single-precision floating-point elements in "a"
  • _mm256_svml_sqrt_ps Compute the square root of packed single-precision floating-point elements in "a"


General Support

A C E F G L M P R S U W X Z

A

  • _allow_cpu_features Treat the processor-specific feature(s) specified in "a" as available

C

  • _mm_clflush Invalidate and flush the cache line that contains "p" from all levels of the cache hierarchy
  • _mm_clflushopt Invalidate and flush the cache line that contains "p" from all levels of the cache hierarchy
  • _mm_clwb Write back to memory the cache line that contains "p" from any level of the cache hierarchy in the cache coherence domain

E

  • _m_empty Empty the MMX state, which marks the x87 FPU registers as available for use by x87 instructions
  • _mm_empty Empty the MMX state, which marks the x87 FPU registers as available for use by x87 instructions

F

  • _mm_free Free aligned memory that was allocated with "_mm_malloc".

G

  • _MM_GET_EXCEPTION_MASK Macro: Get the exception mask bits from the MXCSR control and status register
  • _MM_GET_EXCEPTION_STATE Macro: Get the exception state bits from the MXCSR control and status register
  • _MM_GET_FLUSH_ZERO_MODE Macro: Get the flush zero bits from the MXCSR control and status register
  • _MM_GET_ROUNDING_MODE Macro: Get the rounding mode bits from the MXCSR control and status register
  • _mm_getcsr Get the unsigned 32-bit value of the MXCSR control and status register

L

  • _mm_lfence Perform a serializing operation on all load-from-memory instructions that were issued prior to this instruction

M

  • _mm_malloc Allocate "size" bytes of memory, aligned to the alignment specified in "align"
  • _may_i_use_cpu_feature Dynamically query the processor to determine if the processor-specific feature(s) specified in "a" are available
  • _mm_mfence Perform a serializing operation on all load-from-memory and store-to-memory instructions that were issued prior to this instruction
  • _mm_monitor Arm address monitoring hardware using the address specified in "p"
  • _mm_mwait Hint to the processor that it can enter an implementation-dependent-optimized state while waiting for an event or store operation to the address range specified by MONITOR

P

  • _mm_pause Provide a hint to the processor that the code sequence is a spin-wait loop
  • _mm_prefetch SSE Fetch the line of data from memory that contains address "p" to a location in the cache heirarchy specified by the locality hint "i"
  • _mm_prefetch Other Fetch the line of data from memory that contains address "p" to a location in the cache heirarchy specified by the locality hint "i"

R

  • _rdpid_u32 Copy the IA32_TSC_AUX MSR (signature value) into "dst".
  • _rdpmc Read the Performance Monitor Counter (PMC) specified by "a", and store up to 64-bits in "dst"
  • _rdtsc Copy the current 64-bit value of the processor's time-stamp counter into "dst"
  • __rdtscp Copy the current 64-bit value of the processor's time-stamp counter into "dst", and store the IA32_TSC_AUX MSR (signature value) into memory at "mem_addr"
  • _readfsbase_u32 Read the FS segment base register and store the 32-bit result in "dst"
  • _readfsbase_u64 Read the FS segment base register and store the 64-bit result in "dst"
  • _readgsbase_u32 Read the GS segment base register and store the 32-bit result in "dst"
  • _readgsbase_u64 Read the GS segment base register and store the 64-bit result in "dst"

S

  • _MM_SET_EXCEPTION_MASK Macro: Set the exception mask bits of the MXCSR control and status register to the value in unsigned 32-bit integer "a"
  • _MM_SET_EXCEPTION_STATE Macro: Set the exception state bits of the MXCSR control and status register to the value in unsigned 32-bit integer "a"
  • _MM_SET_FLUSH_ZERO_MODE Macro: Set the flush zero bits of the MXCSR control and status register to the value in unsigned 32-bit integer "a"
  • _MM_SET_ROUNDING_MODE Macro: Set the rounding mode bits of the MXCSR control and status register to the value in unsigned 32-bit integer "a"
  • _mm_setcsr Set the MXCSR control and status register with the value in unsigned 32-bit integer "a"
  • _mm_sfence Perform a serializing operation on all store-to-memory instructions that were issued prior to this instruction

U

  • _mm_undefined_pd Return vector of type __m128d with undefined elements.
  • _mm256_undefined_pd Return vector of type __m256d with undefined elements.
  • _mm_undefined_ps Return vector of type __m128 with undefined elements.
  • _mm256_undefined_ps Return vector of type __m256 with undefined elements.
  • _mm_undefined_si128 Return vector of type __m128i with undefined elements.
  • _mm256_undefined_si256 Return vector of type __m256i with undefined elements.

W

  • _writefsbase_u32 Write the unsigned 32-bit integer "a" to the FS segment base register
  • _writefsbase_u64 Write the unsigned 64-bit integer "a" to the FS segment base register
  • _writegsbase_u32 Write the unsigned 32-bit integer "a" to the GS segment base register
  • _writegsbase_u64 Write the unsigned 64-bit integer "a" to the GS segment base register

X

  • _xabort Force an RTM abort. The EAX register is updated to reflect an XABORT instruction caused the abort, and the "imm8" parameter will be provided in bits [31:24] of EAX. Following an RTM abort, the logical processor resumes execution at the fallback address computed through the outermost XBEGIN instruction.
  • _xbegin Specify the start of an RTM code region. If the logical processor was not already in transactional execution, then this call causes the logical processor to transition into transactional execution. On an RTM abort, the logical processor discards all architectural register and memory updates performed during the RTM execution, restores architectural state, and starts execution beginning at the fallback address computed from the outermost XBEGIN instruction. Return status of ~0 (0xFFFF) if continuing inside transaction
  • _xend Specify the end of an RTM code region. If this corresponds to the outermost scope, the logical processor will attempt to commit the logical processor state atomically. If the commit fails, the logical processor will perform an RTM abort.
  • _xtest Query the transactional execution status, return 1 if inside a transactionally executing RTM or HLE region

Z

  • _mm256_zeroall Zero the contents of all XMM or YMM registers.
  • _mm256_zeroupper Zero the upper 128 bits of all YMM registers; the lower 128-bits of the registers are unmodified


Load

B I L M S

B

  • _mm256_broadcast_pd Broadcast 128 bits from memory (composed of 2 packed double-precision floating-point elements) to all elements of "dst"
  • _mm256_broadcast_ps Broadcast 128 bits from memory (composed of 4 packed single-precision floating-point elements) to all elements of "dst"
  • _mm256_broadcast_sd Broadcast a double-precision floating-point element from memory to all elements of "dst"
  • _mm256_broadcast_ss Broadcast a single-precision floating-point element from memory to all elements of "dst"
  • _mm_broadcast_ss Broadcast a single-precision floating-point element from memory to all elements of "dst"

I

  • _mm_i32gather_epi32 Gather 32-bit integers from memory using 32-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.
  • _mm256_i32gather_epi32 Gather 32-bit integers from memory using 32-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.
  • _mm_i32gather_epi64 Gather 64-bit integers from memory using 32-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.
  • _mm256_i32gather_epi64 Gather 64-bit integers from memory using 32-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.
  • _mm_i32gather_pd Gather double-precision floating-point elements from memory using 32-bit indices
  • _mm256_i32gather_pd Gather double-precision floating-point elements from memory using 32-bit indices
  • _mm_i32gather_ps Gather single-precision floating-point elements from memory using 32-bit indices
  • _mm256_i32gather_ps Gather single-precision floating-point elements from memory using 32-bit indices
  • _mm_i64gather_epi32 Gather 32-bit integers from memory using 64-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.
  • _mm256_i64gather_epi32 Gather 32-bit integers from memory using 64-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.
  • _mm_i64gather_epi64 Gather 64-bit integers from memory using 64-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.
  • _mm256_i64gather_epi64 Gather 64-bit integers from memory using 64-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.
  • _mm_i64gather_pd Gather double-precision floating-point elements from memory using 64-bit indices
  • _mm256_i64gather_pd Gather double-precision floating-point elements from memory using 64-bit indices
  • _mm_i64gather_ps Gather single-precision floating-point elements from memory using 64-bit indices
  • _mm256_i64gather_ps Gather single-precision floating-point elements from memory using 64-bit indices

L

  • _mm_lddqu_si128 Load 128-bits of integer data from unaligned memory into "dst". This intrinsic may perform better than "_mm_loadu_si128" when the data crosses a cache line boundary.
  • _mm256_lddqu_si256 Load 256-bits of integer data from unaligned memory into "dst". This intrinsic may perform better than "_mm256_loadu_si256" when the data crosses a cache line boundary.
  • _mm_load_pd Load 128-bits (composed of 2 packed double-precision floating-point elements) from memory into "dst"
  • _mm256_load_pd Load 256-bits (composed of 4 packed double-precision floating-point elements) from memory into "dst"
  • _mm_load_pd1 Load a double-precision floating-point element from memory into both elements of "dst"
  • _mm_load_ps Load 128-bits (composed of 4 packed single-precision floating-point elements) from memory into "dst"
  • _mm256_load_ps Load 256-bits (composed of 8 packed single-precision floating-point elements) from memory into "dst"
  • _mm_load_ps1 Load a single-precision floating-point element from memory into all elements of "dst"
  • _mm_load_sd Load a double-precision floating-point element from memory into the lower of "dst", and zero the upper element
  • _mm_load_si128 Load 128-bits of integer data from memory into "dst". "mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.
  • _mm256_load_si256 Load 256-bits of integer data from memory into "dst". "mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.
  • _mm_load_ss Load a single-precision floating-point element from memory into the lower of "dst", and zero the upper 3 elements
  • _mm_load1_pd Load a double-precision floating-point element from memory into both elements of "dst"
  • _mm_load1_ps Load a single-precision floating-point element from memory into all elements of "dst"
  • _loadbe_i16 Load 16 bits from memory, perform a byte swap operation, and store the result in "dst"
  • _loadbe_i32 Load 32 bits from memory, perform a byte swap operation, and store the result in "dst"
  • _loadbe_i64 Load 64 bits from memory, perform a byte swap operation, and store the result in "dst"
  • _mm_loaddup_pd Load a double-precision floating-point element from memory into both elements of "dst"
  • _mm_loadh_pd Load a double-precision floating-point element from memory into the upper element of "dst", and copy the lower element from "a" to "dst"
  • _mm_loadh_pi Load 2 single-precision floating-point elements from memory into the upper 2 elements of "dst", and copy the lower 2 elements from "a" to "dst"
  • _mm_loadl_epi64 Load 64-bit integer from memory into the first element of "dst".
  • _mm_loadl_pd Load a double-precision floating-point element from memory into the lower element of "dst", and copy the upper element from "a" to "dst"
  • _mm_loadl_pi Load 2 single-precision floating-point elements from memory into the lower 2 elements of "dst", and copy the upper 2 elements from "a" to "dst"
  • _mm_loadr_pd Load 2 double-precision floating-point elements from memory into "dst" in reverse order
  • _mm_loadr_ps Load 4 single-precision floating-point elements from memory into "dst" in reverse order
  • _mm_loadu_pd Load 128-bits (composed of 2 packed double-precision floating-point elements) from memory into "dst"
  • _mm256_loadu_pd Load 256-bits (composed of 4 packed double-precision floating-point elements) from memory into "dst"
  • _mm_loadu_ps Load 128-bits (composed of 4 packed single-precision floating-point elements) from memory into "dst"
  • _mm256_loadu_ps Load 256-bits (composed of 8 packed single-precision floating-point elements) from memory into "dst"
  • _mm_loadu_si16 Load unaligned 16-bit integer from memory into the first element of "dst"
  • _mm_loadu_si32 Load unaligned 32-bit integer from memory into the first element of "dst"
  • _mm_loadu_si64 Load unaligned 64-bit integer from memory into the first element of "dst"
  • _mm_loadu_si128 Load 128-bits of integer data from memory into "dst". "mem_addr" does not need to be aligned on any particular boundary.
  • _mm256_loadu_si256 Load 256-bits of integer data from memory into "dst". "mem_addr" does not need to be aligned on any particular boundary.
  • _mm256_loadu2_m128 Load two 128-bit values (composed of 4 packed single-precision floating-point elements) from memory, and combine them into a 256-bit value in "dst"
  • _mm256_loadu2_m128d Load two 128-bit values (composed of 2 packed double-precision floating-point elements) from memory, and combine them into a 256-bit value in "dst"
  • _mm256_loadu2_m128i Load two 128-bit values (composed of integer data) from memory, and combine them into a 256-bit value in "dst"

M

  • _mm_mask_i32gather_epi32 Gather 32-bit integers from memory using 32-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8.
  • _mm256_mask_i32gather_epi32 Gather 32-bit integers from memory using 32-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8.
  • _mm_mask_i32gather_epi64 Gather 64-bit integers from memory using 32-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8.
  • _mm256_mask_i32gather_epi64 Gather 64-bit integers from memory using 32-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8.
  • _mm_mask_i32gather_pd Gather double-precision floating-point elements from memory using 32-bit indices
  • _mm256_mask_i32gather_pd Gather double-precision floating-point elements from memory using 32-bit indices
  • _mm_mask_i32gather_ps Gather single-precision floating-point elements from memory using 32-bit indices
  • _mm256_mask_i32gather_ps Gather single-precision floating-point elements from memory using 32-bit indices
  • _mm_mask_i64gather_epi32 Gather 32-bit integers from memory using 64-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8.
  • _mm256_mask_i64gather_epi32 Gather 32-bit integers from memory using 64-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8.
  • _mm_mask_i64gather_epi64 Gather 64-bit integers from memory using 64-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8.
  • _mm256_mask_i64gather_epi64 Gather 64-bit integers from memory using 64-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8.
  • _mm_mask_i64gather_pd Gather double-precision floating-point elements from memory using 64-bit indices
  • _mm256_mask_i64gather_pd Gather double-precision floating-point elements from memory using 64-bit indices
  • _mm_mask_i64gather_ps Gather single-precision floating-point elements from memory using 64-bit indices
  • _mm256_mask_i64gather_ps Gather single-precision floating-point elements from memory using 64-bit indices
  • _mm_maskload_epi32 Load packed 32-bit integers from memory into "dst" using "mask" (elements are zeroed out when the highest bit is not set in the corresponding element)
  • _mm256_maskload_epi32 Load packed 32-bit integers from memory into "dst" using "mask" (elements are zeroed out when the highest bit is not set in the corresponding element)
  • _mm_maskload_epi64 Load packed 64-bit integers from memory into "dst" using "mask" (elements are zeroed out when the highest bit is not set in the corresponding element)
  • _mm256_maskload_epi64 Load packed 64-bit integers from memory into "dst" using "mask" (elements are zeroed out when the highest bit is not set in the corresponding element)
  • _mm256_maskload_pd Load packed double-precision floating-point elements from memory into "dst" using "mask" (elements are zeroed out when the high bit of the corresponding element is not set)
  • _mm_maskload_pd Load packed double-precision floating-point elements from memory into "dst" using "mask" (elements are zeroed out when the high bit of the corresponding element is not set)
  • _mm256_maskload_ps Load packed single-precision floating-point elements from memory into "dst" using "mask" (elements are zeroed out when the high bit of the corresponding element is not set)
  • _mm_maskload_ps Load packed single-precision floating-point elements from memory into "dst" using "mask" (elements are zeroed out when the high bit of the corresponding element is not set)

S

  • _mm_stream_load_si128 Load 128-bits of integer data from memory into "dst" using a non-temporal memory hint
  • _mm256_stream_load_si256 Load 256-bits of integer data from memory into "dst" using a non-temporal memory hint


Logical

A O P T X

A

  • _mm_and_pd Compute the bitwise AND of packed double-precision floating-point elements in "a" and "b"
  • _mm256_and_pd Compute the bitwise AND of packed double-precision floating-point elements in "a" and "b"
  • _mm_and_ps Compute the bitwise AND of packed single-precision floating-point elements in "a" and "b"
  • _mm256_and_ps Compute the bitwise AND of packed single-precision floating-point elements in "a" and "b"
  • _mm_and_si64 Compute the bitwise AND of 64 bits (representing integer data) in "a" and "b"
  • _mm_and_si128 Compute the bitwise AND of 128 bits (representing integer data) in "a" and "b"
  • _mm256_and_si256 Compute the bitwise AND of 256 bits (representing integer data) in "a" and "b"
  • _mm_andnot_pd Compute the bitwise NOT of packed double-precision floating-point elements in "a" and then AND with "b"
  • _mm256_andnot_pd Compute the bitwise NOT of packed double-precision floating-point elements in "a" and then AND with "b"
  • _mm_andnot_ps Compute the bitwise NOT of packed single-precision floating-point elements in "a" and then AND with "b"
  • _mm256_andnot_ps Compute the bitwise NOT of packed single-precision floating-point elements in "a" and then AND with "b"
  • _mm_andnot_si64 Compute the bitwise NOT of 64 bits (representing integer data) in "a" and then AND with "b"
  • _mm_andnot_si128 Compute the bitwise NOT of 128 bits (representing integer data) in "a" and then AND with "b"
  • _mm256_andnot_si256 Compute the bitwise NOT of 256 bits (representing integer data) in "a" and then AND with "b"

O

  • _mm_or_pd Compute the bitwise OR of packed double-precision floating-point elements in "a" and "b"
  • _mm256_or_pd Compute the bitwise OR of packed double-precision floating-point elements in "a" and "b"
  • _mm_or_ps Compute the bitwise OR of packed single-precision floating-point elements in "a" and "b"
  • _mm256_or_ps Compute the bitwise OR of packed single-precision floating-point elements in "a" and "b"
  • _mm_or_si64 Compute the bitwise OR of 64 bits (representing integer data) in "a" and "b"
  • _mm_or_si128 Compute the bitwise OR of 128 bits (representing integer data) in "a" and "b"
  • _mm256_or_si256 Compute the bitwise OR of 256 bits (representing integer data) in "a" and "b"

P

  • _m_pand Compute the bitwise AND of 64 bits (representing integer data) in "a" and "b"
  • _m_pandn Compute the bitwise NOT of 64 bits (representing integer data) in "a" and then AND with "b"
  • _m_por Compute the bitwise OR of 64 bits (representing integer data) in "a" and "b"
  • _m_pxor Compute the bitwise OR of 64 bits (representing integer data) in "a" and "b"

T

  • _mm_test_all_ones Compute the bitwise NOT of "a" and then AND with a 128-bit vector containing all 1's
  • _mm_test_all_zeros Compute the bitwise AND of 128 bits (representing integer data) in "a" and "mask"
  • _mm_test_mix_ones_zeros Compute the bitwise AND of 128 bits (representing integer data) in "a" and "mask", and set "ZF" to 1 if the result is zero, otherwise set "ZF" to 0
  • _mm256_testc_pd Compute the bitwise AND of 256 bits (representing double-precision floating-point elements) in "a" and "b", producing an intermediate 256-bit value, and set "ZF" to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set "ZF" to 0
  • _mm_testc_pd Compute the bitwise AND of 128 bits (representing double-precision floating-point elements) in "a" and "b", producing an intermediate 128-bit value, and set "ZF" to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set "ZF" to 0
  • _mm256_testc_ps Compute the bitwise AND of 256 bits (representing single-precision floating-point elements) in "a" and "b", producing an intermediate 256-bit value, and set "ZF" to 1 if the sign bit of each 32-bit element in the intermediate value is zero, otherwise set "ZF" to 0
  • _mm_testc_ps Compute the bitwise AND of 128 bits (representing single-precision floating-point elements) in "a" and "b", producing an intermediate 128-bit value, and set "ZF" to 1 if the sign bit of each 32-bit element in the intermediate value is zero, otherwise set "ZF" to 0
  • _mm_testc_si128 Compute the bitwise AND of 128 bits (representing integer data) in "a" and "b", and set "ZF" to 1 if the result is zero, otherwise set "ZF" to 0
  • _mm256_testc_si256 Compute the bitwise AND of 256 bits (representing integer data) in "a" and "b", and set "ZF" to 1 if the result is zero, otherwise set "ZF" to 0
  • _mm256_testnzc_pd Compute the bitwise AND of 256 bits (representing double-precision floating-point elements) in "a" and "b", producing an intermediate 256-bit value, and set "ZF" to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set "ZF" to 0
  • _mm_testnzc_pd Compute the bitwise AND of 128 bits (representing double-precision floating-point elements) in "a" and "b", producing an intermediate 128-bit value, and set "ZF" to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set "ZF" to 0
  • _mm256_testnzc_ps Compute the bitwise AND of 256 bits (representing single-precision floating-point elements) in "a" and "b", producing an intermediate 256-bit value, and set "ZF" to 1 if the sign bit of each 32-bit element in the intermediate value is zero, otherwise set "ZF" to 0
  • _mm_testnzc_ps Compute the bitwise AND of 128 bits (representing single-precision floating-point elements) in "a" and "b", producing an intermediate 128-bit value, and set "ZF" to 1 if the sign bit of each 32-bit element in the intermediate value is zero, otherwise set "ZF" to 0
  • _mm_testnzc_si128 Compute the bitwise AND of 128 bits (representing integer data) in "a" and "b", and set "ZF" to 1 if the result is zero, otherwise set "ZF" to 0
  • _mm256_testnzc_si256 Compute the bitwise AND of 256 bits (representing integer data) in "a" and "b", and set "ZF" to 1 if the result is zero, otherwise set "ZF" to 0
  • _mm256_testz_pd Compute the bitwise AND of 256 bits (representing double-precision floating-point elements) in "a" and "b", producing an intermediate 256-bit value, and set "ZF" to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set "ZF" to 0
  • _mm_testz_pd Compute the bitwise AND of 128 bits (representing double-precision floating-point elements) in "a" and "b", producing an intermediate 128-bit value, and set "ZF" to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set "ZF" to 0
  • _mm256_testz_ps Compute the bitwise AND of 256 bits (representing single-precision floating-point elements) in "a" and "b", producing an intermediate 256-bit value, and set "ZF" to 1 if the sign bit of each 32-bit element in the intermediate value is zero, otherwise set "ZF" to 0
  • _mm_testz_ps Compute the bitwise AND of 128 bits (representing single-precision floating-point elements) in "a" and "b", producing an intermediate 128-bit value, and set "ZF" to 1 if the sign bit of each 32-bit element in the intermediate value is zero, otherwise set "ZF" to 0
  • _mm_testz_si128 Compute the bitwise AND of 128 bits (representing integer data) in "a" and "b", and set "ZF" to 1 if the result is zero, otherwise set "ZF" to 0
  • _mm256_testz_si256 Compute the bitwise AND of 256 bits (representing integer data) in "a" and "b", and set "ZF" to 1 if the result is zero, otherwise set "ZF" to 0

X

  • _mm_xor_pd Compute the bitwise XOR of packed double-precision floating-point elements in "a" and "b"
  • _mm256_xor_pd Compute the bitwise XOR of packed double-precision floating-point elements in "a" and "b"
  • _mm_xor_ps Compute the bitwise XOR of packed single-precision floating-point elements in "a" and "b"
  • _mm256_xor_ps Compute the bitwise XOR of packed single-precision floating-point elements in "a" and "b"
  • _mm_xor_si64 Compute the bitwise XOR of 64 bits (representing integer data) in "a" and "b"
  • _mm_xor_si128 Compute the bitwise XOR of 128 bits (representing integer data) in "a" and "b"
  • _mm256_xor_si256 Compute the bitwise XOR of 256 bits (representing integer data) in "a" and "b"


Miscellaneous

A B C E G I M P R S T U W

A

  • _mm_alignr_epi8 Concatenate 16-byte blocks in "a" and "b" into a 32-byte temporary result, shift the result right by "count" bytes, and store the low 16 bytes in "dst"
  • _mm256_alignr_epi8 Concatenate pairs of 16-byte blocks in "a" and "b" into a 32-byte temporary result, shift the result right by "count" bytes, and store the low 16 bytes in "dst"
  • _mm_alignr_pi8 Concatenate 8-byte blocks in "a" and "b" into a 16-byte temporary result, shift the result right by "count" bytes, and store the low 16 bytes in "dst"

B

  • _bnd_chk_ptr_bounds Checks if ["q", "q" + "size" - 1] is within the lower and upper bounds of "q" and throws a #BR if not
  • _bnd_chk_ptr_lbounds Checks if "q" is within its lower bound, and throws a #BR if not.
  • _bnd_chk_ptr_ubounds Checks if "q" is within its upper bound, and throws a #BR if not.
  • _bnd_copy_ptr_bounds Make a pointer with the value of "q" and bounds set to the bounds of "r" (e
  • _bnd_get_ptr_lbound Return the lower bound of "q".
  • _bnd_get_ptr_ubound Return the upper bound of "q".
  • _bnd_init_ptr_bounds Make a pointer with the value of "q" and open bounds, which allow the pointer to access the entire virtual address space
  • _bnd_narrow_ptr_bounds Narrow the bounds for pointer "q" to the intersection of the bounds of "r" and the bounds ["q", "q" + "size" - 1]
  • _bnd_set_ptr_bounds Make a pointer with the value of "srcmem" and bounds set to ["srcmem", "srcmem" + "size" - 1]
  • _bnd_store_ptr_bounds Stores the bounds of "ptr_val" pointer in memory at address "ptr_addr"

C

  • _mm_cldemote Hint to hardware that the cache line that contains "p" should be demoted from the cache closest to the processor core to a level more distant from the processor core
  • _clrssbsy Mark shadow stack pointed to by "p" as not busy.

E

  • _encls_u32 Invoke the Intel SGX enclave system (privileged) leaf function specified by "a"
  • _enclu_u32 Invoke the Intel SGX enclave user (non-privilege) leaf function specified by "a"
  • _enclv_u32 Invoke the Intel SGX enclave virtualized (VMM) leaf function specified by "a"

G

  • _get_ssp If CET is enabled, read the low 32-bits of the current shadow stack pointer

I

  • _inc_ssp Increment the shadow stack pointer by 4 times the value specified in bits [7:0] of "a"
  • _incsspd Increment the shadow stack pointer by 4 times the value specified in bits [7:0] of "a"
  • _incsspq Increment the shadow stack pointer by 8 times the value specified in bits [7:0] of "a"

M

  • _mm_minpos_epu16 Horizontally compute the minimum amongst the packed unsigned 16-bit integers in "a", store the minimum and index in "dst", and zero the remaining bits in "dst"
  • _mm_movemask_epi8 Create mask from the most significant bit of each 8-bit element in "a"
  • _mm256_movemask_epi8 Create mask from the most significant bit of each 8-bit element in "a"
  • _mm_movemask_pd Set each bit of mask "dst" based on the most significant bit of the corresponding packed double-precision floating-point element in "a"
  • _mm256_movemask_pd Set each bit of mask "dst" based on the most significant bit of the corresponding packed double-precision floating-point element in "a"
  • _mm_movemask_pi8 Create mask from the most significant bit of each 8-bit element in "a"
  • _mm_movemask_ps Set each bit of mask "dst" based on the most significant bit of the corresponding packed single-precision floating-point element in "a"
  • _mm256_movemask_ps Set each bit of mask "dst" based on the most significant bit of the corresponding packed single-precision floating-point element in "a"
  • _mm_movepi64_pi64 Copy the lower 64-bit integer in "a" to "dst".
  • _mm256_mpsadbw_epu8 Compute the sum of absolute differences (SADs) of quadruplets of unsigned 8-bit integers in "a" compared to those in "b", and store the 16-bit results in "dst"

P

  • _mm_packs_epi16 Convert packed 16-bit integers from "a" and "b" to packed 8-bit integers using signed saturation
  • _mm256_packs_epi16 Convert packed 16-bit integers from "a" and "b" to packed 8-bit integers using signed saturation
  • _mm_packs_epi32 Convert packed 32-bit integers from "a" and "b" to packed 16-bit integers using signed saturation
  • _mm256_packs_epi32 Convert packed 32-bit integers from "a" and "b" to packed 16-bit integers using signed saturation
  • _mm_packs_pi16 Convert packed 16-bit integers from "a" and "b" to packed 8-bit integers using signed saturation
  • _mm_packs_pi32 Convert packed 32-bit integers from "a" and "b" to packed 16-bit integers using signed saturation
  • _mm_packs_pu16 Convert packed 16-bit integers from "a" and "b" to packed 8-bit integers using unsigned saturation
  • _m_packssdw Convert packed 32-bit integers from "a" and "b" to packed 16-bit integers using signed saturation
  • _m_packsswb Convert packed 16-bit integers from "a" and "b" to packed 8-bit integers using signed saturation
  • _mm_packus_epi16 Convert packed 16-bit integers from "a" and "b" to packed 8-bit integers using unsigned saturation
  • _mm256_packus_epi16 Convert packed 16-bit integers from "a" and "b" to packed 8-bit integers using unsigned saturation
  • _mm256_packus_epi32 Convert packed 32-bit integers from "a" and "b" to packed 16-bit integers using unsigned saturation
  • _m_packuswb Convert packed 16-bit integers from "a" and "b" to packed 8-bit integers using unsigned saturation
  • _pconfig_u32 Invoke the PCONFIG leaf function specified by "a". The "__data" array contains 3 32-bit elements that may act as input, output, or be unused, depending on the semantics of the specified leaf function
  • _m_pmovmskb Create mask from the most significant bit of each 8-bit element in "a"
  • _ptwrite32 Insert the 32-bit data from "a" into a Processor Trace stream via a PTW packet
  • _ptwrite64 Insert the 64-bit data from "a" into a Processor Trace stream via a PTW packet

R

  • _rdsspd_i32 Read the low 32-bits of the current shadow stack pointer, and store the result in "dst"
  • _rdsspq_i64 Read the current shadow stack pointer, and store the result in "dst"
  • _rstorssp Restore the saved shadow stack pointer from the shadow stack restore token previously created on shadow stack by saveprevssp

S

  • _saveprevssp Save the previous shadow stack pointer context.
  • _setssbsy Mark shadow stack pointed to by IA32_PL0_SSP as busy.

T

  • _tpause Directs the processor to enter an implementation-dependent optimized state until the TSC reaches or exceeds the value specified in "counter"
  • _mm_trunc_pd Truncate the packed double-precision floating-point elements in "a"
  • _mm256_trunc_pd Truncate the packed double-precision floating-point elements in "a"
  • _mm_trunc_ps Truncate the packed single-precision floating-point elements in "a"
  • _mm256_trunc_ps Truncate the packed single-precision floating-point elements in "a"

U

  • _umonitor Sets up a linear address range to be monitored by hardware and activates the monitor
  • _umwait Directs the processor to enter an implementation-dependent optimized state while monitoring a range of addresses

W

  • _wbinvd Write back and flush internal caches. Initiate writing-back and flushing of external caches.
  • _wbnoinvd Write back and do not flush internal caches. Initiate writing-back without flushing of external caches.
  • _wrssd Write 32-bit value in "val" to a shadow stack page in memory specified by "p"
  • _wrssq Write 64-bit value in "val" to a shadow stack page in memory specified by "p"
  • _wrussd Write 32-bit value in "val" to a user shadow stack page in memory specified by "p"
  • _wrussq Write 64-bit value in "val" to a user shadow stack page in memory specified by "p"


Move

E P

E

  • _mm_move_epi64 Copy the lower 64-bit integer in "a" to the lower element of "dst", and zero the upper element
  • _mm_move_sd Move the lower double-precision floating-point element from "b" to the lower element of "dst", and copy the upper element from "a" to the upper element of "dst"
  • _mm_move_ss Move the lower single-precision floating-point element from "b" to the lower element of "dst", and copy the upper 3 elements from "a" to the upper elements of "dst"
  • _mm_movedup_pd Duplicate the low double-precision floating-point element from "a"
  • _mm256_movedup_pd Duplicate even-indexed double-precision floating-point elements from "a"
  • _mm_movehdup_ps Duplicate odd-indexed single-precision floating-point elements from "a"
  • _mm256_movehdup_ps Duplicate odd-indexed single-precision floating-point elements from "a"
  • _mm_movehl_ps Move the upper 2 single-precision floating-point elements from "b" to the lower 2 elements of "dst", and copy the upper 2 elements from "a" to the upper 2 elements of "dst"
  • _mm_moveldup_ps Duplicate even-indexed single-precision floating-point elements from "a"
  • _mm256_moveldup_ps Duplicate even-indexed single-precision floating-point elements from "a"
  • _mm_movelh_ps Move the lower 2 single-precision floating-point elements from "b" to the upper 2 elements of "dst", and copy the lower 2 elements from "a" to the lower 2 elements of "dst"

P

  • _mm_movpi64_epi64 Copy the 64-bit integer "a" to the lower element of "dst", and zero the upper element


OS-Targeted

F I X

F

  • _fxrstor Reload the x87 FPU, MMX technology, XMM, and MXCSR registers from the 512-byte memory image at "mem_addr"
  • _fxrstor64 Reload the x87 FPU, MMX technology, XMM, and MXCSR registers from the 512-byte memory image at "mem_addr"
  • _fxsave Save the current state of the x87 FPU, MMX technology, XMM, and MXCSR registers to a 512-byte memory location at "mem_addr"
  • _fxsave64 Save the current state of the x87 FPU, MMX technology, XMM, and MXCSR registers to a 512-byte memory location at "mem_addr"

I

  • _invpcid Invalidate mappings in the Translation Lookaside Buffers (TLBs) and paging-structure caches for the processor context identifier (PCID) specified by "descriptor" based on the invalidation type specified in "type"

X

  • _xgetbv Copy up to 64-bits from the value of the extended control register (XCR) specified by "a" into "dst"
  • _xrstor Perform a full or partial restore of the enabled processor states using the state information stored in memory at "mem_addr"
  • _xrstor64 Perform a full or partial restore of the enabled processor states using the state information stored in memory at "mem_addr"
  • _xrstors Perform a full or partial restore of the enabled processor states using the state information stored in memory at "mem_addr"
  • _xrstors64 Perform a full or partial restore of the enabled processor states using the state information stored in memory at "mem_addr"
  • _xsave Perform a full or partial save of the enabled processor states to memory at "mem_addr"
  • _xsave64 Perform a full or partial save of the enabled processor states to memory at "mem_addr"
  • _xsavec Perform a full or partial save of the enabled processor states to memory at "mem_addr"
  • _xsavec64 Perform a full or partial save of the enabled processor states to memory at "mem_addr"
  • _xsaveopt Perform a full or partial save of the enabled processor states to memory at "mem_addr"
  • _xsaveopt64 Perform a full or partial save of the enabled processor states to memory at "mem_addr"
  • _xsaves Perform a full or partial save of the enabled processor states to memory at "mem_addr"
  • _xsaves64 Perform a full or partial save of the enabled processor states to memory at "mem_addr"
  • _xsetbv Copy 64-bits from "val" to the extended control register (XCR) specified by "a"


Probability/Statistics

A C E P

A

  • _mm_avg_epu8 Average packed unsigned 8-bit integers in "a" and "b", and store the results in "dst"
  • _mm256_avg_epu8 Average packed unsigned 8-bit integers in "a" and "b", and store the results in "dst"
  • _mm_avg_epu16 Average packed unsigned 16-bit integers in "a" and "b", and store the results in "dst"
  • _mm256_avg_epu16 Average packed unsigned 16-bit integers in "a" and "b", and store the results in "dst"
  • _mm_avg_pu8 Average packed unsigned 8-bit integers in "a" and "b", and store the results in "dst"
  • _mm_avg_pu16 Average packed unsigned 16-bit integers in "a" and "b", and store the results in "dst"

C

  • _mm_cdfnorm_pd Compute the cumulative distribution function of packed double-precision floating-point elements in "a" using the normal distribution
  • _mm256_cdfnorm_pd Compute the cumulative distribution function of packed double-precision floating-point elements in "a" using the normal distribution
  • _mm_cdfnorm_ps Compute the cumulative distribution function of packed single-precision floating-point elements in "a" using the normal distribution
  • _mm256_cdfnorm_ps Compute the cumulative distribution function of packed single-precision floating-point elements in "a" using the normal distribution
  • _mm_cdfnorminv_pd Compute the inverse cumulative distribution function of packed double-precision floating-point elements in "a" using the normal distribution
  • _mm256_cdfnorminv_pd Compute the inverse cumulative distribution function of packed double-precision floating-point elements in "a" using the normal distribution
  • _mm_cdfnorminv_ps Compute the inverse cumulative distribution function of packed single-precision floating-point elements in "a" using the normal distribution
  • _mm256_cdfnorminv_ps Compute the inverse cumulative distribution function of packed single-precision floating-point elements in "a" using the normal distribution

E

  • _mm256_erf_pd Compute the error function of packed double-precision floating-point elements in "a"
  • _mm_erf_ps Compute the error function of packed single-precision floating-point elements in "a"
  • _mm256_erf_ps Compute the error function of packed single-precision floating-point elements in "a"
  • _mm_erfc_pd Compute the complementary error function of packed double-precision floating-point elements in "a"
  • _mm256_erfc_pd Compute the complementary error function of packed double-precision floating-point elements in "a"
  • _mm_erfc_ps Compute the complementary error function of packed single-precision floating-point elements in "a"
  • _mm256_erfc_ps Compute the complementary error function of packed single-precision floating-point elements in "a"
  • _mm_erfcinv_pd Compute the inverse complementary error function of packed double-precision floating-point elements in "a"
  • _mm256_erfcinv_pd Compute the inverse complementary error function of packed double-precision floating-point elements in "a"
  • _mm_erfcinv_ps Compute the inverse complementary error function of packed single-precision floating-point elements in "a"
  • _mm256_erfcinv_ps Compute the inverse complementary error function of packed single-precision floating-point elements in "a"
  • _mm_erfinv_pd Compute the inverse error function of packed double-precision floating-point elements in "a"
  • _mm256_erfinv_pd Compute the inverse error function of packed double-precision floating-point elements in "a"
  • _mm_erfinv_ps Compute the inverse error function of packed single-precision floating-point elements in "a"
  • _mm256_erfinv_ps Compute the inverse error function of packed single-precision floating-point elements in "a"

P

  • _m_pavgb Average packed unsigned 8-bit integers in "a" and "b", and store the results in "dst"
  • _m_pavgw Average packed unsigned 16-bit integers in "a" and "b", and store the results in "dst"


Random

R S

R

  • _rdrand16_step Read a hardware generated 16-bit random value and store the result in "val"
  • _rdrand32_step Read a hardware generated 32-bit random value and store the result in "val"
  • _rdrand64_step Read a hardware generated 64-bit random value and store the result in "val"

S

  • _rdseed16_step Read a 16-bit NIST SP800-90B and SP800-90C compliant random value and store in "val"
  • _rdseed32_step Read a 32-bit NIST SP800-90B and SP800-90C compliant random value and store in "val"
  • _rdseed64_step Read a 64-bit NIST SP800-90B and SP800-90C compliant random value and store in "val"


Set

_ 1 R Z

_

  • _mm_set_epi8 Set packed 8-bit integers in "dst" with the supplied values in reverse order
  • _mm256_set_epi8 Set packed 8-bit integers in "dst" with the supplied values in reverse order
  • _mm_set_epi16 Set packed 16-bit integers in "dst" with the supplied values.
  • _mm256_set_epi16 Set packed 16-bit integers in "dst" with the supplied values.
  • _mm_set_epi32 Set packed 32-bit integers in "dst" with the supplied values.
  • _mm256_set_epi32 Set packed 32-bit integers in "dst" with the supplied values.
  • _mm_set_epi64 Set packed 64-bit integers in "dst" with the supplied values.
  • _mm_set_epi64x Set packed 64-bit integers in "dst" with the supplied values.
  • _mm256_set_epi64x Set packed 64-bit integers in "dst" with the supplied values.
  • _mm256_set_m128 Set packed __m256 vector "dst" with the supplied values.
  • _mm256_set_m128d Set packed __m256d vector "dst" with the supplied values.
  • _mm256_set_m128i Set packed __m256i vector "dst" with the supplied values.
  • _mm_set_pd Set packed double-precision floating-point elements in "dst" with the supplied values
  • _mm256_set_pd Set packed double-precision floating-point elements in "dst" with the supplied values
  • _mm_set_pd1 Broadcast double-precision floating-point value "a" to all elements of "dst"
  • _mm_set_pi8 Set packed 8-bit integers in "dst" with the supplied values in reverse order
  • _mm_set_pi16 Set packed 16-bit integers in "dst" with the supplied values.
  • _mm_set_pi32 Set packed 32-bit integers in "dst" with the supplied values.
  • _mm_set_ps Set packed single-precision floating-point elements in "dst" with the supplied values
  • _mm256_set_ps Set packed single-precision floating-point elements in "dst" with the supplied values
  • _mm_set_ps1 Broadcast single-precision floating-point value "a" to all elements of "dst"
  • _mm_set_sd Copy double-precision floating-point element "a" to the lower element of "dst", and zero the upper element
  • _mm_set_ss Copy single-precision floating-point element "a" to the lower element of "dst", and zero the upper 3 elements

1

  • _mm_set1_epi8 Broadcast 8-bit integer "a" to all elements of "dst". This intrinsic may generate "vpbroadcastb".
  • _mm256_set1_epi8 Broadcast 8-bit integer "a" to all elements of "dst". This intrinsic may generate the "vpbroadcastb".
  • _mm_set1_epi16 Broadcast 16-bit integer "a" to all all elements of "dst". This intrinsic may generate "vpbroadcastw".
  • _mm256_set1_epi16 Broadcast 16-bit integer "a" to all all elements of "dst". This intrinsic may generate the "vpbroadcastw".
  • _mm_set1_epi32 Broadcast 32-bit integer "a" to all elements of "dst". This intrinsic may generate "vpbroadcastd".
  • _mm256_set1_epi32 Broadcast 32-bit integer "a" to all elements of "dst". This intrinsic may generate the "vpbroadcastd".
  • _mm_set1_epi64 Broadcast 64-bit integer "a" to all elements of "dst".
  • _mm_set1_epi64x Broadcast 64-bit integer "a" to all elements of "dst". This intrinsic may generate the "vpbroadcastq".
  • _mm256_set1_epi64x Broadcast 64-bit integer "a" to all elements of "dst". This intrinsic may generate the "vpbroadcastq".
  • _mm_set1_pd Broadcast double-precision floating-point value "a" to all elements of "dst"
  • _mm256_set1_pd Broadcast double-precision floating-point value "a" to all elements of "dst"
  • _mm_set1_pi8 Broadcast 8-bit integer "a" to all elements of "dst".
  • _mm_set1_pi16 Broadcast 16-bit integer "a" to all all elements of "dst".
  • _mm_set1_pi32 Broadcast 32-bit integer "a" to all elements of "dst".
  • _mm_set1_ps Broadcast single-precision floating-point value "a" to all elements of "dst"
  • _mm256_set1_ps Broadcast single-precision floating-point value "a" to all elements of "dst"

R

  • _mm_setr_epi8 Set packed 8-bit integers in "dst" with the supplied values in reverse order
  • _mm256_setr_epi8 Set packed 8-bit integers in "dst" with the supplied values in reverse order
  • _mm_setr_epi16 Set packed 16-bit integers in "dst" with the supplied values in reverse order
  • _mm256_setr_epi16 Set packed 16-bit integers in "dst" with the supplied values in reverse order
  • _mm_setr_epi32 Set packed 32-bit integers in "dst" with the supplied values in reverse order
  • _mm256_setr_epi32 Set packed 32-bit integers in "dst" with the supplied values in reverse order
  • _mm_setr_epi64 Set packed 64-bit integers in "dst" with the supplied values in reverse order
  • _mm256_setr_epi64x Set packed 64-bit integers in "dst" with the supplied values in reverse order
  • _mm256_setr_m128 Set packed __m256 vector "dst" with the supplied values.
  • _mm256_setr_m128d Set packed __m256d vector "dst" with the supplied values.
  • _mm256_setr_m128i Set packed __m256i vector "dst" with the supplied values.
  • _mm_setr_pd Set packed double-precision floating-point elements in "dst" with the supplied values in reverse order
  • _mm256_setr_pd Set packed double-precision floating-point elements in "dst" with the supplied values in reverse order
  • _mm_setr_pi8 Set packed 8-bit integers in "dst" with the supplied values in reverse order
  • _mm_setr_pi16 Set packed 16-bit integers in "dst" with the supplied values in reverse order
  • _mm_setr_pi32 Set packed 32-bit integers in "dst" with the supplied values in reverse order
  • _mm_setr_ps Set packed single-precision floating-point elements in "dst" with the supplied values in reverse order
  • _mm256_setr_ps Set packed single-precision floating-point elements in "dst" with the supplied values in reverse order

Z

  • _mm_setzero_pd Return vector of type __m128d with all elements set to zero.
  • _mm256_setzero_pd Return vector of type __m256d with all elements set to zero.
  • _mm_setzero_ps Return vector of type __m128 with all elements set to zero.
  • _mm256_setzero_ps Return vector of type __m256 with all elements set to zero.
  • _mm_setzero_si64 Return vector of type __m64 with all elements set to zero.
  • _mm_setzero_si128 Return vector of type __m128i with all elements set to zero.
  • _mm256_setzero_si256 Return vector of type __m256i with all elements set to zero.


Shift

B L P R S

B

  • _mm256_bslli_epi128 Shift 128-bit lanes in "a" left by "imm8" bytes while shifting in zeros
  • _mm_bslli_si128 Shift "a" left by "imm8" bytes while shifting in zeros, and store the results in "dst"
  • _mm256_bsrli_epi128 Shift 128-bit lanes in "a" right by "imm8" bytes while shifting in zeros
  • _mm_bsrli_si128 Shift "a" right by "imm8" bytes while shifting in zeros, and store the results in "dst"

L

  • _lrotl Shift the bits of unsigned long integer "a" left by the number of bits specified in "shift"
  • _lrotr Shift the bits of unsigned long integer "a" right by the number of bits specified in "shift"

P

  • _m_pslld Shift packed 32-bit integers in "a" left by "count" while shifting in zeros
  • _m_pslldi Shift packed 32-bit integers in "a" left by "imm8" while shifting in zeros
  • _m_psllq Shift 64-bit integer "a" left by "count" while shifting in zeros, and store the result in "dst"
  • _m_psllqi Shift 64-bit integer "a" left by "imm8" while shifting in zeros, and store the result in "dst"
  • _m_psllw Shift packed 16-bit integers in "a" left by "count" while shifting in zeros
  • _m_psllwi Shift packed 16-bit integers in "a" left by "imm8" while shifting in zeros
  • _m_psrad Shift packed 32-bit integers in "a" right by "count" while shifting in sign bits
  • _m_psradi Shift packed 32-bit integers in "a" right by "imm8" while shifting in sign bits
  • _m_psraw Shift packed 16-bit integers in "a" right by "count" while shifting in sign bits
  • _m_psrawi Shift packed 16-bit integers in "a" right by "imm8" while shifting in sign bits
  • _m_psrld Shift packed 32-bit integers in "a" right by "count" while shifting in zeros
  • _m_psrldi Shift packed 32-bit integers in "a" right by "imm8" while shifting in zeros
  • _m_psrlq Shift 64-bit integer "a" right by "count" while shifting in zeros
  • _m_psrlqi Shift 64-bit integer "a" right by "imm8" while shifting in zeros, and store the result in "dst"
  • _m_psrlw Shift packed 16-bit integers in "a" right by "count" while shifting in zeros
  • _m_psrlwi Shift packed 16-bit integers in "a" right by "imm8" while shifting in zeros

R

  • _rotl Shift the bits of unsigned 32-bit integer "a" left by the number of bits specified in "shift"
  • _rotl64 Shift the bits of unsigned 64-bit integer "a" left by the number of bits specified in "shift"
  • _rotr Shift the bits of unsigned 32-bit integer "a" right by the number of bits specified in "shift"
  • _rotr64 Shift the bits of unsigned 64-bit integer "a" right by the number of bits specified in "shift"
  • _rotwl Shift the bits of unsigned 16-bit integer "a" left by the number of bits specified in "shift"
  • _rotwr Shift the bits of unsigned 16-bit integer "a" right by the number of bits specified in "shift"

S

  • _mm_sll_epi16 Shift packed 16-bit integers in "a" left by "count" while shifting in zeros
  • _mm256_sll_epi16 Shift packed 16-bit integers in "a" left by "count" while shifting in zeros
  • _mm_sll_epi32 Shift packed 32-bit integers in "a" left by "count" while shifting in zeros
  • _mm256_sll_epi32 Shift packed 32-bit integers in "a" left by "count" while shifting in zeros
  • _mm_sll_epi64 Shift packed 64-bit integers in "a" left by "count" while shifting in zeros
  • _mm256_sll_epi64 Shift packed 64-bit integers in "a" left by "count" while shifting in zeros
  • _mm_sll_pi16 Shift packed 16-bit integers in "a" left by "count" while shifting in zeros
  • _mm_sll_pi32 Shift packed 32-bit integers in "a" left by "count" while shifting in zeros
  • _mm_sll_si64 Shift 64-bit integer "a" left by "count" while shifting in zeros, and store the result in "dst"
  • _mm_slli_epi16 Shift packed 16-bit integers in "a" left by "imm8" while shifting in zeros
  • _mm256_slli_epi16 Shift packed 16-bit integers in "a" left by "imm8" while shifting in zeros
  • _mm_slli_epi32 Shift packed 32-bit integers in "a" left by "imm8" while shifting in zeros
  • _mm256_slli_epi32 Shift packed 32-bit integers in "a" left by "imm8" while shifting in zeros
  • _mm_slli_epi64 Shift packed 64-bit integers in "a" left by "imm8" while shifting in zeros
  • _mm256_slli_epi64 Shift packed 64-bit integers in "a" left by "imm8" while shifting in zeros
  • _mm_slli_pi16 Shift packed 16-bit integers in "a" left by "imm8" while shifting in zeros
  • _mm_slli_pi32 Shift packed 32-bit integers in "a" left by "imm8" while shifting in zeros
  • _mm_slli_si64 Shift 64-bit integer "a" left by "imm8" while shifting in zeros, and store the result in "dst"
  • _mm_slli_si128 Shift "a" left by "imm8" bytes while shifting in zeros, and store the results in "dst"
  • _mm256_slli_si256 Shift 128-bit lanes in "a" left by "imm8" bytes while shifting in zeros
  • _mm_sllv_epi32 Shift packed 32-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros
  • _mm256_sllv_epi32 Shift packed 32-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros
  • _mm_sllv_epi64 Shift packed 64-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros
  • _mm256_sllv_epi64 Shift packed 64-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros
  • _mm_sra_epi16 Shift packed 16-bit integers in "a" right by "count" while shifting in sign bits
  • _mm256_sra_epi16 Shift packed 16-bit integers in "a" right by "count" while shifting in sign bits
  • _mm_sra_epi32 Shift packed 32-bit integers in "a" right by "count" while shifting in sign bits
  • _mm256_sra_epi32 Shift packed 32-bit integers in "a" right by "count" while shifting in sign bits
  • _mm_sra_pi16 Shift packed 16-bit integers in "a" right by "count" while shifting in sign bits
  • _mm_sra_pi32 Shift packed 32-bit integers in "a" right by "count" while shifting in sign bits
  • _mm_srai_epi16 Shift packed 16-bit integers in "a" right by "imm8" while shifting in sign bits
  • _mm256_srai_epi16 Shift packed 16-bit integers in "a" right by "imm8" while shifting in sign bits
  • _mm_srai_epi32 Shift packed 32-bit integers in "a" right by "imm8" while shifting in sign bits
  • _mm256_srai_epi32 Shift packed 32-bit integers in "a" right by "imm8" while shifting in sign bits
  • _mm_srai_pi16 Shift packed 16-bit integers in "a" right by "imm8" while shifting in sign bits
  • _mm_srai_pi32 Shift packed 32-bit integers in "a" right by "imm8" while shifting in sign bits
  • _mm_srav_epi32 Shift packed 32-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits
  • _mm256_srav_epi32 Shift packed 32-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits
  • _mm_srl_epi16 Shift packed 16-bit integers in "a" right by "count" while shifting in zeros
  • _mm256_srl_epi16 Shift packed 16-bit integers in "a" right by "count" while shifting in zeros
  • _mm_srl_epi32 Shift packed 32-bit integers in "a" right by "count" while shifting in zeros
  • _mm256_srl_epi32 Shift packed 32-bit integers in "a" right by "count" while shifting in zeros
  • _mm_srl_epi64 Shift packed 64-bit integers in "a" right by "count" while shifting in zeros
  • _mm256_srl_epi64 Shift packed 64-bit integers in "a" right by "count" while shifting in zeros
  • _mm_srl_pi16 Shift packed 16-bit integers in "a" right by "count" while shifting in zeros
  • _mm_srl_pi32 Shift packed 32-bit integers in "a" right by "count" while shifting in zeros
  • _mm_srl_si64 Shift 64-bit integer "a" right by "count" while shifting in zeros
  • _mm_srli_epi16 Shift packed 16-bit integers in "a" right by "imm8" while shifting in zeros
  • _mm256_srli_epi16 Shift packed 16-bit integers in "a" right by "imm8" while shifting in zeros
  • _mm_srli_epi32 Shift packed 32-bit integers in "a" right by "imm8" while shifting in zeros
  • _mm256_srli_epi32 Shift packed 32-bit integers in "a" right by "imm8" while shifting in zeros
  • _mm_srli_epi64 Shift packed 64-bit integers in "a" right by "imm8" while shifting in zeros
  • _mm256_srli_epi64 Shift packed 64-bit integers in "a" right by "imm8" while shifting in zeros
  • _mm_srli_pi16 Shift packed 16-bit integers in "a" right by "imm8" while shifting in zeros
  • _mm_srli_pi32 Shift packed 32-bit integers in "a" right by "imm8" while shifting in zeros
  • _mm_srli_si64 Shift 64-bit integer "a" right by "imm8" while shifting in zeros, and store the result in "dst"
  • _mm_srli_si128 Shift "a" right by "imm8" bytes while shifting in zeros, and store the results in "dst"
  • _mm256_srli_si256 Shift 128-bit lanes in "a" right by "imm8" bytes while shifting in zeros
  • _mm_srlv_epi32 Shift packed 32-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros
  • _mm256_srlv_epi32 Shift packed 32-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros
  • _mm_srlv_epi64 Shift packed 64-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros
  • _mm256_srlv_epi64 Shift packed 64-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros


Special Math Functions

A C F M P R S

A

  • _mm_abs_epi8 Compute the absolute value of packed 8-bit integers in "a", and store the unsigned results in "dst"
  • _mm256_abs_epi8 Compute the absolute value of packed 8-bit integers in "a", and store the unsigned results in "dst"
  • _mm_abs_epi16 Compute the absolute value of packed 16-bit integers in "a", and store the unsigned results in "dst"
  • _mm256_abs_epi16 Compute the absolute value of packed 16-bit integers in "a", and store the unsigned results in "dst"
  • _mm_abs_epi32 Compute the absolute value of packed 32-bit integers in "a", and store the unsigned results in "dst"
  • _mm256_abs_epi32 Compute the absolute value of packed 32-bit integers in "a", and store the unsigned results in "dst"
  • _mm_abs_pi8 Compute the absolute value of packed 8-bit integers in "a", and store the unsigned results in "dst"
  • _mm_abs_pi16 Compute the absolute value of packed 16-bit integers in "a", and store the unsigned results in "dst"
  • _mm_abs_pi32 Compute the absolute value of packed 32-bit integers in "a", and store the unsigned results in "dst"

C

  • _mm_ceil_pd Round the packed double-precision floating-point elements in "a" up to an integer value
  • _mm256_ceil_pd Round the packed double-precision floating-point elements in "a" up to an integer value
  • _mm_ceil_ps Round the packed single-precision floating-point elements in "a" up to an integer value
  • _mm256_ceil_ps Round the packed single-precision floating-point elements in "a" up to an integer value
  • _mm_ceil_sd Round the lower double-precision floating-point element in "b" up to an integer value
  • _mm_ceil_ss Round the lower single-precision floating-point element in "b" up to an integer value

F

  • _mm_floor_pd Round the packed double-precision floating-point elements in "a" down to an integer value
  • _mm256_floor_pd Round the packed double-precision floating-point elements in "a" down to an integer value
  • _mm_floor_ps Round the packed single-precision floating-point elements in "a" down to an integer value
  • _mm256_floor_ps Round the packed single-precision floating-point elements in "a" down to an integer value
  • _mm_floor_sd Round the lower double-precision floating-point element in "b" down to an integer value
  • _mm_floor_ss Round the lower single-precision floating-point element in "b" down to an integer value

M

  • _mm_max_epi8 Compare packed 8-bit integers in "a" and "b", and store packed maximum values in "dst"
  • _mm256_max_epi8 Compare packed 8-bit integers in "a" and "b", and store packed maximum values in "dst"
  • _mm_max_epi16 Compare packed 16-bit integers in "a" and "b", and store packed maximum values in "dst"
  • _mm256_max_epi16 Compare packed 16-bit integers in "a" and "b", and store packed maximum values in "dst"
  • _mm_max_epi32 Compare packed 32-bit integers in "a" and "b", and store packed maximum values in "dst"
  • _mm256_max_epi32 Compare packed 32-bit integers in "a" and "b", and store packed maximum values in "dst"
  • _mm_max_epu8 Compare packed unsigned 8-bit integers in "a" and "b", and store packed maximum values in "dst"
  • _mm256_max_epu8 Compare packed unsigned 8-bit integers in "a" and "b", and store packed maximum values in "dst"
  • _mm_max_epu16 Compare packed unsigned 16-bit integers in "a" and "b", and store packed maximum values in "dst"
  • _mm256_max_epu16 Compare packed unsigned 16-bit integers in "a" and "b", and store packed maximum values in "dst"
  • _mm_max_epu32 Compare packed unsigned 32-bit integers in "a" and "b", and store packed maximum values in "dst"
  • _mm256_max_epu32 Compare packed unsigned 32-bit integers in "a" and "b", and store packed maximum values in "dst"
  • _mm_max_pd Compare packed double-precision floating-point elements in "a" and "b", and store packed maximum values in "dst"
  • _mm256_max_pd Compare packed double-precision floating-point elements in "a" and "b", and store packed maximum values in "dst"
  • _mm_max_pi16 Compare packed 16-bit integers in "a" and "b", and store packed maximum values in "dst"
  • _mm_max_ps Compare packed single-precision floating-point elements in "a" and "b", and store packed maximum values in "dst"
  • _mm256_max_ps Compare packed single-precision floating-point elements in "a" and "b", and store packed maximum values in "dst"
  • _mm_max_pu8 Compare packed unsigned 8-bit integers in "a" and "b", and store packed maximum values in "dst"
  • _mm_max_sd Compare the lower double-precision floating-point elements in "a" and "b", store the maximum value in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst"
  • _mm_max_ss Compare the lower single-precision floating-point elements in "a" and "b", store the maximum value in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst"
  • _mm_min_epi8 Compare packed 8-bit integers in "a" and "b", and store packed minimum values in "dst"
  • _mm256_min_epi8 Compare packed 8-bit integers in "a" and "b", and store packed minimum values in "dst"
  • _mm_min_epi16 Compare packed 16-bit integers in "a" and "b", and store packed minimum values in "dst"
  • _mm256_min_epi16 Compare packed 16-bit integers in "a" and "b", and store packed minimum values in "dst"
  • _mm_min_epi32 Compare packed 32-bit integers in "a" and "b", and store packed minimum values in "dst"
  • _mm256_min_epi32 Compare packed 32-bit integers in "a" and "b", and store packed minimum values in "dst"
  • _mm_min_epu8 Compare packed unsigned 8-bit integers in "a" and "b", and store packed minimum values in "dst"
  • _mm256_min_epu8 Compare packed unsigned 8-bit integers in "a" and "b", and store packed minimum values in "dst"
  • _mm_min_epu16 Compare packed unsigned 16-bit integers in "a" and "b", and store packed minimum values in "dst"
  • _mm256_min_epu16 Compare packed unsigned 16-bit integers in "a" and "b", and store packed minimum values in "dst"
  • _mm_min_epu32 Compare packed unsigned 32-bit integers in "a" and "b", and store packed minimum values in "dst"
  • _mm256_min_epu32 Compare packed unsigned 32-bit integers in "a" and "b", and store packed minimum values in "dst"
  • _mm_min_pd Compare packed double-precision floating-point elements in "a" and "b", and store packed minimum values in "dst"
  • _mm256_min_pd Compare packed double-precision floating-point elements in "a" and "b", and store packed minimum values in "dst"
  • _mm_min_pi16 Compare packed 16-bit integers in "a" and "b", and store packed minimum values in "dst"
  • _mm_min_ps Compare packed single-precision floating-point elements in "a" and "b", and store packed minimum values in "dst"
  • _mm256_min_ps Compare packed single-precision floating-point elements in "a" and "b", and store packed minimum values in "dst"
  • _mm_min_pu8 Compare packed unsigned 8-bit integers in "a" and "b", and store packed minimum values in "dst"
  • _mm_min_sd Compare the lower double-precision floating-point elements in "a" and "b", store the minimum value in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst"
  • _mm_min_ss Compare the lower single-precision floating-point elements in "a" and "b", store the minimum value in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst"

P

  • _m_pmaxsw Compare packed 16-bit integers in "a" and "b", and store packed maximum values in "dst"
  • _m_pmaxub Compare packed unsigned 8-bit integers in "a" and "b", and store packed maximum values in "dst"
  • _m_pminsw Compare packed 16-bit integers in "a" and "b", and store packed minimum values in "dst"
  • _m_pminub Compare packed unsigned 8-bit integers in "a" and "b", and store packed minimum values in "dst"

R

  • _mm_round_pd Round the packed double-precision floating-point elements in "a" using the "rounding" parameter
  • _mm256_round_pd Round the packed double-precision floating-point elements in "a" using the "rounding" parameter
  • _mm_round_ps Round the packed single-precision floating-point elements in "a" using the "rounding" parameter
  • _mm256_round_ps Round the packed single-precision floating-point elements in "a" using the "rounding" parameter
  • _mm_round_sd Round the lower double-precision floating-point element in "b" using the "rounding" parameter
  • _mm_round_ss Round the lower single-precision floating-point element in "b" using the "rounding" parameter

S

  • _mm_svml_ceil_pd Round the packed double-precision floating-point elements in "a" up to an integer value
  • _mm256_svml_ceil_pd Round the packed double-precision floating-point elements in "a" up to an integer value
  • _mm_svml_ceil_ps Round the packed single-precision floating-point elements in "a" up to an integer value
  • _mm256_svml_ceil_ps Round the packed single-precision floating-point elements in "a" up to an integer value
  • _mm_svml_floor_pd Round the packed double-precision floating-point elements in "a" down to an integer value
  • _mm256_svml_floor_pd Round the packed double-precision floating-point elements in "a" down to an integer value
  • _mm_svml_floor_ps Round the packed single-precision floating-point elements in "a" down to an integer value
  • _mm256_svml_floor_ps Round the packed single-precision floating-point elements in "a" down to an integer value
  • _mm_svml_round_pd Round the packed double-precision floating-point elements in "a" to the nearest integer value
  • _mm256_svml_round_pd Round the packed double-precision floating-point elements in "a" to the nearest integer value
  • _mm_svml_round_ps Round the packed single-precision floating-point elements in "a" to the nearest integer value
  • _mm256_svml_round_ps Round the packed single-precision floating-point elements in "a" to the nearest integer value


Store

D M S

D

  • _directstoreu_u32 Store 32-bit integer from "val" into memory using direct store.
  • _directstoreu_u64 Store 64-bit integer from "val" into memory using direct store.

M

  • _mm_maskmove_si64 Conditionally store 8-bit integer elements from "a" into memory using "mask" (elements are not stored when the highest bit is not set in the corresponding element) and a non-temporal memory hint
  • _mm_maskmoveu_si128 Conditionally store 8-bit integer elements from "a" into memory using "mask" (elements are not stored when the highest bit is not set in the corresponding element) and a non-temporal memory hint
  • _m_maskmovq Conditionally store 8-bit integer elements from "a" into memory using "mask" (elements are not stored when the highest bit is not set in the corresponding element)
  • _mm_maskstore_epi32 Store packed 32-bit integers from "a" into memory using "mask" (elements are not stored when the highest bit is not set in the corresponding element)
  • _mm256_maskstore_epi32 Store packed 32-bit integers from "a" into memory using "mask" (elements are not stored when the highest bit is not set in the corresponding element)
  • _mm_maskstore_epi64 Store packed 64-bit integers from "a" into memory using "mask" (elements are not stored when the highest bit is not set in the corresponding element)
  • _mm256_maskstore_epi64 Store packed 64-bit integers from "a" into memory using "mask" (elements are not stored when the highest bit is not set in the corresponding element)
  • _mm256_maskstore_pd Store packed double-precision floating-point elements from "a" into memory using "mask"
  • _mm_maskstore_pd Store packed double-precision floating-point elements from "a" into memory using "mask"
  • _mm256_maskstore_ps Store packed single-precision floating-point elements from "a" into memory using "mask"
  • _mm_maskstore_ps Store packed single-precision floating-point elements from "a" into memory using "mask"
  • _movdir64b Move 64-byte (512-bit) value using direct store from source memory address "src" to destination memory address "dst"

S

  • _mm_store_pd Store 128-bits (composed of 2 packed double-precision floating-point elements) from "a" into memory
  • _mm256_store_pd Store 256-bits (composed of 4 packed double-precision floating-point elements) from "a" into memory
  • _mm_store_pd1 Store the lower double-precision floating-point element from "a" into 2 contiguous elements in memory
  • _mm_store_ps Store 128-bits (composed of 4 packed single-precision floating-point elements) from "a" into memory
  • _mm256_store_ps Store 256-bits (composed of 8 packed single-precision floating-point elements) from "a" into memory
  • _mm_store_ps1 Store the lower single-precision floating-point element from "a" into 4 contiguous elements in memory
  • _mm_store_sd Store the lower double-precision floating-point element from "a" into memory
  • _mm_store_si128 Store 128-bits of integer data from "a" into memory. "mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.
  • _mm256_store_si256 Store 256-bits of integer data from "a" into memory. "mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.
  • _mm_store_ss Store the lower single-precision floating-point element from "a" into memory
  • _mm_store1_pd Store the lower double-precision floating-point element from "a" into 2 contiguous elements in memory
  • _mm_store1_ps Store the lower single-precision floating-point element from "a" into 4 contiguous elements in memory
  • _storebe_i16 Perform a bit swap operation of the 16 bits in "data", and store the results to memory
  • _storebe_i32 Perform a bit swap operation of the 32 bits in "data", and store the results to memory
  • _storebe_i64 Perform a bit swap operation of the 64 bits in "data", and store the results to memory
  • _mm_storeh_pd Store the upper double-precision floating-point element from "a" into memory
  • _mm_storeh_pi Store the upper 2 single-precision floating-point elements from "a" into memory
  • _mm_storel_epi64 Store 64-bit integer from the first element of "a" into memory.
  • _mm_storel_pd Store the lower double-precision floating-point element from "a" into memory
  • _mm_storel_pi Store the lower 2 single-precision floating-point elements from "a" into memory
  • _mm_storer_pd Store 2 double-precision floating-point elements from "a" into memory in reverse order
  • _mm_storer_ps Store 4 single-precision floating-point elements from "a" into memory in reverse order
  • _mm_storeu_pd Store 128-bits (composed of 2 packed double-precision floating-point elements) from "a" into memory
  • _mm256_storeu_pd Store 256-bits (composed of 4 packed double-precision floating-point elements) from "a" into memory
  • _mm_storeu_ps Store 128-bits (composed of 4 packed single-precision floating-point elements) from "a" into memory
  • _mm256_storeu_ps Store 256-bits (composed of 8 packed single-precision floating-point elements) from "a" into memory
  • _mm_storeu_si16 Store 16-bit integer from the first element of "a" into memory. "mem_addr" does not need to be aligned on any particular boundary.
  • _mm_storeu_si32 Store 32-bit integer from the first element of "a" into memory. "mem_addr" does not need to be aligned on any particular boundary.
  • _mm_storeu_si64 Store 64-bit integer from the first element of "a" into memory. "mem_addr" does not need to be aligned on any particular boundary.
  • _mm_storeu_si128 Store 128-bits of integer data from "a" into memory. "mem_addr" does not need to be aligned on any particular boundary.
  • _mm256_storeu_si256 Store 256-bits of integer data from "a" into memory. "mem_addr" does not need to be aligned on any particular boundary.
  • _mm256_storeu2_m128 Store the high and low 128-bit halves (each composed of 4 packed single-precision floating-point elements) from "a" into memory two different 128-bit locations
  • _mm256_storeu2_m128d Store the high and low 128-bit halves (each composed of 2 packed double-precision floating-point elements) from "a" into memory two different 128-bit locations
  • _mm256_storeu2_m128i Store the high and low 128-bit halves (each composed of integer data) from "a" into memory two different 128-bit locations
  • _mm_stream_pd Store 128-bits (composed of 2 packed double-precision floating-point elements) from "a" into memory using a non-temporal memory hint
  • _mm256_stream_pd Store 256-bits (composed of 4 packed double-precision floating-point elements) from "a" into memory using a non-temporal memory hint
  • _mm_stream_pi Store 64-bits of integer data from "a" into memory using a non-temporal memory hint
  • _mm_stream_ps Store 128-bits (composed of 4 packed single-precision floating-point elements) from "a" into memory using a non-temporal memory hint
  • _mm256_stream_ps Store 256-bits (composed of 8 packed single-precision floating-point elements) from "a" into memory using a non-temporal memory hint
  • _mm_stream_si32 Store 32-bit integer "a" into memory using a non-temporal hint to minimize cache pollution
  • _mm_stream_si64 Store 64-bit integer "a" into memory using a non-temporal hint to minimize cache pollution
  • _mm_stream_si128 Store 128-bits of integer data from "a" into memory using a non-temporal memory hint
  • _mm256_stream_si256 Store 256-bits of integer data from "a" into memory using a non-temporal memory hint


String Compare

E I

E

  • _mm_cmpestra Compare packed strings in "a" and "b" with lengths "la" and "lb" using the control in "imm8"
  • _mm_cmpestrc Compare packed strings in "a" and "b" with lengths "la" and "lb" using the control in "imm8"
  • _mm_cmpestri Compare packed strings in "a" and "b" with lengths "la" and "lb" using the control in "imm8", and store the generated index in "dst"
  • _mm_cmpestrm Compare packed strings in "a" and "b" with lengths "la" and "lb" using the control in "imm8", and store the generated mask in "dst"
  • _mm_cmpestro Compare packed strings in "a" and "b" with lengths "la" and "lb" using the control in "imm8"
  • _mm_cmpestrs Compare packed strings in "a" and "b" with lengths "la" and "lb" using the control in "imm8"
  • _mm_cmpestrz Compare packed strings in "a" and "b" with lengths "la" and "lb" using the control in "imm8"

I

  • _mm_cmpistra Compare packed strings with implicit lengths in "a" and "b" using the control in "imm8"
  • _mm_cmpistrc Compare packed strings with implicit lengths in "a" and "b" using the control in "imm8"
  • _mm_cmpistri Compare packed strings with implicit lengths in "a" and "b" using the control in "imm8", and store the generated index in "dst"
  • _mm_cmpistrm Compare packed strings with implicit lengths in "a" and "b" using the control in "imm8", and store the generated mask in "dst"
  • _mm_cmpistro Compare packed strings with implicit lengths in "a" and "b" using the control in "imm8"
  • _mm_cmpistrs Compare packed strings with implicit lengths in "a" and "b" using the control in "imm8"
  • _mm_cmpistrz Compare packed strings with implicit lengths in "a" and "b" using the control in "imm8"


Swizzle

B E I P S T U

B

  • _mm_blend_epi16 Blend packed 16-bit integers from "a" and "b" using control mask "imm8"
  • _mm256_blend_epi16 Blend packed 16-bit integers from "a" and "b" within 128-bit lanes using control mask "imm8"
  • _mm_blend_epi32 Blend packed 32-bit integers from "a" and "b" using control mask "imm8"
  • _mm256_blend_epi32 Blend packed 32-bit integers from "a" and "b" using control mask "imm8"
  • _mm_blend_pd Blend packed double-precision floating-point elements from "a" and "b" using control mask "imm8"
  • _mm256_blend_pd Blend packed double-precision floating-point elements from "a" and "b" using control mask "imm8"
  • _mm_blend_ps Blend packed single-precision floating-point elements from "a" and "b" using control mask "imm8"
  • _mm256_blend_ps Blend packed single-precision floating-point elements from "a" and "b" using control mask "imm8"
  • _mm_blendv_epi8 Blend packed 8-bit integers from "a" and "b" using "mask", and store the results in "dst"
  • _mm256_blendv_epi8 Blend packed 8-bit integers from "a" and "b" using "mask", and store the results in "dst"
  • _mm_blendv_pd Blend packed double-precision floating-point elements from "a" and "b" using "mask"
  • _mm256_blendv_pd Blend packed double-precision floating-point elements from "a" and "b" using "mask"
  • _mm_blendv_ps Blend packed single-precision floating-point elements from "a" and "b" using "mask"
  • _mm256_blendv_ps Blend packed single-precision floating-point elements from "a" and "b" using "mask"
  • _mm_broadcastb_epi8 Broadcast the low packed 8-bit integer from "a" to all elements of "dst"
  • _mm256_broadcastb_epi8 Broadcast the low packed 8-bit integer from "a" to all elements of "dst"
  • _mm_broadcastd_epi32 Broadcast the low packed 32-bit integer from "a" to all elements of "dst"
  • _mm256_broadcastd_epi32 Broadcast the low packed 32-bit integer from "a" to all elements of "dst"
  • _mm_broadcastq_epi64 Broadcast the low packed 64-bit integer from "a" to all elements of "dst"
  • _mm256_broadcastq_epi64 Broadcast the low packed 64-bit integer from "a" to all elements of "dst"
  • _mm_broadcastsd_pd Broadcast the low double-precision floating-point element from "a" to all elements of "dst"
  • _mm256_broadcastsd_pd Broadcast the low double-precision floating-point element from "a" to all elements of "dst"
  • _mm_broadcastsi128_si256 Broadcast 128 bits of integer data from "a" to all 128-bit lanes in "dst"
  • _mm256_broadcastsi128_si256 Broadcast 128 bits of integer data from "a" to all 128-bit lanes in "dst"
  • _mm_broadcastss_ps Broadcast the low single-precision floating-point element from "a" to all elements of "dst"
  • _mm256_broadcastss_ps Broadcast the low single-precision floating-point element from "a" to all elements of "dst"
  • _mm_broadcastw_epi16 Broadcast the low packed 16-bit integer from "a" to all elements of "dst"
  • _mm256_broadcastw_epi16 Broadcast the low packed 16-bit integer from "a" to all elements of "dst"

E

  • _mm_extract_epi8 Extract an 8-bit integer from "a", selected with "imm8", and store the result in the lower element of "dst"
  • _mm256_extract_epi8 Extract an 8-bit integer from "a", selected with "index", and store the result in "dst"
  • _mm_extract_epi16 Extract a 16-bit integer from "a", selected with "imm8", and store the result in the lower element of "dst"
  • _mm256_extract_epi16 Extract a 16-bit integer from "a", selected with "index", and store the result in "dst"
  • _mm_extract_epi32 Extract a 32-bit integer from "a", selected with "imm8", and store the result in "dst"
  • _mm256_extract_epi32 Extract a 32-bit integer from "a", selected with "index", and store the result in "dst"
  • _mm_extract_epi64 Extract a 64-bit integer from "a", selected with "imm8", and store the result in "dst"
  • _mm256_extract_epi64 Extract a 64-bit integer from "a", selected with "index", and store the result in "dst"
  • _mm_extract_pi16 Extract a 16-bit integer from "a", selected with "imm8", and store the result in the lower element of "dst"
  • _mm_extract_ps Extract a single-precision floating-point element from "a", selected with "imm8"
  • _mm256_extractf128_pd Extract 128 bits (composed of 2 packed double-precision floating-point elements) from "a", selected with "imm8"
  • _mm256_extractf128_ps Extract 128 bits (composed of 4 packed single-precision floating-point elements) from "a", selected with "imm8"
  • _mm256_extractf128_si256 Extract 128 bits (composed of integer data) from "a", selected with "imm8"
  • _mm256_extracti128_si256 Extract 128 bits (composed of integer data) from "a", selected with "imm8"

I

  • _mm_insert_epi8 Copy "a" to "dst", and insert the lower 8-bit integer from "i" into "dst" at the location specified by "imm8"
  • _mm256_insert_epi8 Copy "a" to "dst", and insert the 8-bit integer "i" into "dst" at the location specified by "index"
  • _mm_insert_epi16 Copy "a" to "dst", and insert the 16-bit integer "i" into "dst" at the location specified by "imm8"
  • _mm256_insert_epi16 Copy "a" to "dst", and insert the 16-bit integer "i" into "dst" at the location specified by "index"
  • _mm_insert_epi32 Copy "a" to "dst", and insert the 32-bit integer "i" into "dst" at the location specified by "imm8"
  • _mm256_insert_epi32 Copy "a" to "dst", and insert the 32-bit integer "i" into "dst" at the location specified by "index"
  • _mm_insert_epi64 Copy "a" to "dst", and insert the 64-bit integer "i" into "dst" at the location specified by "imm8"
  • _mm256_insert_epi64 Copy "a" to "dst", and insert the 64-bit integer "i" into "dst" at the location specified by "index"
  • _mm_insert_pi16 Copy "a" to "dst", and insert the 16-bit integer "i" into "dst" at the location specified by "imm8"
  • _mm_insert_ps Copy "a" to "tmp", then insert a single-precision floating-point element from "b" into "tmp" using the control in "imm8"
  • _mm256_insertf128_pd Copy "a" to "dst", then insert 128 bits (composed of 2 packed double-precision floating-point elements) from "b" into "dst" at the location specified by "imm8"
  • _mm256_insertf128_ps Copy "a" to "dst", then insert 128 bits (composed of 4 packed single-precision floating-point elements) from "b" into "dst" at the location specified by "imm8"
  • _mm256_insertf128_si256 Copy "a" to "dst", then insert 128 bits from "b" into "dst" at the location specified by "imm8"
  • _mm256_inserti128_si256 Copy "a" to "dst", then insert 128 bits (composed of integer data) from "b" into "dst" at the location specified by "imm8"

P

  • _mm256_permute_pd Shuffle double-precision floating-point elements in "a" within 128-bit lanes using the control in "imm8"
  • _mm_permute_pd Shuffle double-precision floating-point elements in "a" using the control in "imm8"
  • _mm256_permute_ps Shuffle single-precision floating-point elements in "a" within 128-bit lanes using the control in "imm8"
  • _mm_permute_ps Shuffle single-precision floating-point elements in "a" using the control in "imm8"
  • _mm256_permute2f128_pd Shuffle 128-bits (composed of 2 packed double-precision floating-point elements) selected by "imm8" from "a" and "b"
  • _mm256_permute2f128_ps Shuffle 128-bits (composed of 4 packed single-precision floating-point elements) selected by "imm8" from "a" and "b"
  • _mm256_permute2f128_si256 Shuffle 128-bits (composed of integer data) selected by "imm8" from "a" and "b"
  • _mm256_permute2x128_si256 Shuffle 128-bits (composed of integer data) selected by "imm8" from "a" and "b"
  • _mm256_permute4x64_epi64 Shuffle 64-bit integers in "a" across lanes using the control in "imm8"
  • _mm256_permute4x64_pd Shuffle double-precision floating-point elements in "a" across lanes using the control in "imm8"
  • _mm256_permutevar_pd Shuffle double-precision floating-point elements in "a" within 128-bit lanes using the control in "b"
  • _mm_permutevar_pd Shuffle double-precision floating-point elements in "a" using the control in "b"
  • _mm256_permutevar_ps Shuffle single-precision floating-point elements in "a" within 128-bit lanes using the control in "b"
  • _mm_permutevar_ps Shuffle single-precision floating-point elements in "a" using the control in "b"
  • _mm256_permutevar8x32_epi32 Shuffle 32-bit integers in "a" across lanes using the corresponding index in "idx"
  • _mm256_permutevar8x32_ps Shuffle single-precision floating-point elements in "a" across lanes using the corresponding index in "idx"
  • _m_pextrw Extract a 16-bit integer from "a", selected with "imm8", and store the result in the lower element of "dst"
  • _m_pinsrw Copy "a" to "dst", and insert the 16-bit integer "i" into "dst" at the location specified by "imm8"
  • _m_pshufw Shuffle 16-bit integers in "a" using the control in "imm8", and store the results in "dst"
  • _m_punpckhbw Unpack and interleave 8-bit integers from the high half of "a" and "b"
  • _m_punpckhdq Unpack and interleave 32-bit integers from the high half of "a" and "b"
  • _m_punpckhwd Unpack and interleave 16-bit integers from the high half of "a" and "b"
  • _m_punpcklbw Unpack and interleave 8-bit integers from the low half of "a" and "b"
  • _m_punpckldq Unpack and interleave 32-bit integers from the low half of "a" and "b"
  • _m_punpcklwd Unpack and interleave 16-bit integers from the low half of "a" and "b"

S

  • _mm_shuffle_epi8 Shuffle packed 8-bit integers in "a" according to shuffle control mask in the corresponding 8-bit element of "b"
  • _mm256_shuffle_epi8 Shuffle 8-bit integers in "a" within 128-bit lanes according to shuffle control mask in the corresponding 8-bit element of "b"
  • _mm_shuffle_epi32 Shuffle 32-bit integers in "a" using the control in "imm8", and store the results in "dst"
  • _mm256_shuffle_epi32 Shuffle 32-bit integers in "a" within 128-bit lanes using the control in "imm8"
  • _mm_shuffle_pd Shuffle double-precision floating-point elements using the control in "imm8"
  • _mm256_shuffle_pd Shuffle double-precision floating-point elements within 128-bit lanes using the control in "imm8"
  • _mm_shuffle_pi8 Shuffle packed 8-bit integers in "a" according to shuffle control mask in the corresponding 8-bit element of "b"
  • _mm_shuffle_pi16 Shuffle 16-bit integers in "a" using the control in "imm8", and store the results in "dst"
  • _mm_shuffle_ps Shuffle single-precision floating-point elements in "a" using the control in "imm8"
  • _mm256_shuffle_ps Shuffle single-precision floating-point elements in "a" within 128-bit lanes using the control in "imm8"
  • _mm_shufflehi_epi16 Shuffle 16-bit integers in the high 64 bits of "a" using the control in "imm8"
  • _mm256_shufflehi_epi16 Shuffle 16-bit integers in the high 64 bits of 128-bit lanes of "a" using the control in "imm8"
  • _mm_shufflelo_epi16 Shuffle 16-bit integers in the low 64 bits of "a" using the control in "imm8"
  • _mm256_shufflelo_epi16 Shuffle 16-bit integers in the low 64 bits of 128-bit lanes of "a" using the control in "imm8"

T

  • _MM_TRANSPOSE4_PS Macro: Transpose the 4x4 matrix formed by the 4 rows of single-precision floating-point elements in "row0", "row1", "row2", and "row3", and store the transposed matrix in these vectors ("row0" now contains column 0, etc

U

  • _mm_unpackhi_epi8 Unpack and interleave 8-bit integers from the high half of "a" and "b"
  • _mm256_unpackhi_epi8 Unpack and interleave 8-bit integers from the high half of each 128-bit lane in "a" and "b"
  • _mm_unpackhi_epi16 Unpack and interleave 16-bit integers from the high half of "a" and "b"
  • _mm256_unpackhi_epi16 Unpack and interleave 16-bit integers from the high half of each 128-bit lane in "a" and "b"
  • _mm_unpackhi_epi32 Unpack and interleave 32-bit integers from the high half of "a" and "b"
  • _mm256_unpackhi_epi32 Unpack and interleave 32-bit integers from the high half of each 128-bit lane in "a" and "b"
  • _mm_unpackhi_epi64 Unpack and interleave 64-bit integers from the high half of "a" and "b"
  • _mm256_unpackhi_epi64 Unpack and interleave 64-bit integers from the high half of each 128-bit lane in "a" and "b"
  • _mm_unpackhi_pd Unpack and interleave double-precision floating-point elements from the high half of "a" and "b"
  • _mm256_unpackhi_pd Unpack and interleave double-precision floating-point elements from the high half of each 128-bit lane in "a" and "b"
  • _mm_unpackhi_pi8 Unpack and interleave 8-bit integers from the high half of "a" and "b"
  • _mm_unpackhi_pi16 Unpack and interleave 16-bit integers from the high half of "a" and "b"
  • _mm_unpackhi_pi32 Unpack and interleave 32-bit integers from the high half of "a" and "b"
  • _mm_unpackhi_ps Unpack and interleave single-precision floating-point elements from the high half "a" and "b"
  • _mm256_unpackhi_ps Unpack and interleave single-precision floating-point elements from the high half of each 128-bit lane in "a" and "b"
  • _mm_unpacklo_epi8 Unpack and interleave 8-bit integers from the low half of "a" and "b"
  • _mm256_unpacklo_epi8 Unpack and interleave 8-bit integers from the low half of each 128-bit lane in "a" and "b"
  • _mm_unpacklo_epi16 Unpack and interleave 16-bit integers from the low half of "a" and "b"
  • _mm256_unpacklo_epi16 Unpack and interleave 16-bit integers from the low half of each 128-bit lane in "a" and "b"
  • _mm_unpacklo_epi32 Unpack and interleave 32-bit integers from the low half of "a" and "b"
  • _mm256_unpacklo_epi32 Unpack and interleave 32-bit integers from the low half of each 128-bit lane in "a" and "b"
  • _mm_unpacklo_epi64 Unpack and interleave 64-bit integers from the low half of "a" and "b"
  • _mm256_unpacklo_epi64 Unpack and interleave 64-bit integers from the low half of each 128-bit lane in "a" and "b"
  • _mm_unpacklo_pd Unpack and interleave double-precision floating-point elements from the low half of "a" and "b"
  • _mm256_unpacklo_pd Unpack and interleave double-precision floating-point elements from the low half of each 128-bit lane in "a" and "b"
  • _mm_unpacklo_pi8 Unpack and interleave 8-bit integers from the low half of "a" and "b"
  • _mm_unpacklo_pi16 Unpack and interleave 16-bit integers from the low half of "a" and "b"
  • _mm_unpacklo_pi32 Unpack and interleave 32-bit integers from the low half of "a" and "b"
  • _mm_unpacklo_ps Unpack and interleave single-precision floating-point elements from the low half of "a" and "b"
  • _mm256_unpacklo_ps Unpack and interleave single-precision floating-point elements from the low half of each 128-bit lane in "a" and "b"


Trigonometry

A C H S T

A

  • _mm_acos_pd Compute the inverse cosine of packed double-precision floating-point elements in "a" expressed in radians
  • _mm256_acos_pd Compute the inverse cosine of packed double-precision floating-point elements in "a"
  • _mm_acos_ps Compute the inverse cosine of packed single-precision floating-point elements in "a" expressed in radians
  • _mm256_acos_ps Compute the inverse cosine of packed single-precision floating-point elements in "a" expressed in radians
  • _mm_acosh_pd Compute the inverse hyperbolic cosine of packed double-precision floating-point elements in "a" expressed in radians
  • _mm256_acosh_pd Compute the inverse hyperbolic cosine of packed double-precision floating-point elements in "a" expressed in radians
  • _mm_acosh_ps Compute the inverse hyperbolic cosine of packed single-precision floating-point elements in "a" expressed in radians
  • _mm256_acosh_ps Compute the inverse hyperbolic cosine of packed single-precision floating-point elements in "a" expressed in radians
  • _mm_asin_pd Compute the inverse sine of packed double-precision floating-point elements in "a" expressed in radians
  • _mm256_asin_pd Compute the inverse sine of packed double-precision floating-point elements in "a" expressed in radians
  • _mm_asin_ps Compute the inverse sine of packed single-precision floating-point elements in "a" expressed in radians
  • _mm256_asin_ps Compute the inverse sine of packed single-precision floating-point elements in "a" expressed in radians
  • _mm_asinh_pd Compute the inverse hyperbolic sine of packed double-precision floating-point elements in "a" expressed in radians
  • _mm256_asinh_pd Compute the inverse hyperbolic sine of packed double-precision floating-point elements in "a" expressed in radians
  • _mm_asinh_ps Compute the inverse hyperbolic sine of packed single-precision floating-point elements in "a" expressed in radians
  • _mm256_asinh_ps Compute the inverse hyperbolic sine of packed single-precision floating-point elements in "a" expressed in radians
  • _mm_atan_pd Compute the inverse tangent of packed double-precision floating-point elements in "a" expressed in radians
  • _mm256_atan_pd Compute the inverse tangent of packed double-precision floating-point elements in "a" expressed in radians
  • _mm_atan_ps Compute the inverse tangent of packed single-precision floating-point elements in "a" expressed in radians
  • _mm256_atan_ps Compute the inverse tangent of packed single-precision floating-point elements in "a" expressed in radians
  • _mm_atan2_pd Compute the inverse tangent of packed double-precision floating-point elements in "a" divided by packed elements in "b"
  • _mm256_atan2_pd Compute the inverse tangent of packed double-precision floating-point elements in "a" divided by packed elements in "b"
  • _mm_atan2_ps Compute the inverse tangent of packed single-precision floating-point elements in "a" divided by packed elements in "b"
  • _mm256_atan2_ps Compute the inverse tangent of packed single-precision floating-point elements in "a" divided by packed elements in "b"
  • _mm_atanh_pd Compute the inverse hyperbolic tangent of packed double-precision floating-point elements in "a" expressed in radians
  • _mm256_atanh_pd Compute the inverse hyperbolic tangent of packed double-precision floating-point elements in "a" expressed in radians
  • _mm_atanh_ps Compute the inverse hyperbolic tangent of packed single-precision floating-point elements in "a" expressed in radians
  • _mm256_atanh_ps Compute the inverse hyperbolic tangent of packed single-precision floating-point elements in "a" expressed in radians

C

  • _mm_cos_pd Compute the cosine of packed double-precision floating-point elements in "a" expressed in radians
  • _mm256_cos_pd Compute the cosine of packed double-precision floating-point elements in "a" expressed in radians
  • _mm_cos_ps Compute the cosine of packed single-precision floating-point elements in "a" expressed in radians
  • _mm256_cos_ps Compute the cosine of packed single-precision floating-point elements in "a" expressed in radians
  • _mm_cosd_pd Compute the cosine of packed double-precision floating-point elements in "a" expressed in degrees
  • _mm256_cosd_pd Compute the cosine of packed double-precision floating-point elements in "a" expressed in degrees
  • _mm_cosd_ps Compute the cosine of packed single-precision floating-point elements in "a" expressed in degrees
  • _mm256_cosd_ps Compute the cosine of packed single-precision floating-point elements in "a" expressed in degrees
  • _mm_cosh_pd Compute the hyperbolic cosine of packed double-precision floating-point elements in "a" expressed in radians
  • _mm256_cosh_pd Compute the hyperbolic cosine of packed double-precision floating-point elements in "a" expressed in radians
  • _mm_cosh_ps Compute the hyperbolic cosine of packed single-precision floating-point elements in "a" expressed in radians
  • _mm256_cosh_ps Compute the hyperbolic cosine of packed single-precision floating-point elements in "a" expressed in radians

H

  • _mm_hypot_pd Compute the length of the hypotenous of a right triangle, with the lengths of the other two sides of the triangle stored as packed double-precision floating-point elements in "a" and "b"
  • _mm256_hypot_pd Compute the length of the hypotenous of a right triangle, with the lengths of the other two sides of the triangle stored as packed double-precision floating-point elements in "a" and "b"
  • _mm_hypot_ps Compute the length of the hypotenous of a right triangle, with the lengths of the other two sides of the triangle stored as packed single-precision floating-point elements in "a" and "b"
  • _mm256_hypot_ps Compute the length of the hypotenous of a right triangle, with the lengths of the other two sides of the triangle stored as packed single-precision floating-point elements in "a" and "b"

S

  • _mm_sin_pd Compute the sine of packed double-precision floating-point elements in "a" expressed in radians
  • _mm256_sin_pd Compute the sine of packed double-precision floating-point elements in "a" expressed in radians
  • _mm_sin_ps Compute the sine of packed single-precision floating-point elements in "a" expressed in radians
  • _mm256_sin_ps Compute the sine of packed single-precision floating-point elements in "a" expressed in radians
  • _mm_sincos_pd Compute the sine and cosine of packed double-precision floating-point elements in "a" expressed in radians, store the sine in "dst", and store the cosine into memory at "mem_addr"
  • _mm256_sincos_pd Compute the sine and cosine of packed double-precision floating-point elements in "a" expressed in radians, store the sine in "dst", and store the cosine into memory at "mem_addr"
  • _mm_sincos_ps Compute the sine and cosine of packed single-precision floating-point elements in "a" expressed in radians, store the sine in "dst", and store the cosine into memory at "mem_addr"
  • _mm256_sincos_ps Compute the sine and cosine of packed single-precision floating-point elements in "a" expressed in radians, store the sine in "dst", and store the cosine into memory at "mem_addr"
  • _mm_sind_pd Compute the sine of packed double-precision floating-point elements in "a" expressed in degrees
  • _mm256_sind_pd Compute the sine of packed double-precision floating-point elements in "a" expressed in degrees
  • _mm_sind_ps Compute the sine of packed single-precision floating-point elements in "a" expressed in degrees
  • _mm256_sind_ps Compute the sine of packed single-precision floating-point elements in "a" expressed in degrees
  • _mm_sinh_pd Compute the hyperbolic sine of packed double-precision floating-point elements in "a" expressed in radians
  • _mm256_sinh_pd Compute the hyperbolic sine of packed double-precision floating-point elements in "a" expressed in radians
  • _mm_sinh_ps Compute the hyperbolic sine of packed single-precision floating-point elements in "a" expressed in radians
  • _mm256_sinh_ps Compute the hyperbolic sine of packed single-precision floating-point elements in "a" expressed in radians

T

  • _mm_tan_pd Compute the tangent of packed double-precision floating-point elements in "a" expressed in radians
  • _mm256_tan_pd Compute the tangent of packed double-precision floating-point elements in "a" expressed in radians
  • _mm_tan_ps Compute the tangent of packed single-precision floating-point elements in "a" expressed in radians
  • _mm256_tan_ps Compute the tangent of packed single-precision floating-point elements in "a" expressed in radians
  • _mm_tand_pd Compute the tangent of packed double-precision floating-point elements in "a" expressed in degrees
  • _mm256_tand_pd Compute the tangent of packed double-precision floating-point elements in "a" expressed in degrees
  • _mm_tand_ps Compute the tangent of packed single-precision floating-point elements in "a" expressed in degrees
  • _mm256_tand_ps Compute the tangent of packed single-precision floating-point elements in "a" expressed in degrees
  • _mm_tanh_pd Compute the hyperbolic tangent of packed double-precision floating-point elements in "a" expressed in radians
  • _mm256_tanh_pd Compute the hyperbolic tangent of packed double-precision floating-point elements in "a" expressed in radians
  • _mm_tanh_ps Compute the hyperbolic tangent of packed single-precision floating-point elements in "a" expressed in radians
  • _mm256_tanh_ps Compute the hyperbolic tangent of packed single-precision floating-point elements in "a" expressed in radians